Copyright O 1 B 7 3 Ameriemn Telephone and Telegraph Company THE BELL STBIXII TECHNICAL JODSNAL

Vol. 6 2 , No. β, July-AuguBt, 1 9 7 3 Printed in U.S.A.

Switching Networks of Planar Shifting Arrays

By R. S. K R U P P and L. A. T O M K O (Manuscript received June 2, 1072)

An array of shift registers that may operate in two orthogonal directions can be ccdled a planar shifting array. This aríicle shows how two basic building blocks, fashioned from planar shifting arrays, may be inter­connected to form a time-division stoitching network of arbitrary size. The characteristics of magnetic bubble and charge-coupled devices are com­patible with the concept of planar arrays, and it is in these emerging technologies that switching networks of planar shifting arrays may become practical.

I . I N T R O D U C T I O N

Switching machines in the Bell System have grown in bo th numbe r and capaci ty to mee t t h e growing traffic demand . Ear ly machines con­sisted of a small amoun t of distr ibuted logic embodied in electrome­chanical devices bu t , as technology has permit ted , the machines have evolved into largely solid s t a te systems with centra l processor control . T h e environmen t in which switching machines mus t operate has also changed from a relatively small collection of analog voice grade circuits to an overwhelming numbe r of circuits of various bandwidths with an increasing proportion of digital facilities. I t is the purpose of this paper to look a t a possible future realization of one portion of a switching machine t h a t migh t have advantages in meeting future requirements in a largely digital environment .

We may consider t h a t a switching machine consists of three major subdivisions . One is a switching network , which makes cross connec­t ions for each call. A controller, used to direct t he operation of t he network , is another . Finally , some interface is needed between t he network , the controller, and external circuits . The subjec t of this pape r is a switching network , one t ha t may reduce t he complexity of t he tasks of t h e other two subdivisions of a switching machine as well as have advantages of its own in conjunction with some emerging technologies.

ΘΘ1

ΘΘ2 Τ Η Β B B L L S T B T B M T B C H N I C A L J O U B N A L , J U L T - A U G U S T 1973

Most switching networks in the pas t have been "space-division" ne t ­works; t ha t is, a spatially distinct pa th is assigned to each of the m a n y simultaneous calls t h a t might pass through t h e network. T h e present paper, however, refers to a "t ime-division" network, in which inter­leaved samples of several simultaneous calls m a y share par t s of the same spatiaJ pa th . A potential savings of equipment is implied by this t ime-sharing process, and its merits have already resulted in plans for a large-scale digital electronic switching machine with some t ime shar­ing in the switching network (the No. 4 ESS, now under development in Bell Laborator ies) . '

T h e possibility of constructing a somewhat different time-division digital switching network from two basic building blocks is explored in this paper. T h e two blocks, or subsystems, m a y be realized in the form of planar shifting arrays which are basicaUy shift registers t h a t can perform shifting operations in two orthogonal directions. These capa­bilities seem to be consistent with those of the emerging technologies of magnetic bubble and charge-coupled d e v i c e s , ' ' which do shift d a t a on a plane. Although these types of devices m a y be part icularly well suited for use as planar shifting arrays , t he concepts presented below are no t restricted to implementat ion b y a n y part icular t ype of device.

T h e first building block, a time-slot interchanger, is t he only actual switching element in the system. The other type of block, a mass serial-to-parallel converter, performs a time-space mapping and thereby acts as the interconnection links between successive stages of time-slot interchangers. Networks of a rb i t ra ry size and blocking probabil i ty can be fashioned from these two building blocks.

I n the sections t h a t follow, the basic interconnections of time-slot interchangers and mass serial-to-parallel converters necessary to per­form multistage switching fimctions are explained, and some logical details of the two building blocks a re presented. Although t h e network is only a p a r t of a to ta l switching machine, the concepts presented here m a y simplify the interface with digital external circuits and m a y help reduce the burden on the central control processor.

I I . N B T W O B S A B C H I T E C T U B B

I n this section, mult is tage switching network structures are described t h a t use pure time-division techniques only. Such a network m a y be diagrammed using two types of functional blocks, as in Figure 1.

Each block labelled TSI denotes one time-slot interchanger—a familiar subsystem in t h e time-division switching ar t . T h e a t t ached nota t ion Ν X Μ indicates t h a t the T S I rearranges words from an

SWITCHING NETWORKS OF PLANAR ARRAYS 993

TSI

" T "

_ 1 _ TSI

τ

TSI TSI

1

S-P S-P

1 1 S-P

*

• S-P

1 1 1 1

S-P S-P

1

1

TSI

J L

] — O U T ,

TSI •OUT,

N>M LxL MxN

Fig. 1—^Three-stage switching network.

iV-slot inpu t frame into an ilZ-slot ou tpu t frame. The T S I is the only actua l switching elemen t in the network . I t corresponds to an X Af ar ray of crosspoints in an analogous space-division network .

Each block labelled S - P denotes a mass serial-to-parallel converter . The S -P does no t perform switching functions, bu t corresponds to the links between crosspoint stages in a mult is tage space-division network . I t s basic function is t h a t of interchanging t h e space and t ime co­ordinates of each word it handles . As inputs to one S -P , the figure shows L time-division multiplexed lines, each carrying Μ t ime slots per frame. The ou tpu t is Μ lines with L slots per frame. An inpu t word in slot m of line / will always be routed by the S - P to slot t of ou tpu t line m, where 1 ^ m ^ Μ and I ^ t ^ L. Thus , t he m th words of all L inpu t frames are combined to form a single ou tpu t frame on line m, and conversely the inpu t frame on line t gets dis tr ibuted into t he ith slots of all the Μ ou tpu t frames.

A three-stage switching network is d iagrammed in Figure 1 using the two functional blocks. T o i l lustrate i ts operation , suppose t h a t a word in slot η of inpu t line t mus t be sen t to t ime slot ν on ou tpu t line λ, where 1 ^ n,v ^ Ν and 1 ^ f,\ ^ L. Firs t an intermediate t ime slot m is assigned for some 1 g m ^ Λ/, which permits t he middle s tage to complete a connection . Thereafter :

(t) The Ah inpu t TS I switches word η to slot TO. (n ) The first S - P places this word in slot ( on line TO.

(ύ ϊ ) The TOth intermediate T S I switches word f to slot λ. (it)) The second S - P places the word in slot m on line λ. (υ) The Xth ou tpu t TS I switches word m to slot y, and the task is

finished.

T h e portion of t he figure surrounded by a dashed line performs t he same function as t he t ime-shared space-division switch (TSSDS) s tages of t he No . 4 ESS.» T h a t is, all words t h a t enter the first S - P in t ime slot TO will exit the second S - P in t he same slot. I n their passage th rough

994 T H E B E L L S Y S T E M T E C H N I C A L J O U R N A L , J U L Y - A U G U S T 1973

OUT

Fig. 2—Spiderweb graph for Figure 1.

t he S - P ' s and the mth intermediate T S I , however, these words m a y be spatially rearranged to different ou tpu t lines. A direct realization of t h e same TSSDS function using magnetic bubbles has been suggested b y P . I . Bonyhard.«

Figure 2 is the probabil i ty linear g r a p h ' (also called spiderweb or Lee graph) of all pa ths for one call in Figure 1. I t is t he s tandard Lee graph for a three-stage network and yields t h e usual blocking formulas. In part icular , if Μ ^ Ν — I and we assume independent occupancy ρ of all input and ou tpu t t ime slots, t hen a modification of C. Y. Lee's a rgumen t ' yields the mismatch blocking probabil i ty first given b y M. K a r n a u g h ' in 1954:

PB = ( p ' ) " - ' ' + ' [ l - (1 - p)«]»^-^-»(iV - 1 ) ! V Ml(2N - Μ - 2)1. (1)

On the other hand, if Λί ^ iV̂ — 1 and we assume aU intermediate t ime slots m have independent occupancy p , a more appropr ia te esti­m a t e i s :

= [1 - (1 - p ) » ] ' . (2)

When Μ ^ 2N — 1 in Figure 1, Pa vanishes and t h e network is non-blocking.* Figure 3 il lustrates such a case for Μ = 2N. A pa r t of t h e t ime-space interchange is accomplished, no t by t h e S -P , b u t by spli t­t ing each inpu t and ou tpu t T S I into two separate TSI ' s . Now each T S I in t h e network handles inpu t and ou tpu t frames of equal size. This might prove convenient for certain applications or implementat ions. N o t e t h a t Figure 3 m a y also be interpreted as a pair of three-stage net­works whose inputs and outputs are tied in parallel. A third, inactive, network could be placed in parallel as well, and held in reserve against failure of one of the first two.

The re is an unavoidable signal delay of a t least one frame for each stage of the TSI ' s . This could contr ibute t o t h e cost of echo suppression on long toll circuits; however, the dura t ion of the frame itself m a y be shortened within the switch to mit igate this effect.

T h e three-stage network of Figure 1 has a capacity of C = LN terminat ions. Such networks m a y be nested to achieve a higher switch­ing capacity. A five-stage example having capacity C « JLN is dia-

S W I T C H I N G N E T W O R K S O F P L A N A R A R R A Y S 995

IN,

IN,

• a

N x N L x L N x N

Fig. 3—Nonblocking three-stage network.

-OUT,

-OUT,

grammed in Figure 4. Shown are Μ three-stage T S S D S sections within dashed lines, as well as one large overall T S S D S which re­arranges JL words spatially in each of Μ t ime slots. Blocking probabili­t ies for t h e five-stage nested network are obtained b y arguments simi­lar t o those for eqs. (1) and (2), using the spiderweb graph in Figure 4.

A different kind of five-stage network organization is shown in Figure 5. N o section of this network performs t h e TSSDS function. I n fact, a word entering its first S - P in t ime slot m may exit its last S - P in any t ime slot μ for 1 ^ τη,μ ^ M, depending upon the p a t h i t follows through the network. The number M* of possible pairs (m, μ) yields t h e same number of possible pa th s for rout ing a message, as t h e spider-web graph in Figure 5 shows. At full occupancy, this graph reduces to

TT " V J L _

L x K

Η

Λ Γ

-· I I

- Γ Π - 4 - Γ - μ 1

H Η 1

-J J«J K x L M x N

Fig. 4—Nested five-stage network.

996 T H E B E L L S Y S T E M T E C H N I C A L J O U B N A L , J U L Y - A U O U S T 1973

-{ I L

BLOCK j

-CD-NxM

LxM -CD-

JxJ

H I 3 Mx L

C D — f V M E g - n y-BLOCK Γ

MxN

Fig. 5—Crose-connected five-etage network.

Figure 2, b u t with M' = (Λί — JV + 1)* center-stage switches, so t h a t (2) applies wi th link occupancies ρ = N{L — 1)/Af' to yield the fol­lowing blocking probabil i ty expression:

P b = [ 1 - (1 - ρ)«]<ί'-Λ^+υ·. (3)

Thus , parameters L = = 48 and i l / = 60 yield PB < l O " " a t any occupancy level; essentially, this is a nonblocking network. The same parameters in a nested arrangement produce a much higher degree of blocking, P b > 0.027 a t full occupancy, based on (1) for the case ρ = 1.

T o il lustrate operation of the network in Figure 5, suppose t h a t a word in t ime slot η on line ( of input block j mus t be t ransmit ted to slot V on line λ of ou tpu t block Γ for 1 ^ n,v ^ Ν and 1 i t,\ ^ L with 1 ^ j,r ^ J. First , intermediate t ime slots m and μ mus t be chosen for some 1 S τη,μ ^ Af which permits completion of t h e connection. Then TSI ' s in the five stages perform the following switching opera­t ions consecutively t o complete t h e task, as indicated on Figure 5 :

(i) Switch word η into slot m (Stage 1). (n ) Switch word t in to slot μ (Stage 2).

( in ) Switch word j in to slot Γ (Stage 3). (iv) Switch word m into slot λ (Stage 4). (v) Switch word μ into slot ν (Stage 5).

T h e networks of Figures 4 and 5 each have a center section consisting of t he third-stage TSI ' s and the two rows of S -P ' s t o which they

S W I T C H I N G N E T W O R K S O F P L A . N A B A R R A Y S 997

at tach . A total of J independent input and ou tpu t blocks of LN termi­nations each connect to the center. Each pair of blocks consists of an inpu t S -P , an ou tpu t S -P , and their a t tached TSI ' s in the first, second, fourth, and fifth stages. This s t ruc ture immediately suggests an ap­propriate s t ra tegy for growing the network capaci ty in modules of LN terminat ions.

I I I . N E T W O R K P A T H S E A R C H

Section I I mentioned the need to choose one or two intermediate t ime slots m before set t ing u p a message p a t h through the network. This amounts to specifying which of the m a n y possible pa ths in the spider-web graph is currently free and will be used. T h e decision might be made by a central control processor after consulting its memory records of the current s t a tus of the network. I n this section, an a l ternate pro­cedure is described by which some simple operations within the network itself can identify suitable pa ths for routing a new call. A possible ad­vantage is reduced demands upon processor t ime and memory for call processing.

T o provide necessary information about network s ta tus , a "busy-b i t " is used. This is a bi t in each word which travels through t h e net­work with t h a t word and serves to indicate whether or not the word is pa r t of a call currently in progress. T h e busy-bi t m a y occur in every word of a message or less frequently, perhaps every t en th or hundred th frame. For concreteness, assiune the busy-bit is " o n e " for a call in progress and "ze ro" otherwise.

T o determine occupancy of a t ime slot on some line in the network, we merely consult t he busy-bit in t h a t slot. For example, in rout ing a word from input line ( of Figure 1 to ou tpu t line λ, an intermediate t ime slot m was chosen t h a t was vacant bo th a t t he ou tpu t of the tih first-stage TSI and a t the input of the Xth third-stage TSI . Such m m a y be found by comparing the two corresponding s treams of busy-bits. This is il lustrated by Figure 6a for the case / = λ = 1. Ou tpu t from the first input T S I and inpu t to t h e first ou tpu t T S I are sent to a N O R gate. When simultaneous zeroes are found in the busy-bit positions of words m, an ou tpu t pulse is produced b y the gate identifying an available pa th through the network by its t iming.

Other means of sampling and matching busy-bits are possible. For instance, the s t ream of busy-bits from the / t h input TSI will exit the first S - P simultaneously in word t ime t, while the busy-bits entering the second S -P a t word t ime λ are those for the Xth ou tpu t TSI . Hence, t imed sampling pulses to the two S-P ' s can select the two de-

998 T H E B E L L S Y S T E M T E C H N I C A L J O U R N A L , J U L Y - A U G U S T 1973

IN TSI

m

• {NOR)<

TSI

Ν xM

S-P

TSI

r JL TSI

S-P

TSI

IL

TSI

Lx L MxN

OUT ,

OUT ,

Fig. Sa—^Path search in three-stage network.

sired strings of busy-bits ra ther t h a n use spatial selection of an inpu t and ou tpu t T S I . Such an option might serve to reduce t h e amoun t of control and signal wiring associated with the network.

Once an in termediate t ime slot m is chosen, a central processor could issue the necessary orders t o the first-, second-, and third-stage T S I ' s to establish the pa th . B u t again some additional logical appa ra tus in the network could perform the same task. T h e significance of this ob­servation is t h a t the dependence of the network upon external inter­vent ion may be reduced. Indeed, for each new message, the principal external control required would be a specification of which input and ou tpu t terminat ions mus t be connected. Such a s t ructure might lend itself, for example, t o applications in which all processor functions a re performed b y a remote computer t h a t sends its instructions to the net­work over a da t a link.

T h e pa th search procedure in the nested five-stage network of Figure 4 would consist of two nested three-stage p a t h searches. T h a t is, t h e busy-bi t s t reams of the input and ou tpu t TSI ' s are compared, as above, to determine which one m of the Μ in termediate three-stage networks will carry t h e message. Then the mth three-stage network is searched for some intermediate t ime slot 1 ^ k ^ Κ which will complete t h e connection.

A different search procedure is required for the cross-connected net­work of Figure 5, since all M* pa ths in t h e spiderweb graph mus t be tested. This involves sorting the Μ busy-bi t s t reams leaving the second-stage TSI ' s of the input block j by using t h e m as inputs t o an S - P with Af ou tpu t lines. T h e S - P outputs are then compared by a set of O R gates to the Μ busy-bit s t reams entering t h e fourth-stage TSI ' s of t h e ou tpu t block Γ. A "zero" a t word t ime tn from gate μ identifies a pos­sible pa th in Figure 6b. No te tha t , if t ime slot m from the first-stage

SWITCHING NETWORKS OF PLANAR ARRAYS

It— ;w ;w ; m

999

Fig. 6b—^Path search in five-stage network.

T S I or t ime slot μ into t h e fifth-stage T S I is busy, then pa th (m, μ) cannot be used. T o eliminate such possibilities, all t he OR gates should be pulsed during each busy first-stage slot m, and all gates μ correspond­ing to busy fifth-stage slots should be pulsed for the entire frame, as is accomplished in Figure 6b by feeding parallel "ones" t o the S -P . This last pa th search requires only one pass instead of two nested steps.

IV. PLANAR SHIFTING ARRAYS

T o unders tand the role of planar a r ray devices in the reaUzation of the functions described above, it is helpful to s tudy the building blocks a t t he logical level, with a notat ion suggestive of the two-dimensional na ture of the devices. The device technologies mentioned in Section I differ considerably in their physical principles. Nevertheless, certain common features of their operation may be abstracted to aid in discus­sing their use for switching applications. To this end, a "planar shifting a r r a y " (PSA) notat ion will be introduced, exemplified by Figure 7. Circles O represent fixed word-storage locations in one-dimensional or two-dimensional shift registers. Diamonds O s tand for shifting ap ­para tus , which can move the contents of each circle to the next in line, under control of clock pulses A and B. Gates [»^ allow transfer of individual words between the adjacent circles imder control of switch-

1000 T H E B B L L S Y S T E M T E C H N I C A L J O X T B N A L , J U L Y - A U G U S T 1973

IN

OUT

0 < i > 0 < 3 > Ö < S > 0 < H > 0 < S > 0 Θ Θ Θ Θ Θ Θ Ο <Ε> Ο <s> Ο <$> Ο < 5 > Ο < 5 > Ο

β Fig. 7—Switch elemente for time-slot interchanger.

ing signals n. T h e distinction between O and O is one of function ra ther than physical s t ructure . I n this section, a word, ra ther t han a bit , is t h e basic q u a n t u m of information. I t is not necessary to specify whether this word is in a serial or parallel digital representation or some other form.

A basic scheme for performing switching functions in a time-slot interchanger appears in Figure 7. Gates 1 t o 6 allow transfer of inpu t words from a frame stored in the upper shift register into ou tpu t slots in a frame stored in the lower shift register. The input and ou tpu t frames move, relative to one another, in the two adjacent shift registers, and the switching s t ra tegy is : For each input word a, wait unti l its des­tined ou tpu t slot β lies directly underneath and t hen transfer through the appropr ia te gate.

I t is impor tan t to note a part icular diflSculty. If bo th the input and ou tpu t frames are shifted simultaneously, then word o in t h e diagram will pass slot β halfway between gates 3 and 4, so t h a t i t is not possible to transfer. This we will call the "half-word" problem. At least three kinds of solution can be suggested:

(i) Alternate clock pulses A and B, so t h a t only one frame shifts a t a t ime.

OUT

o <£> o <t> o <S> o <3> o <*> O-Θ Θ Θ Θ Θ Θ 0 0 0 0 0 0 Θ Θ Θ Θ Θ Θ • 0 < ί > 0 ^ 0 < Ε > 0 < ί > 0 < ΐ > 0

Fig, 8—Switch elements for time-slot interchanger with buffer.

IN

S W I T C H I N G N E T W O R K S O F P L A N A R A R R A Y S 1001

(n) Omi t one set of clock pulses, say A, so t h a t one frame is held in s ta t ionary buffers,

( m ) Le t each circle contain only a half-word, so t h a t two consecutive locations hold an entire word . Then it is never necessary to transfer between first and second half-word locations .

A fourth solution , based on the technique of bubble expansion , has been found by P . I . Bonyhard.*

The first solution above may be i l lustrated by Figure 7. The basic switching cycle would consist of t he following four s teps :

(i) Diamonds < ^ move the inpu t words r igh t one slot. (Ü) Gates ^ may transfer inpu t words to ou tpu t slots,

( m ) Diamonds < J > move the ou tpu t words left one slot. (w) Gates Θ may transfer input words to ou tpu t slots.

For an ilf-word frame, switching is completed in Μ cycles. Each shift register operates Μ t imes, and the Μ gates each have as many as 2M chances to operate in every frame.

The second solution to the half-word problem is i l lustrated by Figure 8. T h e diamonds < ^ read in an entire input frame, which is stored in buffers 0 by simultaneous operation of all gates [ β ] a t the end of the input frame. Then the following two-step switching cycle:

(t) d iamonds move the ou tpu t words left one slot, (M ) gates (3? may transfer words from buffers to output ,

is repeated 2M t imes, and the Μ gates each have Μ chances to operate in an ilf-word frame. This scheme has the additional advantage t h a t the input and ou tpu t clocks need not be synchronous. Each solution to the half-word problem has advantages with respect to particular hardware.

Figure 9 uses the PSA notat ion to i l lustrate a simple scheme for implementing the S - P function. The S - P shown has L = 4 input lines, each carrying six-word frames, and Μ = & ou tpu t lines, each with four t ime slots per frame. The diamonds operate to load an entire frame into the S - P from each input line. Then the diamonds < e ^ oper­a te to unload an entire frame from the S - P onto each ou tpu t line. Loading and unloading may proceed a t twice the external basic word ra te so t h a t the S - P empties in t ime to receive the next frame, or else an al ternate S -P m a y handle the next frame while the first one is un­loading. Other schemes permit the S -P to load and unload simulta­neously. While the S - P is drawn as a distinct uni t in preceding figures.

1002 T H E B E L L S Y S T E M T E C H N I C A L J O Ü E N A L , J U L Y - A U G U S T 1973

o <$> o <s> o <ε> o <^ o <í> o— ' l i l i l í

OUT, OUT2 OUT3 OUT4 OUT5 ουτβ Fig. 9—Maes serial-to-parallel converter.

only its function need be distinct. T h e S -P as a device m a y be broken u p and its pa r t s integrated onto t h e same chips as t h e various T S I ' s which i t serves. Schemes to obviate the S - P completely using specific device properties have been proposed by W. F . Chow and P . I . Bonyhard.*

V. MEMORY STRUCTURE

I n the switching schemes described above, each gate should operate a t t he same word t imes in each consecutive frame; i t is na tura l to place it under the control of a recirculating local memory. This could consist of a shift register fabricated from the same materials as the switching elements and preferably integrated onto the same chips. Such an ar rangement is diagrammed in Figure 10, using the PSA nota­tion. The switching elements appear a t t he right. The rest of the dia­gram is the local memory a r ray t o control these elements. Each shift register in the control memory moves its contents one word to the right under the action of clock pulse C whenever a pulse A οτ Β occurs. A word in shift register η is read when it reaches the box [V] , which is considered to generate a pulse η t h a t operates gates Q . For example, the gating operations might be realized through repulsion between control bubbles and message bubbles. Gates 0 a t the left s t a r t new words down the shift registers to accomplish recirculation of the local memory.

O <Φ> O <S> O <3> O <^ O <3> O —^ φ ^ <̂ <̂ <̂

0 < t > 0 < t > 0 ' ^ 0 < t > 0 <3> 0^"'3

^ θ θ Φ ^ <̂ O <3> O <s> O <s> O <ε> O <3>o*-'~̂

S W I T C H I N G N E T W O R K S O F P L A N A R A B R A Y S 1003

T h e size of the local memory a r ray depends on t h e numbe r of words Q in each register and t he numbe r R of such registers, which is t h e same as t he numbe r of switching gates . Although t he exac t size depends on t he part icular solution chosen for t h e half-word problem presented above , we can conclude in each case t h a t t he local memory in a T S I grows quadratically in frame size (as QR), while the numbe r of switch­ing elements grows only linearly (as R). Fo r moderate-size frames (say, 20 words or more) , each TS I becomes a large recirculating memory plane with a small quan t i ty of logic elements a t t he edges. A word in t h e contro l memory corresponds mos t closely to a crosspoint in a space-division switch , since t he numbe r of crosspoints also grows as t he square of t he numbe r of circuits, and each crosspoint stores j u s t one bi t of information .

V I . C O N T R O L I N S E R T I O N A N D E R A S U R E

T h e switching operations of a T S I are fixed from frame to frame on a shor t t ime scale (say, thousands of frames) ; thus , the contents of i ts local memory a r ray are fixed. On some longer t ime scale, though , i t is necessary to be able to change portions of local memory ; for instance , in response to external signals emanat ing from a centra l contro l processor.

Specifically, one requires t he capabili ty to address single word posi­tions in t h e local memory in order to close or open a "crosspoint" by writing or erasing a bit . I n t he case of erasure , i t would be sufficient to simultaneously erase all memory locations affecting a given inpu t word , or al ternatively a given ou tpu t slot. This is due to t h e following two properties of t he T S I :

(A) Each inpu t word is switched into one ou tpu t slot a t most . (B) Each ou tpu t slot receives a t mos t one inpu t word .

OUT

0Ε)θ<£>ο<Φ>ο< ·̂··ο<£>

0 [ ϊ ) Ο < ε > Ο < £ > Ο < ^ · · · Ο < ε >

0 E ) O < ^ O ^ O < ^ - - - O < £ >

I

o a o

o a o o a o

IN

Fig. 10—^Recirculating memory array for TSI gates.

1004 T H E B E L L S Y S T E M T E C H N I C A L J O U B N A L , J U L Y - A U G U S T 1973

Θ

Ο[°)0Ι])Ο<£>Ο<ε>···Ο^ΠΘ0(3θ οΒθΕ)ο^ο^· · ·ο<^Ξαοαο

θΕ>0[ϊ)0<5>0<ε>···0<£>[Ι]αθ(!]0 Fig. 11—Addressing and erasure schemes for the T8I local memory.

Hence , one can provide for erasure of a control word wi thou t knowing exactly where i t is in the local memory b y erasing a whole class of words .

T h e fact t h a t local memory recirculates will great ly simplify t h e problem of addressing specific locations, since this allows access to any location from t h e edge of t h e a r ray . Indeed , one eflScient and convenien t scheme would be to build an analog of the switching elements and oper­a te i t "backwards" to inser t control bi ts into the local memory . Inser­tion could be directed by two external control pulses whose t iming would specify an inpu t word and the ou tpu t slot for which it is in­tended . Such an approach is i l lustrated in Figure 11 , in which switch­ing elements are deleted to concentrate a t tent ion on t he memory plane . Contro l insertion elements appear a t the r ight-hand side. A b i t is in­serted in order to control gate η a t word t ime m as follows:

(z) A t the s t a r t of a frame , ® gates a " o n e " in to t he vertical shift register, where i t propagates downward .

(ii) After η of the A clock pulses, gates (7j operate to place t h e " o n e " in buffer Q a t t he r igh t of t h e n th recirculating shift register in local memory .

(Hi) In t h e nex t frame , gates (7] operate with t he with clock pulse C, to place the " o n e " in word m of memory line n. This is indi­cated formally by reading t he " o n e " a t [T] , bu t the actua l details of bi t injection will depend on the t ype of hardware .

I t is clear now t h a t a n y word location in t he local memory m a y be addressed emplojang a pair of time-coded pulses / and J. T h e scheme shown would be part icularly appropr ia te to t h e case of buffered input , since η then becomes the numbe r of the inpu t word to be switched .

SWITCHING NETWORKS OF PLANAR ARRAYS 1005

Indeed, the nth shift register contains only those locations t ha t can affect input word n. By property (A) above, a t most one location on this memory line has nonzero contents. I t is sufficient now to erase the en­tire shift register, by interrupt ing recirculation, for example, before a new control word is inserted.

The left side of Figure 1 1 shows a simple scheme for erasure in the case of buffered input , which also guarantees t ha t a t most one nonzero word is resident in each memory line. Once each frame, the buffers 0 a t the left are loaded with "ones ." Gates 0 then s ta r t these "ones" down the various shift registers a t t he appropr ia te t imes to accomplish recirculation. Clearly, a t most one nonzero word can circulate. To erase memory line n, t he " o n e " is simply deleted in its recirculation buffer for a single frame.

A single time-coded pulse will suffice to specify erasure of any word in the local memory above, if the buffers are loaded serially. Ju s t such an arrangement appears a t the left side. Ga te (T^ enters "ones" in the vertical shift register a t each input word time, and these are loaded into the buffers by gates [«) a t t he s ta r t of each frame. By deleting the Β pulse a t the n th w o r d t i m e , a "ze ro" is sent to the buffer for the n th memory line, erasing it and opening any "crosspoint" which might affect the n th input word. The deletion of pulse Β could coincide with pulse / , which routes a n e w control word t o memory line n. Then the pair of external signals / and J would accomplish erasure together with address insertion. Examples at device level of this procedure have been given by P. I . Bonyhard and W. F . Chow.*

VII. B U S Y - B I T S FOR PATH TAKE-DOWN

The preceding section considered two schemes for erasure in the local memory:

(t) A direct instruction from the central control processor. (M) Automatic erasure when a new control word is inserted.

A third scheme is to provide for automat ic erasure when the message t h a t is being switched terminates. This might be accomplished through use of the busy-bits introduced previously. Recirculation of a word in local memory would be made contingent on the presence of a " o n e " in the busy-bit position of the particular input word which t ha t control word switches. When the message terminates, the pa th along which it was routed through the switch is taken down simply by sending through one word with a "zero" busy-bit. This function is analogous to t ha t of

1006 ΤΗΒ BBLL ΘΤβΤΒΗ TBCHNICAL JOUBNAL, JULT-AUGUST 1973

t he sleeve-lead in electromechanical switches and might be considered an "electronic sleeve-lead" appUcation of busy-bits .

This s t ra tegy of making recirculation in t h e local memory contingent on busy-bits can be easily implemented in Figure 11. I t is merely neces­sary t o read t h e busy-bi t s t ream for t h e inpu t frame into the left-hand shift register and load it into the recirculation buffers once each frame. Now each busy-bit will prime the recirculation of the memory register associated with the word of t h a t busy-bit .

VIII. CONCLUSION

T h e possibiUty of constructing a time-division switching network using two building blocks of planar arrays was discussed in this paper. The compatibiUty of planar arrays with the emerging technologies of magnetic bubble, charge-coupled, and bucket-brigade d e v i c e s ' ' m a y lead to appUcation of these concepts in the construction of relatively inexpensive large-capacity switching machines.

T h e need for external connections to a network composed of these building blocks can be minimized by including pa th search and p a t h maintenance functions with t h e blocks. As a result, a relatively smaU amoun t of information mus t be exchanged between the network and the supervisory processor, and some of the processing burden on t h e controller is shared by t h e network itself.

Some examples of compatible network archi tecture have been given, al though no specific design is proposed. The process of switching is ac­complished by time-slot interchangers within the network ra ther t h a n a space-division crosspoint array, b u t t h e task performed b y some of the described subnetworks, when viewed from their external ports, is t he same as a t ime-shared space-division switch.

ACKNOWLBDGMBNTS

We wish to t h a n k the reviewers and referee for their comments and suggestions. We have received invaluable advice on the properties and capabilities of bucket-brigade and charge-coupled devices from W. F . Chow, C. H. Sequin, G. E . Smith, and M. F . Tompset t , and on mag­netic bubble devices from P . I . Bonyhard, who also suggested im­provements in the network design.

BBFBBBNCBS

1. Vaughan, H. K, "An Introduction to No. 4 ESS," paper jpresented at the Inter­national Switching Sympoeium, Massachuaetts Institute of Technology, Cambridge, Mass., June 6,1972.

SWITCHINQ NETWORKS OF PLANAR ARRAYS 1007

2. Bobeck, A. H., Fischer, R. F., Pemeski, A. J., Remeika, J. P., and Van Uitert, L. G., "Application of Orthoferrites to Domain Wall Devices," IEEE Trans. Magnetics, Af<v-tf, No. 3 (September 1969), pp. 644-553.

3. Sangster, F. L. J., apd Teer, Κ., "Bucket Brigade Electronics—New PoesibiUties for Delay, Time Axis Conversion and Scanmng," IEEE J. Solid State Circuits, aC-4, No. 3 (June 1969).

4. Chow, W. F., and Bonyhard, P. I., unpublished work (1971) and private conversations.

5. Lee, C. Y., "Analysis of Switching Networks," B.S.T.J., S4, No. 6 (November 1955), pp. 1287-1315.

6. Karnaugh, M., unpublished work, August 1954. 7. Qoe, Chelee, "A Study of Non-Blocking Switching Networks," B.8.T.J., S«,

No. 2 (M^roh 1953), pp. 406-124.