. 56 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 41, NO. 1, JANUARY 1994

Scaling of Poly-Encapsulated LOCOS for 0.35 pm CMOS Technology

P. U. Kenkare, C. Mazurk, J. D. Hayden, J. R. Pfiester, J. KO, H. C. Kirsch, S. A. Ajuria, P. Crabtree, and T. Vuong

Abstract- We demonstrate the scaling of Poly-Encapsulated LOCOS (PELOX) for 0.35 pm CMOS technology without detri- mental effects on gate oxide and shallow source/drain junction integrity. As-grown bird’s beak punchthrough is shown to fun- damentally limit the scalability of LOCOS-based schemes for narrow nitride features. A quantitative comparison of bird’s beak punchthrough is made between LOCOS, Poly-Buffer LOCOS (PBL), and PELOX. The PELOX scalability is emphasized by evaluating the impact of the polysilicon-sealed cavity length for narrow nitride features. We present the realization of a 1 pm active/isolation pitch fully meeting the geometry and off-leakage requirements of 0.35 pm CMOS technologies ( V D S 5 5 V). This field-implant-free isolation module avoids unnecessary process complexity by successfully integrating scaled PELOX with the split well-drive-in scheme. A highlight of this new approach is that the NMOSFET characteristics are largely width-independent down to 0.3 pm dimensions.

I. INTRODUCTION IGH-density 0.35 pm CMOS and BiCMOS processes H require an isolation module capable of achieving 5 1 pm

active pitch [ 11. The appropriate choice of the isolation scheme for achieving this tight pitch is crucial because it has a far reaching impact on the front end integrity. For example, isolation-induced stresses in the substrate may lead to crystal defect formation jeopardizing diode and/or gate oxide quality. In addition, any resulting topography adds to the depth-of- focus limitations the lithography will need to overcome for fine feature patteming in the subsequent process steps.

Trench isolation [2] strategies have demonstrated the tightest pitches; however, LOCOS-based schemes [7] such as PBL (Poly-Buffer LOCOS) 131, Reverse L-Shape Sealed PBL [4], and PELOX (Poly-Encapsulated LOCOS) 151-[7] require less process complexity and are more manufacturable. A major challenge for the integration of LOCOS-based isolation is the fabrication of narrow active features without degrading isolation of the small field regions, which are especially vulnerable to as-grown field oxide (FOX) thinning [8]. Char- acterization of LOCOS-based schemes generally emphasize the final encroachment following oxide etchbacks. However, we show that the as-grown encroachment can fundamentally

Manuscript received March 12, 1993; revised June 3, 1993. The review of this paper was arranged by Associate Editor Y. Nishi.

P. U. Kenkare, J. D. Hayden, J. R. Pfiester, J. KO, H. C. Kirsch, S. A. Ajuria, P. Crabtree, and T. Vuong are with Advanced Products Research & Development Laboratory, Motorola Inc., Austin, TX 78721.

C. Mazur6 was with Advanced Products Research & Development Labo- ratory, Motorola Inc., Austin, TX 78721. He is now with IBM/Siemens Joint Development Project, Hopewell Junction, NY 12533.

IEEE Log Number 9213693.

limit the scalability of a given isolation for narrow nitride features. In particular, bird’s beak punchthrough occurs when the bird’s beak length approaches 50% of the nitride width. The thicker oxide undemeath the nitride mask must then be etched back, resulting in a reduced field oxide thickness which degrades isolation of the small active spaces. As a solution, a post-FOX field implantation has been proposed in order to locally increase the well doping and compensate for the thinner field oxide in the small isolation regions [9]-[ 111. However, achieving acceptable MOSFET performance requires that a very critical and alignment-sensitive photomask be used to keep the implant out of neighboring active regions [lo].

In this paper, the impact of bird’s beak punchthrough on isolation scalability for PELOX, PBL, and LOCOS is addressed. Although PELOX has been previously presented as an evolutionary isolation for sub-0.8 pm technology [5], 161, this process is extended to 0.35 pm BiCMOS technology [ 11 to reduce bird’s beak punchthrough down to 0.5 pm nitride lines. The resulting minimization of field oxide etchbacks combined with the recessed field oxide profile allows good electrical isolation without the use of a post-FOX field implant. Furthermore, even the conventional pre-FOX field implant is eliminated by integrating PELOX with the split well-drive- in scheme [12], [13] where the drive-in is split before and after field oxidation. The post-FOX drive-in step adjusts the field doping concentration by allowing updiffusion of boron from the well to the p-well surface. The second part of this paper will present physical and electrical data demonstrating the scalability of PELOX to achieve 1 pm active pitch without the use of any field implants.

11. EXPERIMENTAL DETAILS Physical characterization of the as-grow bird’s beak was

carried out for three different isolation stacks: LOCOS (1400 8, nitride/500 A oxide), Poly Buffer LOCOS (1400 8, nitride/500 A poly/l50 A oxide), and PELOX (1400 A nitride/500 8, oxide). The as-grown field oxide (FOX) thickness was about 7000 A. The PELOX process sequence [5], [6] involves a pad oxide undercut followed by 300 8, polysilicon deposition prior to field oxidation. This creates a poly-filled cavity offset from the nitride edge. The cavity lengths used in this work ranged from 0.120 pm per side to 0.165 pm per side. Bird’s beak punchthrough for various nitride widths was characterized using Scanning Electron Microscope (SEM) photographs taken following field oxidation. The bird’s beak height was measured by the vertical nitride displacement at the center of the nitride line. These physical data allowed us to design a PELOX

0018-9383/94$04.00 0 1994 IEEE

KENKARE et al.: SCALING OF POLY-ENCAPSULATED LOCOS 57

Fig. 1. Cross-section SEM view-following 7000 8, field oxidation of a PBL stack using 1400 8, nitride/500 8, poly/l50 8, oxide. The nitride width is 0.52 Fm.

Fig. 2. Cross-section SEM view following 7000 8, field oxidation of a PELOX stack using 1400 A nitride400 8, oxide with 300 A poly encap- sulation. The nitride width is 0.48 Fm.

process for fabricating 1 pm active pitch. In contrast to previously published work [5], [6], we scaled the PELOX cavity length to avoid bird’s beak punchthrough for the 0.5 pm nitride lines. The field oxide etchback was also reoptimized.

Electrical characterization was conducted on devices fabri- cated using a self-aligned twin-well CMOS process with 105 A gate oxide and N+ polysilicon gates. Unless otherwise noted, all of the device and SEM cross-section data in this paper were obtained using the same isolation module. The PELOX stack was 1400 A nitride/500 A oxide with an as-grown field oxide thickness of about 7000 A. A 300 A polysilicon deposition was used to fill the cavity. Other parameters such as PELOX cavity length, field oxide etchback, and sacrificial gate oxidation were kept constant. The final nwell and pwell doping concentrations of 1017cm-3 were set by performing a split well-drive-in sequence at 1150°C [12], [13]. No separate field implant steps were used. Our electrical results are based on 850°C backend processing and shallow S/D junctions of 0.15 pm and 0.25 pm for N+ and P+, respectively.

111. RESULTS AND DISCUSSION

A . Characterization of Birds Beak Punchthrough

Figs. 1 and 2 show the as-grown field oxide profile for PBL and PELOX, respectively. The pattemed nitride widths were measured to be 0.52 pm for PBL and 0.48 pm for PELOX. Bird’s beak punchthrough is clearly seen to have occurred for the PBL case. The bird’s beaks have met under the nitride mask resulting in almost complete oxidation of the pad poly and very thick oxide on the narrow active region. In contrast, the small as-grown bird’s beak for PELOX drastically reduces bird’s beak punchthrough.

The PBL profile in Fig. 1 clearly indicates that as-grown bird’s beak punchthrough becomes a fundamental scaling limitation as the bird’s beak length approaches 50% of the pattemed nitride width. Retrieval of the active feature is then difficult because extended field oxide etchbacks excessively thin down the field oxide and degrade isolation for the small

PBL A LOCOS , 0.0

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nitride width for three different isolation schemes.

active spaces. Scalability of the active pitch is thus severely limited.

The relationship of as-grown bird’s beak height versus nitride width for each of the isolations is shown in Fig. 3. It is seen that all of the schemes experience bird’s beak punchthrough below a certain minimum nitride width which is a function of the isolation stack composition. However, bird’s beak punchthrough for PELOX occurs only at sub-0.5 pm nitride widths. Unlike LOCOS and PBL, a linear addition of the two merging bird’s beaks cannot totally explain the PELOX data. Instead, we will show that the cavity-to-cavity spacing is an important parameter for scaling PELOX.

B . Effect of PELOX Cavity Length Narrow width effects on n-channel threshold voltage (VT)

are shown in Fig. 4 for the PELOX case. Note that VT is plotted as a function of nitride width, which could be construed as the mask active dimension for a bias-free nitride patteming process. Data for three different cavity lengths are shown. In addition, the LOCOS case is also included for comparison. Due to the split-well drive-in, the VT increase for narrower widths is mainly determined by the increasing gate dielectric

58 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 41, NO. 1 , JANUARY 1994

4 . 0 1 7 1

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WIDTH OF PATTERNED ” U D E LINE Olm)

Fig. 4. Threshold voltage versus pattemed nitride width for n-channel transistors with 5 pm length. Data for four different cavity lengths are shown.

thickness caused by merging of the bird’s beaks. The narrow width transistor behavior (shown in Fig. 4) is therefore a sensitive indicator of the bird’s beak punchthrough for various cavity lengths in PELOX.

The strong narrow width effects for LOCOS are easily explained because of the large encroachment. In contrast, the PELOX cavity clearly reduces narrow width effects by sup- pressing the as-grown bird’s beak. The lack of field implants in our study results in a slight reduction in n-channel VT as the nitride width is decreased from 1.1 to -0.7pm [12], [13]. The VT increase for narrower nitride widths is caused by bird’s beak punchthrough. However, the data indicate that there is a subtle relationship between the cavity length and V, increase for sub-0.6 pm nitride lines. Bird’s beak punchthrough effects for the narrow nitride lines become stronger as the cavity length is increased from 0.120 pm per side to 0.165 pm per side. Insight into these data can be inferred from Fig. 2, which shows that almost all of the as-grown encroachment for PELOX is confined to oxidation of the poly-filled cavity region offset from the nitride edge. Hence, the cavity-to-cavity spacing becomes an important factor in understanding bird’s beak punchthrough. This spacing is smaller for larger cavity lengths, and we eventually approach a regime where the nitride becomes too narrow to separate the two oxidizing cavities. Furthermore, the narrow nitride stress is no longer sufficient to suppress the upward force exerted by the oxidizing cavities. These data therefore indicate that the cavity length is an important scaling parameter for PELOX, and potentially for other cavity-based isolations such as sealed PBL [4].

C. Potential Scalability of PELOX to Sub-0.35 pm Technology

The PELOX data presented in Figs. 2 and 3 are based on a 1400 8, nitride/500 8, oxide stack with 300 8, poly encapsulation and 7000 8, field oxidation, which is designed for a minimum 0.5 pm nitride width. More aggressive profiles can be obtained by using a thinner pad oxide combined with thicker nitride. There do not seem to be any fundamental issues associated with forming the poly-filled cavity with thin pad oxide. As an example, Fig. 5 presents a SEM picture for a

Fig. 5. Cross-section SEM view following 5000 A field oxidation and an HF deglaze. The PELOX stack was 1400 A nitride/l50 A oxide with 150 A a-Si encapsulation. The nitride width is 0.44 pm.

O L - 1 2 - 1 1 -10 - 9 - 8 - 7 - 6

LOG OF DIODE LEAKAGE @ 5V

Fig. 6. Reverse-bias leakage (5 V) for field-edge intensive N+ diodes measured at room temperature. Normalized average leakage is under 10 pA/cm-edge. Database consists of 2129 die from 71 wafers. Each site had 6.28 cm of field edge.

0.44 pm nitride line following field oxidation. The sample preparation included the use of a silicon stain and the picture confirms the lack of substrate defects. The relatively aggressive profile was achieved using a 1400 8, nitride/l50 8, oxide stack with 150 A amorphous silicon (a-Si) encapsulation and 5000 A field oxidation. The cavity length was also scaled by about 25%. There is a manufacturing advantage to using a-Si as the thin encapsulating layer because of its improved uniformity and deposition. In addition, the thinner field oxide is consistent with current scaling trends of LOCOS-based schemes for sub- 0.35 pm technology. For example, recently proposed field isolation schemes for a 0.25 pm technology use 3500 8, of as-grown field oxide [14], [15].

D. Gate Oxide and Diode Data

The aggressive physical characteristics for PELOX were obtained without compromising gate oxide or diode integrity relative to LOCOS. As an example, Fig. 6 shows a histogram

KENKARE et al.: SCALING OF POLY-ENCAPSULATED LOCOS

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BREAKDOWN VOLTAGE (V) 1 5

Fig. 7. Gate oxide breakdown data for 512 K SRAM defect arrays fabricated using 105 8, thermal oxide and PELOX isolation. Database consisted of 148 capacitors.

Fig. 8. Cross-section view of 1 p m active pitch obtained using the PELOX process described in the text. SEM picture was taken following gate oxidation and gate poly deposition.

of N+ diode leakage measured at room temperature with a reverse bias of 5 V for field-edge intensive structures. The normalized average leakage is under 10 pA/cm-edge. Good diode integrity was also obtained for P+ diodes, which had a leakage of 20 pA/cm-edge at 5 V reverse bias. Typical gate oxide data for 512 Kb SRAM defect arrays is presented in Fig. 7 for 105 8, thermal oxides. Note that these results are based on the use of a more aggressive PELOX stack (1750 8, nitride/250 8, oxide) as compared to the 1400 8, nitride/500 8, oxide stack and indicate considerable latitude in PELOX scalability without creating substrate defects. Little difference in defectivity was found between nwell and pwell capacitors.

E. Physical and Electrical Evidence of I pm Acti1,e Pitch

Fig. 8 shows SEM results obtained for the case of a 1 pm active pitch. The field oxide is recessed with a final thickness of 2000 8, in the 0.6 pm isolation regions. Furthermore, the 0.4 pm wide active does not exhibit the surface curvature typical of strongly etched-back isolation schemes. In addition to al-

0 1 2 PATERNED " U D E WIDTH Um)

Peak n-channel transconductance versus patterned nitride width. The Fig. 9. x-intercept provides the total isolation-induced encroachment.

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GATE BIAS (V) Fig. IO. Ir , vs 1 i; curve for NMOSFET with I I L s / L of 0.3 pm/5 pm and

5 pm/5 pm, 1 1 , ~ is 0.2 p m smaller than the nitride width.

lowing good electrical characteristics, these factors contribute to planarity in the tight pitch regions.

Fig. 9 is a plot of NMOS peak transconductance versus the pattemed nitride width, which can be construed as the mask active dimension for a bias-free nitride patteming process. The x-intercept of 0.2 pm represents the total encroachment with respect to the pattemed nitride width. It is seen that the final encroachment of 0.1 pm per side is width-independent down to isolated nitride widths of 0.50 pm. The absence of field implants allows the electrical channel width we^) to match the physical MOSFET width, as measured from SEM cross-sections.

Fig. 10 presents subthreshold characteristics for two differ- ent NMOSFET widths. There is no change in the subthreshold slope as we^ is reduced from 5 to 0.3 pm. As seen in Fig. 11, this constancy of the subthreshold slope is also true for PMOS devices. However, unlike the NMOS case, the 0.3 pm wide device has a threshold voltage (VT) approximately 80 mV higher than the 5 pm wide device. This behavior originates

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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 41, NO. 1 , JANUARY 1994

2 0 -

h

v 15-

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THRESHOLD VOLTAGE (V)

Fig. 11. I D vs V , curve for PMOSFET with U',B/L of 0.3 pm/5 p m and 5 p d 5 pm. weff is 0.2 pm smaller than the nitride width. Fig. 13. 1% distribution for NMOSFET's with designed I.t;s/L of 0.35

p m/5 pm and 5 pm/5 pm. Database consists of 355 die from 71 wafers (same as Fig. 11)

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Fig. 12. U i e ~ histogram for NMOSFET's with designed I.t;fi/L of 0.35 p d 5 pm. Database consists of 355 die from 71 wafers.

from the field oxidation induced pileup of Phosphorous at the nwell silicon surface in the isolation regions. The increased Phosphorous surface concentration at the bird's beak edge becomes increasingly relevant for narrower widths thereby causing the higher VT.

NMOS electrical channel width and threshold voltage dis- tributions are shown in Figs. 12 and 13 and are based on 355 die from 71 wafers fabricated from three different lots. The we^ histogram in Fig. 12 indicates a well-controlled process. The threshold voltage distributions are extremely tight with a slightly smaller VT for the 0.35 pm wide device. This weak inverse narrow width effect is the result of the split well- drive-in scheme and Boron segregation effects during field oxidation [12], [13]. In this case, the lack of field implants allows for Boron diffusion from the channel to the isolation regions during the post-oxidation well drive-in.

DRAIN BIAS (V)

Fig. 14. Drain leakage versus drain bias for an n-channel metal-gated field transistor with 0.6 p m beak-to-beak dimension and 179 pm width. Data for two back biases are shown.

Fig. 14 illustrates the punchthrough characteristics of a n-channel metal-gated field transistor with a 0.6 pm beak- to-beak dimension. The leakage current is measured at the drain terminal for backbias values of 0 and -1 V. It is seen that for the 0 V backbias case, the off-leakage is under 0.1 pA/pm at V& = 5 V. Increasing the backbias to -1 V results in a six-fold reduction in the leakage and a 2.5 V increase in the punchthrough voltage. The n-channel poly- gated field transistor indicated a threshold voltage in excess of 7 V. As seen in Fig. 15, low isolation leakage (< 0.1 pA/pm at VDS = -5 V) was also found for the 0.6 pm beak-to-beak p-channel metal-gated field transistor. Clearly, the stringent isolation requirements for 0.35 pm technology are satisfied by coupling scaled PELOX with the split well-drive-in scheme.

KENKARE er ai.: SCALING OF POLY-ENCAPSULATED LOCOS 61

-1 -1 -1

n S. -1

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z -1

a 3 -1

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I ” 0 - 2 - 4 - 6 - 8 -10 DRAIN BIAS (V)

Fig. 15. Drain leakage versus drain bias for a p-channel metal-gated field transistor with 0.6 p m beak-to-beak dimension and 179 p m width. No back bias was used.

IV. CONCLUSIONS The as-grown bird’s beak punchthrough has been shown to

fundamentally limit the scalability of certain LOCOS-based isolations. In contrast to PBL, PELOX does not suffer as much from bud’s beak punchthrough and can be extended down to 0.5 pm nitride widths. Physical evidence has been presented which suggests the potential scalability of PELOX to even smaller nitride widths. The impact of the polysilicon- sealed cavity length on bird’s beak punchthrough has also been studied using narrow width transistor characteristics. These data highlight the importance of cavity length as an important parameter for scaling cavity-based isolations such as PELOX.

The scaling of PELOX to fabricate 1 pm active pitch has been achieved without the creation of substrate defects. In addition, the integration of scaled PELOX with the split well-drive-in scheme satisfies device requirements for a 0.35 pm BiCMOS technology while maintaining a simple front- end architecture. The off-leakage requirements are met at VDS = 5 V, which provides adequate margin for a 3.3 V technology. The NMOSFET characteristics remain largely width-independent down to 0.30 pm width dimensions, thus maximizing the performance of minimal geometry devices as required for high performance and high-density parts.

ACKNOWLEDGMENT The authors acknowledge the contributions of the APRDL

pilot line, process engineering, and testing organizations. Ex- cellent SEM support was provided by L. Ejiofor and L. Nguyen. C. Gunderson is thanked for his assistance with measurement tools and software. The managerial support of R. Sivan and L. Parrillo is appreciated.

REFERENCES

[I] J. D. Hayden et al . , “A high-performance quadruple well, quadruple poly BiCMOS process for Fast 16 Mb SRAMs,” IEDM Tech. Dig.. p. 819, 1992.

R. Rung et al., “Deep trench isolated CMOS devices,” IEDM Tech. Dig., p. 237, 1982. J. Matsunaga, N. Matsukawa, H. Nozawa, and S. Kohyama, “Selective polysilicon technology for defect free isolation,” IEDM Tech. Dig., p. 565, 1980. J. M. Sung, C. Y. Lu, L. B. Fritzinger, T. T. Sheng, and K. H. Lee, “Reverse L-shape sealed poly-buffer LOCOS technology,” IEEE Electron Device Letr., vol. 11, p. 549, Nov. 1990. S. S. Roth, W. Ray, C. Mazure, and H. C. Kirsch, “Polysilicon encapsulated local oxidation,” IEEE Elecrron Device Left., vol. 12, p. 92, 1991. S. S. Roth, W. J. Ray, C. Mazuri, K. Cooper, H. C. Kirsch, C. D. Gunderson, and J. KO, “Characterization of polysilicon-encapsulated local oxidation,” IEEE Transaction Electron Devices, vol. 39, p. 1085, May 1992. E. Kooi, “The invention of LOCOS,” IEEE Case Histories of Achieve- ment Sci. Technol., vol. 1, 1991. J. Hui, P. Vande Voorde, and J. Moll, “Scaling limitations of submicron local oxidation technology,” IEDM Tech. Dig., p. 392, 1985. H.-M. Muhloff, J. Dietl, P. Kupper, and R. Lemme, “Field isolation and active devices for 16 Mbit DRAMS,” in Proc. ESSDERC, 1990, p. 531. K. Sunouchi et al. , “Process integration for 64M DRAM using an asymmetrical stacked trench capacitor (AST) cell,” IEDM Tech. Dig., p. 647, 1990. K. Yuzuhira et al., “A large cell-ratio and low node leak 16M-bit SRAM cell using ring-gate transistors,” IEDM Tech. Dig., p. 485, 1991. C. Mazuri, A. Lill, and Ch. Zeller, “Width-independent narrow nMOS- FET reliability by split-well drive-in,” IEEE Electron Device Letr., vol. 11, p. 224, May 1990. Ch. Zeller, C. Mazuri, and M. Kerber, “Field-implant-free isolation by double-well split drive-in,” IEEE Elecrron Device Lett., vol. 11, p. 215, May 1990. P. H. Woerlee et al., “A low power 0.25 p m CMOS technology,” IEDM Tech. Dig., p. 31, 1992. N. Shimuzu et al., “A poly-buffer recessed LOCOS process for 256 Mbit DRAM cells,” IEDM Tech. Dig., p. 279, 1992.

Prashant U. Kenkare received the Bachelor’s

zation of gate dielectrics, analysis.

degree in electrical engineering from General Motors Institute in 1984, and the Ph.D. de- gree in electrical engineering from Princeton University in 1990. He wrote his doctoral dissertation in radiation-induced charge transport and interface state generation in thermal ox- ides.

He joined the Motorola Advanced Products Research and Development Laboratory in 1990. Since then, his activities have included characteri- advanced isolation development, and SRAM bitcell

Carlos Mazure, photograph and biography not available at time of publica- tion.

J. D. Hayden, for a photograph and biography, see p.68.

James Pfiester, for a photograph and biography, see the July 1992 issue of IEEE Transactions on Elecrron Devices.

J. KO, photograph and biography unavailable at time of publication.

62 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 41, NO. 1, JANUARY 1994

H. C. Kirsch received the B.S. degree in engineer- ing science from Case Institute of Technology in 1966, and the Ph.D. degree in applied physics from Stanford University in 1972.

From 1972 to 1979 he was with AT&T Bell Lab- oratories, and was involved the the design of custom PMOS and CMOS logic chips, NMOS DRAM’S and Digital Signal Processors. From 1979 to 1989, he was with AT&T Bell Laboratories in Allentown, PA, as a design supervisor for AT&T’s 1M CMOS DRAM, and subsequently as supervisor of submi-

cron CMOS technology development. He joined Motorola in 1989 as a Manager of Advanced Technology Development for the Advanced Products Research and Development Laboratory. Currently, he is a Senior Technologist at Motorola’s MOS 11 lab in Austin, TX.

P. Crabtree, photograph and biography unavailable at time of publication.

T. Vuong, photograph and biography unavailable at time of publication.

S. A. Ajuria was bom in Califomia in August 15, 1964. He received the B.S. degree in matenals science and engineering from the Massachusetts Institute of Technology in 1986, and the S.M. and Ph.D. degrees in electronic materials, also from MIT, in 1989 and 1992, respectively.

Since 1992, he has been with Motorola, Inc., in Austin, TX, where his research interests encompass the kinetics, processing, and charactenzation of ther- mal oxides for VLSI applications

Dr. Ajuna is a member of Tau Beta Pi, Sigma Xi, and the Matenals Research Society.