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Hindawi Publishing CorporationAdvances in Power ElectronicsVolume 2010, Article ID 253508, 9 pagesdoi:10.1155/2010/253508

Research Article

One Clock-Cycle Response 0.5 μm CMOS Dual-Mode ΣΔDC-DCBypass Boost Converter Stable over Wide RESRLC Variations

Neeraj A. Keskar1 and Gabriel A. Rincon-Mora2

1 DC-DC Controllers, Texas Instruments, Manchester, NH 03054, USA2 Georgia Tech Analog, Power, and Energy IC Research Laboratory, School of ECE, Georgia Institute of Technology,Atlanta, GA 30332, USA

Correspondence should be addressed to Neeraj A. Keskar, [email protected]

Received 29 April 2009; Accepted 21 January 2010

Academic Editor: Vassilios G. Agelidis

Copyright © 2010 N. A. Keskar and G. A. Rincon-Mora. This is an open access article distributed under the Creative CommonsAttribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work isproperly cited.

Power supplies in portable applications must not only conform and adapt to their highly integrated on-chip and in-packageenvironments but also, more intrinsically, respond quickly to fast load dumps to achieve and maintain high accuracy. Thefrequency-compensation network, however, limits speed and regulation performance because it must cater to all combinationsof filter capacitor CO, inductor L, and CO’s equivalent series resistance RESR resulting from tolerance and modal design targets. Assuch, it must compensate the worst-case condition and therefore restrain the performance of all other possible scenarios, even ifthe likelihood of occurrence of the latter is considerably high and the former substantially low. Sigma-delta (ΣΔ) control, whichaddresses this issue in buck converters by easing its compensation requirements and offering one-cycle transient response, has notbeen able to simultaneously achieve high bandwidth, high accuracy, and wide RESRLC compliance in boost converters. This paperpresents a dual-mode ΣΔ boost bypass converter, which by using a high-bandwidth bypass path only during transient load-dumpevents was experimentally 1.41 to 6 times faster than the state of the art in current-mode ΣΔ boost supplies, and this without anycompromise in RESRLC compliance range (0–50 mΩ, 1–30 μH, and 1–350 μF).

1. Introduction

In portable applications like cellular phones, PDAs, andthe like, integrated BiCMOS and CMOS switching dc-dcsupply circuits reduce cost, size, component count, anddesign complexity (from a user’s perspective). One of thecritical bottlenecks in obtaining a fully integrated solution,however, is the frequency-compensation circuit, which isdesigned around off-chip power LC filter devices to obtainoptimal performance [1]. The fact is mode-rich state-of-the-art applications, manufacturing tolerances, and parameterdrifts expose dc-dc converter integrated circuits (ICs) towide variations in output capacitance CO, power inductanceL, and CO’s equivalent series resistance RESR, inducingconsiderable changes in loop-gain and transient response,compromising feedback stability or transient response. Asa result, to guarantee stability and high bandwidth with afixed on-chip frequency-compensation circuit, the design

necessarily constrains RESRLC values within a narrow targetrange [1]. This is especially detrimental in compact high-performance multiple input-output converters [2, 3], wherethe on-chip or in-package LC filter is variable by design todynamically accommodate the diverse loading conditions ofthe system.

Unclocked or asynchronous sigma-delta (ΣΔ) buck con-verters [4–8] are self-compensating and free of the speed-stability tradeoffs of most dc-dc converters because thecontrol loop in these converters resembles current-modecontrol by indirectly sensing the inductor current ripple viathe ripple voltage it drops across CO’s RESR. In other words,the ESR voltage mostly sets the terminal ripple voltage of CO,impressing the inductor ripple current information on theoutput voltage and achieving current-mode-like control. Theresulting single-pole-like response yields higher bandwidthand more explicit control over the output ripple voltage[7].

2 Advances in Power Electronics

Extending this technique and its benefits to boostconverters, which are popular in portable electronics forboosting battery voltages to 3.3–5 V, is not straightforwardbecause the inductor current does not fully flow to CO.Consequently, in realizing ΣΔ control in boost converters,the feedback circuit must explicitly sense and mix inductorcurrent with the sensed output voltage [9]. Such techniques,however, resurrect the limiting speed-stability tradeoffs ΣΔcontrol averted in buck converters in the first place, forcingthe designer to adjust current and voltage gains therebyreducing the loop bandwidth in order to accommodatelarge RESR LC filter values.

This paper presents a dual-mode boost ΣΔ bypasscontroller IC that overcomes the aforementioned speed-stability compromise by introducing a high-speed bypassmode (and circuit) that engages only during transient load-dump events, achieving both high bandwidth and wideRESRLC compliance. To this end, Section 2 first reviewsand discusses the stability requirements of ΣΔ convertersand their resulting transient response to fast load dumps.Section 3 then describes the proposed dual-mode techniqueand the design of its IC-prototype embodiment, followed byexperimental results in Section 4; Section 5 draws relevantconclusions.

2. ΣΔ Converters

2.1. ΣΔ Control in Buck Converters. A ΣΔ buck converter,as shown in Figure 1, controls the frequency and duty cycleof PMOS switch SM by comparing rippling output voltagevO via sensed voltage vS against dc reference VREF withcomparator CPV . Operationally, ac inductor ripple currentil flows into CO and its RERS (which is relatively largein these converters at 100–250 mΩ to ensure its voltage—vesr— overwhelms ac capacitor voltage vc) [7] as capacitordisplacement current ic, forcing ac output ripple voltage vo tomimic il (vo≈ vesr =ilRESR). As a result, in regulating vo, theconverter also regulates il, which in the process simplifies thefrequency response of the converter to that of a single-polesystem, as in current-mode control, guaranteeing stability,irrespective of RESRLC values.

In a positive load-step transient event, when load currentiO suddenly rises, comparator CPV detects the voltage droopthe now larger iO induces on vO and consequently switchesSM on indefinitely (i.e., at 100% duty cycle) until vO returnswithin CPV ’s predefined hysteretic window limits, that is,within an acceptably low margin of VREF. During SM ’s ontime, the inductor voltage being nearly constant at VIN−VO,inductor current iL slews in a single switching cycle untilit fully supplies iO and recharges CO back to VREF [8]. Inother words, only the inductor and capacitor slew-rate limitsand second-order delays across the comparator and switchset the response time (effective bandwidth) of the system.Note a negative load dump undergoes a similar but reversedresponse.

2.2. ΣΔ Control in Boost Converters. Unlike buck converters,ac inductor ripple current il in boost converters does not

flow completely to output capacitor CO because reverse-biased diode D (shown in Figure 2) temporarily disconnectsL from vO (and CO) when switch SM conducts all of iL toground. The resulting ac ripple voltage in vO does not fullyreflect the behavior of il, as it does in buck converters withnonnegligible RESRvalues, which means that ΣΔ control inboost converters cannot rely on vO alone [9]. The negativefeedback loop in a boosting supply must therefore sense,scale, and mix iL with vO explicitly (e.g., mix iLRIgmi andvOgmv into RS as scaled sum vSUM) to achieve current-mode-like control characteristics. A hysteretic comparator thenmodulates SM ’s frequency and duty cycle based on how thescaled sum (vSUM) of the ripples compares against a user-defined hysteresis window. Note the voltage feedback loopmodulates the effective inductor reference current vI.REF/RI ,which is also the average inductor current IL (or low-passfiltered —LPF— version of iL) to whatever is necessary tofully supply iO.

Within the context of averaged small-signal analysis, therelatively high-gain, low-bandwidth voltage control loop (VLoop) of the system effectively embeds a higher bandwidth,lower gain current loop (I Loop), as shown Figure 3 [10].At low frequencies, below low-pass filter pole pLPF, iLRI

nearly equals vI.REF and the gain of the current loop ispractically zero, but increasing with frequency until reachingits highest possible gain at frequencies past pLPF. The currentloop’s gain again drops at high frequencies, past the complexLC double poles, when the ac voltage across L decreases.Given that iL is, for all practical purposes, regulated tohigher frequencies and therefore is a current source to theouter voltage loop at moderate-to-high frequencies, CO andeffective load resistance RO set the dominant low-frequencypole of the system while L and RO invoke right-half planezero zRHP [11].

For stable conditions to prevail, the unity-gain frequencyof the voltage loop (i.e., the system — fV.0 dB—) must fallbelow zRHP and iL must remain a current source (i.e., currentloop must stay closed with considerable loop gain) for thefrequency range of interest to the voltage loop [10]. Assuch, fV.0 dB must stay below both zRHP and current-loopbandwidth fI.0 dB:

f0 dBV ≈gmvD

′M

2πRIgmiCO<< f0 dBI ≈

RIgmiRSMVO

2πL, (1)

f0 dBV ≈gmvD

′M

2πRIgmiCO< zRHP = D′MVO

2πLIL, (2)

or

LILVOCO

= LIOCOVOD

′M<RIgmigmv

, (3)

where DM is the duty-cycle of SM , D′M is (1−DM), and M isthe modulator gain. Note that zRHP and fI.0 dB shift to lowerfrequencies with increasing inductance values, which meansthat fV.0 dB must also decrease accordingly, in an ideal case.LPF pole pLPF, whose location indicates the lowest frequencyat which the current loop is closed, must also be below

Advances in Power Electronics 3

VIN SM

D

iL

L

RESR

COvc

ic

iO

Load

LC filter vGM

vO

R1

R2

CPv+

−

vS

VREF

Figure 1: Circuit schematic of a switching ΣΔ buck converter.

iLRI

RI

gmv

vI .REF

vSUMgmi

iL′

++−

+− −CO

KI = gmiRSKV = gmvRS

iOiD

LPF

RESR

Load

I-Loop

V-Loop

VGM

vO

ic

RS

VIN

SM

D

L

iL

vPH

VREF

Figure 2: Circuit schematic of a switching ΣΔ boost converter.

the worst-case value of fV.0 dB to ensure there is enough gainfor iL to remain a current source:

pLPF<fV.0 dB|min = D′M2VO

2πLIL. (4)

Ultimately, the system responds to a load dump at the speedof the voltage loop, whose bandwidth is fV.0 dB, allowingswitch SM to cycle multiple times before restoring vO backto its target window. LPF pole pLPF limits the extent to whichiL naturally responds to a load dump by allowing moderate-to-high frequency ac error-correcting signals through thecurrent loop. In other words, the current loop limits (whileattempting to regulate) the rising and falling rates of averageiL below iL’s maximum possible slew-rates of VIN /L and(vO – VIN )/L. Because fV.0 dB and pLPF both decrease withincreasing L, with the former also decreasing with decreasingCO, the worst-case LC combination, from the perspective ofstability, occurs at the highest L and lowest CO, the conditionfor which gains RIgmiRS and gmvRS and pole pLPF are adjustedand transient-response performance over the entire LC filterrange is sacrificed.

3. Proposed Dual-Mode ΣΔ Controller IC

The proposed ΣΔ boost controller IC in Figure 4 overcomesthe transient-response degradation associated with theworst-case LC combination by bypassing the main voltageloop (and its fV.0 dB) with a fast (and lower low-frequencyloop gain) feed-forward path only during transient events.The stability requirements of the main loop set the acceptableRESRLC range for the system while the high-bandwidth

gmv+−VREF

+−vSUM M

dm

RS

i1

RI

GI D′M

−IL

ZOvO

++

id

gmiI Loop

V Loop

Figure 3: Small-signal equivalent control diagram of switching ΣΔboost converter at moderate-to-high frequencies.

bypass path allows the system to respond in one cycle at themaximum possible inductor current slew rate, the responseof which is similar to ΣΔ buck converters. The transientimprovement is achieved on chip (i.e., without an off-chipfrequency compensation circuit) and without sacrificing LCcompliance.

3.1. Steady-State and Bypass Operation. The basic objectiveof the bypass mode is to override nominal equivalent averageinductor current reference IL(nom) (vI.REF/RI) to a highervalue almost instantly only during load dumps and allow thebypass voltage loop to control and limit how much of theextra current in L flows to vO. Initially, during steady-stateconditions, the bypass circuit is inactive and load currentiO and SM ’s average off duty cycle D′M (i.e., one minus SM ’saverage on duty cycle DM) set the nominal average inductorcurrent IL(nom) required to support a given iO, which ishigher than iO because SM steers a portion of iL away fromvO to ground according to DM :

IL(nom) = IODM′

= IO1−DM

. (5)

In the bypass mode, however, independent loops regulate iLto a value higher than IL(nom) and sensed output voltage vSto VREF, as depicted in the equivalent circuit of Figure 5.

The current loop, which modulates switching frequencyfSW and SM ’s duty cycle dM , has higher bandwidth andappears as a current source for frequencies of interest to thelower bandwidth bypass voltage loop controlling auxiliaryswitch SA. In the bypass mode, inductor current iL isregulated at a value IPK or VPK /RI that is greater thanIL(nom) (i.e., IL required to support IO). This means, unlessotherwise limited, average diode current ID is now higherthan IO, as a result of which CO recharges quickly. OncevO is back within the hysteretic window limit of bypasscomparator CPB and about to surpass its upper boundary,CPB and SA divert excess current away from D through SAuntil iO again discharges vO to CPB’s lower window limit.The switching cycle repeats as average inductor current ILgradually drops back to IL(nom), at which point the bypassloop stops switching and SA remains open. Note as long asIL exceeds IL(nom), the bypass voltage loop, by independentlyregulating vO with higher loop gain than the current loop,ensures that the voltage inputs of summing comparator CPSare virtually short-circuited (i.e., vS ≈ VREF), as shown inFigure 6, allowing CPS to regulate iL exclusively.


+KIKV−+−

VREF

VREF+

−

VREF−+

CPs

CPT

CPB

Bypass voltageloop

Bypass current loop

Mode transition

VI.REF

LPFRI

iL

VIN

LSA

vGA

vGM SM

CO

iDRESR R1

R2

ic

iO vO

Load

vS

Figure 4: Simplified schematic of the proposed dual-mode ΣΔboost converter.

−

R1

R2

CPB

Bypass voltageloop

Bypasscurrent

loopVREF−

+

IREG = DM′IL ≈ DM

′ vI.REF

RIID = IO = DM

′IL(nom)

VPKRI

≈ IPK � IL � IL(nom)

RESR

CO

SA

ic

DiO vO

vS

iD

vGAiREG

VIN

Load

Figure 5: Equivalent circuit of the proposed ΣΔ converter in thebypass mode.

With respect to stability, as already mentioned, the unity-gain frequency of the current loop ( fI.0 dB) must exceed thatof the bypass voltage loop ( fB.0 dB) so the inductor appearsas a current source in the voltage loop, eliminating thecomplex conjugate pair associated with LC in the voltageloop [12]. Because the unity-gain bandwidth of a ΣΔ loopis its switching frequency, SM ’s switching frequency ( fI.0 dB)must exceed that of SA ( fB.0 dB). Therefore, since fI.0 dB

depends on the rising and falling rates of iLRI as it traversesCPS’s hysteretic current window HI ,

fI.0 dB =(

HI

RI

)−1( L

VIN+

L

VO −VIN

)−1

= VIN (VO −VIN )RIVOHIL

(6)

RI

iLRI

From CPT

VPK = IPKRI

RF CF

vI.REF

CPS

KI

KV

−+−+

iL∑

Δ current loop

Powerstage

Virtual short due tobypass voltage loop

+−

Figure 6: Simplified conceptual circuit schematic of the dual-modeΣΔ converter in bypass mode, as the bypass loop virtually shorts vSand VREF and the current loop regulates iL to vI.REF/RI .

and fB.0 dB on how fast excess iD (i.e., D′MIL – ID) and IOcharge and discharge output capacitor CO between CPB’shysteretic voltage window HV ,

fB.0 dB =(

HV (R1 + R2)R2

)−1(

COIO

+CO

(

D′MIL − IO)

)−1

,

(7)

to force fI.0 dB to be greater than fB.0 dB, CO must exceed

CO ≥(

HI

HV

)

(

IOL

VORID′M

)

(

R2

R1 + R2

)

≡ CO(min), (8)

where the R1-R2 divider represents the effect of the resistivefeedback factor on HV and CO(min) the minimum stableoutput capacitance.

3.2. Transient Response and Mode Transition. During apositive load-dump event, when IO suddenly rises and vOdroops in response, as shown in Figure 7, the dual-modeconverter enters its bypass mode, raising iL to peak value IPK(or VPK /RI) in a single switching cycle of SM . SubsequentlyvO (or vS) is pulled back to VREF (R1+R2)/R2 (or VREF) ina single switching cycle of SA. Transient-detect comparatorCPT in Figure 4 perceives the load dump and engages thebypass mode by sensing when vS drops below VREF by apreset threshold value of ΔVBP (e.g., 2.5% of VREF) (afterthe delay the comparator requires to switch: td). Then,CPT clamps vI.REF to peak voltage VPK , the value of whichsets the maximum current the circuit can drive. Switch SMtherefore remains closed (tt.M(on)) until iL reaches VPK /RI

(IPK ), the new value of vI.REF/RI . After SM resumes switchingand regulating iL about IPK , SA remains open and allowsall diode current iD to flow to vO until CO recharges to(VREF+HV /2)·(R1+R2)/R2. Beyond this point, CPB and SAregulate vS about VREF by switching SA, in other words, bysteering excess inductor current away from CO.

Ultimately, output voltage vO droops in response to loaddump ΔiO until iL reaches IPK . First, excess current ΔiOdischarges CO during delay td while vS reachesVREF − ΔVBP .Then, while SM raises iL from iL(avg) (orVREF/RI or IL(nom)1) to


vGA

iO

iL

vO ΔVBP

ΔvO

vI.REF/RI

VIN /L IL(nom)1

IL(nom)2

ΔiOIO2

IO1

IPK

HvR1 + R2

R2

td

tt.M(on) Time

Figure 7: Transient-response performance when presented withfast load-steps (positive and negative).

VI.OS

RI.OS

II.OS

RF vI.REF

CF

CPS

ΣΔ current loop

Powerstage

+ −iL

iLRI

RI

Virtual short due tobypass voltage loop

KI

KV

−+

−+

Figure 8: Equivalent converter circuit in bypass mode with addedoffset voltage VI.OS to ensure that vI.REF/RI is slightly below iL(avg).

IPK (or VPK /RI), iD is zero and full load current IO dischargesCO, yielding a total variation (ΔvO) of

ΔvO = ΔVBP +(

IOCO

)

tt.M(on)

= ΔVBP +(

IOCO

)

[(

IPK − IL(nom)1)

L

VIN

]

= ΔVBP +(

IOCO

)

(VPK − vI.REF)LRIVIN

.

(9)

Note that the ratio of L and CO sets the dominant part ofΔvO.

Once sensed output voltage vS is within the hystereticvoltage window of CPB, to transition back to steady state,iL(avg) must somehow fall back to whatever value (IL(nom)) isnecessary to sustain IO, reducing to zero the amount of excesscurrent iL that bypass comparator CPB steers away fromvO through SA. To that end, introducing a series negativeoffset voltage VI.OS, as shown in Figure 8, ensures that iL isalways above its target (i.e., iL(avg) is greater than vI .REF/RI),forcing the loop to gradually decrease both iL(avg) and theexcess current. Finally, when iL is low enough to be able tofully supply iO, and the excess current (D′MIL–IO) is zero, thebypass loop stops switching (i.e., disengages), which meansthat the main voltage loop now regulates vO via SM (Figure 4)to its target. In other words, henceforth, iL(avg) equals IL(nom).

vI.REF

+VI.OS/2

−VI.OS/2

Current-loop Voltage-loop

VR

EF

(5V/V)

ADV

ADI

(8V/V)iL

L RS

SM

SDiO vO

SA

RESR

CO

RI(50 mΩ)

ADS CPM

CPT

CPB

(140 mV)

(140 mV)

VV.OS (50 mV)

gmiRS = 2.8V/VgmvRS = 5.3V/V

gmi

gmv

Load

VIN

R1

(76 K)

R2

(24 K)

vS

+−

−+

+

+

−−

+

−

+

−

+

−

+

−

+ −

+−+− −

+

+−

+

−+−

Figure 9: 0.5μm CMOS circuit embodiment of the proposed dual-mode ΣΔ bypass boost converter.

Power switch (SA)Power switch (SA)

Drivers + deadtime

Comparators + digital

Bias

Decoupling caps

Amplifiers

VIN

VO

IO

RESR LC space

ηpeak

IQ

ΔvO (5.6μH,

53μF, 0.1–1 A)

Process

Die size

2.7–4.2 V

5 V± 5%

0–1 A

0–50 mΩ1–30μH1–350μF

93%

1.5 mA

0.23 V

0.5μmCMOS

(1.9× 2.6)

mm2

Figure 10: Die photograph and performance summary.

Note that the transition is continuous, allowing SA to stopswitching without incurring irregularities in SM .

During a negative load dump, when iO suddenly drops, asalso shown in Figure 7, iL(avg) automatically exceeds its newsteady-state target and vO rises above its target. As a result,bypass comparator CPB engages and diverts current awayfrom vO until vS again drops to VREF–HV /2 (in one cycle ofSA). The circuit gradually transitions back to steady state inthe same manner as described earlier, through VI.OS.

4. Experimental Results and Discussion

4.1. IC Design. The proposed dual-mode ΣΔ bypass con-verter was designed, fabricated, and evaluated using a 0.5 μm,5 V CMOS process. The circuit embodiment of the converter,as shown in Figure 9, employs a differential-signal processingscheme to attenuate the effects of substrate noise on thehigh-bandwidth ΣΔ loops [10]. For simplicity, series resistor


4030

20

10100

101

102

Capacitance (μF)

Capacitor ESR (mΩ)

10

5

10

15

20

25

30

Indu

ctan

ce(μ

H)

iL (0.5 A/div)

vO (20 mV/div)

VIN = 2.7 V,

IO = 1 A

L = 5.6μH,

C = 53μF

Proposed ΣΔ

State-of-the-art ΣΔ

Figure 11: Nominal steady-state snapshot of inductor current iLand output voltage vO ripples (inset) for the proposed solution andexperimental RESRLC stability space for both the proposed dual- andstate-of-the-art single-mode boost ΣΔ converters.

RI senses iL with the understanding more power efficienttechniques are possible and recommended [13]. Current-sense amplifier ADI , which monitors the voltage across RI ,includes an internal RC filter that generates differentialcurrent reference vI.REF. Differential preamplifier ADV buffersand amplifies sensed output voltage vS by 5V/V to decreasethe effects of offsets and hysteretic window limits in posterioramplifiers and comparators on vS and vO (i.e., improveaccuracy); ADV drives differential summing amplifier ADS,bypass hysteretic comparator CPB, and transient-detecthysteretic comparator CPB.

For ease of design and reliability, main, bypass, andtransient-detect comparators CPM , CPB, and CPT adoptthe same circuit architecture, which is designed to yield ahysteretic window of 140 mV. The bypass threshold voltage(ΔVBP) is composed of half the comparator hystereticwindow plus an additional offset of 50 mV (VV.OS) thatis added between CPB and CPT . Differential current-senseamplifier ADI includes a 40 mV offset voltage (VI.OS) at itsoutput to ensure iL is below its target by VI.OS/RI during thebypass mode, to gradually transition back to steady state aftera load dump. The designed offsets are sufficiently large todwarf the transistor mismatch-induced offsets in ADI , CPB,and CPT and ensure that the polarities of VV.OS and VI.OS

remain unchanged across process and temperature corners.In the absence of deep-N or buried layer isolation

structures, the bulk of a single PMOS transistor servingthe function of auxiliary switch SA could not be connectedto the highest potential (vO) because of latch-up concerns.Whenever the switching node flies above vO following theturn-off of SM , SA’s body diode can conduct engagingthe parasitic vertical PNP transistor present, channelingconsiderable current to the substrate. A second PMOS deviceis therefore added in series to use its reverse-biased bodydiode to block the foregoing current. And during normal

operating conditions, when vO is higher than VIN , as thebody diode of the first blocks the current of the second.

The proposed ΣΔ controller 0.5μm IC was designed tosupply power from a 2.7–4.2 V Li-Ion battery and drive a 0-1 A load at 5V± 5% with as wide an RESRLC range as possible(0–50 mΩ, 1–30μH, and 1–350μL was achieved). The totalsilicon surface area the IC occupied was 1.9 × 2.6 mm(Figure 10). The peak efficiency of the converter was 93% at0.4A with a biasing quiescent current of 1.5 mA. The totaloutput voltage variation of the converter in response to a0.1–1A load dump (ΔiO) with 5 mΩ, 5.6 μH, and 53 μF ofRESRLC was 200 mV, which constitutes a 4x improvementover its nonbypassed counterpart under similar conditions(800 mV).

4.2. LC Compliance. The measured RESRLC space for whichthe converter was stable is 0–50 mΩ, 1–30μH, and 1–350μF, as illustrated in Figure 11. This range was determinedby subjecting the converter to 0.1–1A load dumps with100 nanoseconds rise and fall times. The stability limitwas observed as a loss of regulation for the proposed ΣΔconverter in the bypass mode, as the bypass loop was nolonger able to control the loop, and subharmonic oscillationsfor the nonbypassed (state-of-the-art) ΣΔ boost converter[14].

The stability limits for both converters, with and withoutthe bypass path, are reached when their respective current-loop bandwidths ( fI.0 dB) approach their voltage-loop coun-terparts ( fB.0 dB and fV.0 dB), as that is when L ceases to bea current source for the voltage loop, be the main loop,or the bypass loop. As a result, because fV.0 dB and fB.0 dB

increase with decreasing CO and increasing IO and fI.0 dB andRHP zero zRHP decrease with increasing L and decreasingVIN , the highest L-IO(30 μH–1A) and lowest CO-VIN (12 μF-2.7 V) combination constitutes worst-case conditions. SinceRESR essentially introduces a left-half plane zero in thevoltage loop, increasing RESR also increases fV.0 dB and fB.0 dB,which means that the above-mentioned limits along with thehighest RESR value (50 mΩ) describe the worst-case stabilitypoint of the converter. In other words, CO(min) increases withincreasing L, IO, and RESR and decreasing VIN .

The maximum capacitance was limited to 350 μF as apractical limit for the intended portable application space(the circuit is stable at higher CO values). Similarly, themaximum RESR value was limited to 50 mΩ to keep theoutput voltage ripple acceptably low under a 1 A load.Under these conditions and constraints, the stability spacesfor the proposed and the state-of-the-art converters areapproximately equal in “volume.”

4.3. Transient Load-Dump Performance. As shown inFigure 12(a), the transient-response variation of vO (ΔvO) inresponse to 0.1–1A load dumps (ΔiO) with 100 nanosecondsrise and fall times under 2.7 V, 5.6 μH, 53μF, and 5 mΩof VIN , L, CO, and RESR was 200 mV for the proposeddual-mode scheme and 800 mV for its single-mode state-of-the-art counterpart. While the proposed converterresponds by increasing iL above its target (to IPK or VPK/RI)


0

1

2

3

4

−1−0.8−0.6−0.4

−0.20

0.20.4

Vol

tage

(V)

Cu

rren

t(A

)

0 0.2 0.4 0.6 0.8 1

Time (ms)

Proposed

State-of-the-art

Proposed

State-of-the-art vO

iL

VIN = 2.7 , L = 5.6μH, C = 53μF

(a)

−1

−0.50

0.51

1.52

2.5

−0.2

0

0.2

0.4

0.6

Vol

tage

(V)

Cu

rren

t(A

)

0 0.5 1 1.5 2

Time (ms)

Proposed

State-of-the-art

Proposed

State-of-the-artvO

iL

VIN = 2.7 , L = 5.6μH, C = 53μF

(b)

Figure 12: Measured transient performance of the proposed dual-mode and state-of-the-art single-mode ΣΔ boost converters in responseto (a) 0.1–1 A and (b) 1–0.1 A load steps.

00.5

1

1.5

22.5

33.5

−0.8

−0.6

−0.4

−0.2

0

0.2

Vol

tageΔv O

(V)

Cu

rren

ti L

(A)

0 0.05 0.1 0.15

Time (ms)

Increasing L

Increasing L

vO

iL

30μH15μH

5.6μH

30μH

15μH

5.6μH

Figure 13: Measured effects of L on the transient performance ofthe proposed dual-mode ΣΔ bypass boost in response to 0.1–1 Aload dumps, CO = 53μF.

in one switching cycle of SM , the state-of-the-art circuitincreases iL gradually, pulling vO back to regulation inseveral cycles of SM , which is why the proposed solutionexhibits a fourfold improvement over its predecessor.In a negative load-step (Figure 12(b)), while the excessinductor current is immediately bypassed by switch SA in theproposed converter keeping the output voltage overshootlow (<75 mV), the excess inductor energy causes a largevoltage overshoot (600 mV) in the state-of-the-art converter.

Decreasing (increasing) L increases (decreases) the rateat which iL responds to a load dump, as shown inFigure 13, thereby decreasing (increasing) the time vOslews (reducing ΔvO). Similarly, increasing (decreasing)CO decreases (increases) vO’s droop rate in response to

00.5

1

1.5

22.5

33.5

−1

−0.8

−0.6

−0.4

−0.2

0

0.2

Vol

tageΔv O

(V)

Cu

rren

ti L

(A)

0 0.05 0.1 0.15

Time (ms)

Increasing CO

Increasing CO

vO

iL26μF

11μF

53μF

26μF

11μF

53μF

Figure 14: Measured effects of CO on the transient performance ofthe proposed dual-mode ΣΔ bypass boost converter in response to0.1–1 A load dumps.

a load dump (Figure 14). Note that increasing (decreas-ing) CO also increases (decreases) the delay time betweenthe load step and the onset of bypass threshold voltageΔVBP (td) (Figure 7), which is why the onset of iL rising shiftswith CO.

Although transient-response performance for the pro-posed dual-mode scheme improves with decreasing L, thesame is not true for the single-mode converter whose iLresponse time is limited by the bandwidth of the loop,not L’s slew rate. As a result, as illustrated in Figure 15,the percentage improvement that the dual-mode enjoysover its single-mode counterpart increases with decreasingL: 6- and 1.43-fold improvement at 1μH–36μF and 30μH–36μF, respectively.


0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

Tran

sien

tvo

ltag

eΔv O

(V)

1 10 100

Capacitance CO (μF)

VIN = 2.7 V, VO = 5 V

1μH, state-of-the-art1μH, proposed10μH, state-of-the-art

10μH, proposed15μH, state-of-the-art15μH, proposed

ΔvO = 5%

ΔVBP = 120 mV

Figure 15: Measured transient output voltage variation ΔvO undervarious LC combinations in response to 0.1–1 A load dumps (ΔiO)for the proposed dual-mode and state-of-the-art single-mode ΣΔconverters.

0

1

2

3

4

5

60

1

2

3

−0.4

−0.3

−0.2

−0.1

0

0.1

0.2

Cu

rren

t(A

)V

olta

ge(V

)

Vol

tage

(V)

0 1 32 4

Time (ms)

Load current iO

ΔvO (300 mV)

Switch SA’sgate voltage vGA

Bypassmode

Outputvoltage vO

140 mV Mainmode

Inductor current iL

IPK

1.1 A

VIN = 2.7 , L = 15μH, CO = 53μF

Figure 16: Measured steady state to bypass and back transitions inresponse to positive 0.1–0.6 A load dumps (positive ΔiO).

Increasing CO decreases vO’s transient droop in bothconverter cases, except that bypass threshold voltage ΔVBP

effectively limits the extent to which a larger CO decreasesΔvO in the proposed scheme. In the limit, increasing CO tosuch an extent that ΔvO is less than ΔVBP would preventthe bypass mode from ever engaging. As a result, theperformance improvement in ΔvO is lower between the

0

1

2

3

4

5

60

0.5

1

1.5

2−0.4

−0.2

0

0.2

0.4

Cu

rren

t(A

)V

olta

ge(V

)

Vol

tage

(V)

0 1 32 4

Time (ms)

Load current iO

Switch SA’sgate

voltage vGA

Bypassmode

Output voltage vO

140 mVMainmode

Inductor current iL

IL(nom)1.3 A

VIN = 2.7 , L = 15μH, CO = 53μF

Figure 17: Measured steady state to bypass and back transitions inresponse to negative 0.6–0.1 A load dumps (negative ΔiO).

75

77

79

81

83

87

85

89

91

93

95

Effi

cien

cy(%

)

0 0.2 0.4 0.6 0.8 1

Load current (A)

L = 15μH

VIN = 2.7 VVIN = 3.3 VVIN = 4.2 V

Figure 18: Measured steady-state efficiency Vs. Load current IO forthe proposed converter.

proposed and state-of-the-art solutions at higher CO values:ΔvO for the proposed and state of the art asymptoticallyconverge as CO increases.

4.4. Mode Transition. Figures 16 and 17 illustrate how theproposed dual-mode ΣΔ bypass boost converter transitionsfrom steady state to bypass mode and back in response topositive and negative 0.1–0.6A load dumps with an LC com-bination of 15μH and 53 μF. As designed, the bypass mode


ripple is larger at ±70 mV (±(HV /2)·(R1 + R2)/(R2ADV ) ≈±140 mV/2) or ±1.4% than the steady-state counterpart,which is at ±15 mV or ±0.3%. During a positive load dump(Figure 16), when iO suddenly rises, a load-induced dropin vO exceeding the ΔVBP limit engages the bypass modeand increases iL to 2.5 A (IPK ) in one switching cycle ofSM . As determined by offset VI.OS , the circuit then takesapproximately 2.5 ms to gradually decrease iL back to its newtarget of roughly 1.3A, at which point SA stops switchingand the converter is back in steady state. During a negativeload dump (Figure 17), iL is automatically above its targetand SA consequently starts diverting some of iL back to VIN

almost immediately, until 2.5 ms later, when iL drops to itsnew target.

The main drawbacks of the auxiliary bypass path arethe silicon real estate, power, and switching noise associatedwith power switch SA. The latter two shortcomings, however,are more often than not inconsequential because they onlyoccur during transient events, which are typically sporadic,short, and seldom occur without significantly affecting thesteady-state power efficiency (Figure 18). The prominentdisadvantage of the proposed solution is therefore additionalsilicon real estate for SA because it carries substantial current.The transient-performance benefits of SA and the bypasspath that drives it, however, offset this cost.

5. Conclusion

A dual-mode ΣΔ bypass boost dc-dc controller 0.5 μmCMOS IC that is stable for an RESRLC filter range of 0–50 mΩ, 1–30 μH, and 1–350 μF and responds to positiveand negative load dumps in one switching cycle has beenproposed, designed, fabricated, and evaluated. The drivingfeature of the foregoing solution is a robust on-chip (i.e.,smooth transitioning) ΣΔ bypass path that responds onlyduring transient load dumps. While the converter increasesinductor current iL in one switching cycle in response to asudden rise in load current iO and uses it to quickly slewoutput capacitor CO back to its target, it also limits howmuch of iL flows to CO in the case of a negative load dump,when iO drops, limiting the total transient variation of outputvoltage vO and therefore improving accuracy performance.The transient-response benefits of the proposed scheme, ascompared to state-of-the-art single-mode ΣΔ converters, arethe highest at low values of L (e.g., 6x at 1μH and 1.41x or40% improvement at 30μH) because L limits how fast iL risesand falls to its targets. The main drawback of the proposedtechnique is the additional silicon real estate required forauxiliary power switch SA, which is partially (and oftencompletely) offset by its improved accuracy performance.In summary, the proposed dual-mode ΣΔ bypass boostconverter is fast, widely LC compliant (robust), and easilyimplementable.

Acknowledgment

This work was supported by Texas Instruments.

References

[1] B. Schaffer, “Internal compensation—boon or bane?” inUnitrode Design Seminar SEM 1400, Texas Instruments, Dallas,Tex, USA, 2001.

[2] M. Chen, J. P. Vogt, and G. A. Rincon-Mora, “Design method-ology of a hybrid micro-scale fuel cell-thin-film Lithium Ionsource,” in Proceedings of the 50th Midwest Symposium onCircuits and Systems (MWSCAS ’07), pp. 674–677, Montreal,Canada, August 2007.

[3] H.-P. Le, C.-S. Chae, K.-C. Lee, et al., “A single-inductorswitching DC-DC converter with 5 outputs and orderedpower-distributive control,” in Proceedings of the 54th IEEEInternational Solid-State Circuits Conference (ISSCC ’07), pp.534–620, San Francisco, Calif, USA, February 2007.

[4] H. Sira-Ramırez, “Sliding mode-Δ modulation control of a“buck” converter,” in Proceedings of the 42nd IEEE Conferenceon Decision and Control, vol. 3, pp. 2999–3004, Maui, Hawaii,USA, December 2003.

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[8] S.-C. Tan, Y. M. Lai, M. K. H. Cheung, and C. K. Tse, “Onthe practical design of a sliding mode voltage controlled buckconverter,” IEEE Transactions on Power Electronics, vol. 20, no.2, pp. 425–437, 2005.

[9] R. Venkataramanan, A. Sabanovic, and S. Cuk, “slidingmode control of DC-to-DC converters,” in Proceedings ofthe International Conference on Industrial Electronics, Controland Instrumentation (IECON ’85), vol. 1, pp. 251–258, SanFrancisco, Calif, USA, 1985.

[10] N. A. Keskar and G. A. Rincon-Mora, “A compact 1–30 μh, 1–350 μf, 5–50 mΩ ESR compliant, 1.5% accurate 0.6 μm CMOSdifferential ΣΔ boost DC-DC converter,” Analog IntegratedCircuits and Signal Processing, vol. 54, no. 3, pp. 157–169, 2008.

[11] R. Erickson, Fundamentals of Power Electronics, Chapman &Hall, New York, NY, USA, 1st edition, 1997.

[12] N. Keskar and G. A. Rincon-Mora, “Self-stabilizing, inte-grated, hysteretic boost DC-DC converter,” in Proceedingsof the 30th Annual Conference of IEEE Industrial ElectronicsSociety (IECON ’04), vol. 1, pp. 586–591, Busan, Korea,November 2004.

[13] H. P. Forghani-Zadeh and G. A. Rincon-Mora, “Current-sensing techniques for DC-DC converters,” in Proceedings ofthe 45th Midwest Symposium on Circuits and Systems, vol. 2,pp. 577–580, Tulsa, Okla, USA, August 2002.

[14] J. Calvente, F. Guinjoan, L. Martinez, and A. Poveda, “Subhar-monics, bifurcations and chaos in a sliding-mode controlledboost switching regulator,” in Proceedings of IEEE InternationalSymposium on Circuits and Systems (ISCAS ’96), vol. 1, pp.573–576, 1996.

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