Reconfigurable Switched-Capacitor∆Σ ModulatorTopology DesignYing Wei, Pengbo Sun, Alex Doboli

Department of Electrical and Computer Engineering,Stony Brook University, Stony Brook, NY, 11794-2350

Abstract— In this paper, a methodology for designing recon-figurable discrete-time ∆Σ modulator topologies is proposed.Topologies are generated from a set of all possible topologiesexpressed by a generic topology, and optimized for minimizing thecomplexity of the topologies, maximizing the topology robustnesswith respect to circuit nonidealities, and minimizing total powerconsumption. The paper presents a case study for designingtopologies for a three-mode reconfigurable∆Σ modulator. Thepaper also offers a reconfigurable topology implementation on aProgrammable System-on-Chip (PSoC) device.

I. I NTRODUCTION

The rapid development in wireless technologies has ledto a demand for reconfigurable receiver-on-a-chip that sup-ports multiple standards. In the multi-standard receiver im-plementation, the major difficulty falls in the design of highperformance, compact multimode analog to digital converters(ADC), because of the different requirements (e.g. dynamicrange (DR) and bandwidth) between different modes [1].

There is few work on reconfigurable multimode ADCs [1],[2], [3]. So far, the design of reconfigurable multimode∆Σmodulators is manual and relatively unsystematic. There islittle understanding on how to develop optimal reconfigurabletopologies for a new set of modes. Also, to improve design clo-sure and reduce cost, topology design must contemplate a fairamount of circuit nonidealities. More efficient methodologiesare needed for systematically designing reconfigurable ADCswhile contemplating nonidealities early in the design flow.

Current design methodologies are for single-mode∆Σ only.Most of the work is on topology parameter optimization withlimited modification of the modulator topology. Medeiroetal. [4] propose a design flow based on extensive analysis andmodeling of the nonidealities that degrade the∆Σ modulatorperformance. However, their methodology is limited to thefour single-mode, discrete-time topologies supported by CADtools – SDOPT and FRIDGE. Franckenet al. [5] describe anapproach for high-level simulation and synthesis of discrete-time ∆Σ modulators. Behavioral models for integrators, quan-tizer, and feedback digital-to-analog converter (DAC), areintegrated in a synthesis tool (DAISY) that selects the mod-ulator topology with the lowest power consumption for agiven specification and constraints for the building blocks. Ananalytical integration method for the simulation of continuous-time ∆Σ modulators is suggested in [7]. However, the set ofallowed topologies is not complete, thus optimal solutionsmight be missed. Tang and Doboli [6] present a synthesisalgorithm that finds the optimal topology for a given spec-ification by solving a mixed-integer nonlinear programming(MINLP) problem [10] with a cost function expressing thesignal path complexity, sensitivity, and power consumption

of the topology. This method considers only single-mode∆Σmodulators built out of ideal blocks.

This paper proposes a systematic methodology for designingreconfigurable discrete-time∆Σ modulator topologies, opti-mized for minimum topology complexity, maximum robust-ness to circuit nonidealities, and minimum power consump-tion. The methodology is based on the concept of generictopology that expresses all possible signal paths in a reconfig-urable topology. We present the modeling of generic topolo-gies including following nonidealities: integrator leakage andgain error, circuit noise, and nonlinearity. Models are usedin the methodology to set up a set of nonlinear equationsets. Equations are solved for finding efficient reconfigurabletopologies. Found topologies are then refined usingSimulinksimulation of models with more detailed nonidealities. Thedesign methodology is presented in Section II. The paperpresents a case study for designing topologies for a threemode reconfigurable∆Σ modulator, and the implementation ofa second-order reconfigurable topology on PSoC, as discussedin Section III.

II. OVERVIEW OF THE METHODOLOGY FOR

RECONFIGURABLE∆Σ MODULATOR TOPOLOGY DESIGN

In this section, we will use a dual-mode third-order re-configurable∆Σ modulator as example to show the designmethodology, which can be generalized to reconfigurable∆Σmodulator of any order.

The input to the topology design methodology is the speci-fications for the dual-mode reconfigurable∆Σ modulator. Foreach target specifications, such as DR, a set of solutionsthat can achieve the target DR are found by using analyticalexpressions, such as the expressions embedded in the∆Σtoolbox [9]. Each solution has four parameters: (i) the orderof the loop filter, (ii) the oversampling ratio (OSR), (iii) theinternal quantizer bits, and (iv) the noise transfer function(NTF) type, Butterworth or Inverse Chebyshev. Any solutionfor a single mode can be combined with the solution foranother mode to build a dual-mode ADC. Hence, the set ofpossible candidates for the dual-mode reconfigurable ADCare generated. Each candidate can be implemented usingdifferent topologies, and optimal topologies are generated bythe proposed methodology.

Optimal reconfigurable∆Σ modulator topologies are de-signed for a set of specifications starting from agenericmodulator topology. The generic topology contains all pos-sible signal paths in a reconfigurable modulator. The generictopology for a third order modulator is shown in Fig. 1.

The state-space description of the topology is expressed asfollows:

Σ Σ ΣY3

ΣI2 I3

Y2

2S

1S

I1V

U

−−−−−

DAC

t1,1

Y1

t2,1

t3,1

t1,2

t1,3

−t3,3t2,2

t3,2

t2,3

t2,4

t1,4

t3,4

b2 b3 b4b1

a3a2a1 a4

−− − −

Fig. 1. Third order reconfigurable∆Σ modulator topology

Y1Y2Y3

=

−t1,1−t2,1−t3,1t1,2 −t2,2−t3,2t1,3 t2,3 −t3,3

Y1Y2Y3

+

b1−a1b2−a2b3−a3

[UV

] ·

I1I2

I3

+

Nth1Nth2Nth3

V = [ t1,4 t2,4 t3,4 ]

[Y1Y2Y3

]+[ b4 −a4 ]

[UV

]+Eq (1)

Where,I1, I2, and I3 are nonideal integrator transfer func-tions, which are of two possible types: delayed or delayless.Eq denotes the quantization noise.Nth1, Nth2, andNth3 denotesthe circuit noise in each integrating stage.

By solving the state-space equations, the transfer function ofthe modulator is written as equationV = L0U +L1V +Eq [8].VariablesL0 andL1 are loop filters, which can be analyticallyderived from the state-space equations.

MINLP formulation. For a cost functionf (expressing thedesired design goals), the problem of designing an optimizedreconfigurable topology is formulated as

minimize costf = f (xm,i ,wxm,i);subject to:g(xm,i) = 0;

subject to:xm,i ≥ 0, wxm,i ∈ {0,1};Variablexm,i denotes any of the unknown coefficientsai , bi ,

and ti, j for the mth mode. Unknownwxm,i represents whetherthe signal path with coefficientxm,i is present in the optimaltopology or not.g are the24 equality constrains obtained fromequating symbolic expressions forL0 and L1 to the desiredloop filter functions for all the modes [6].

The cost function for optimal reconfigurable modulatortopology design is

f = α1 ∑m

∑i

wxm,i +α2 ∑m1

∑m2 6=m1

∑i, j

|wxm1,i −wxm2, j |+∑m

βm(∑k

γm,k ·hm,k(xm,i))+γ∑m

∑i

pm,i

(2)

The first two terms in the cost function represent the com-plexity of the modulator topology. The first term is the absolutecomplexity, considering the total number of signal paths inthe topology. The second term is the relative complexitythat accounts for the changes of the signal paths when themodulator is reconfigured.

The third cost function term minimizes the sensitivity of themodulator with respect to circuit nonidealities. The term is theweighted sum of the impact of nonidealities on the modulatorNTF. hm,k, a function of xm,i , minimizes the impact of thekth nonideality on NTF for themth mode, which captures thefollowing nonidealities.

Integrator leakage and gain error: for switched-capacitorintegrator, the integrator leakage and gain error are modeledby including the finite gain (Ai) of the OpAmp and capacitormismatch factor (εi) in the integrator transfer functionIi ,respectively, as shown below.

Ii = gi(1− εi)(1,z)

z− (1−gi/Ai), i = 1,2,3 (3)

Where, gi is the integrator gain,(1,z) denotes two typesof integrators: delayed or delayless. Notice that the NTFonly depends on the loop filterL1. Therefore, minimizing thevariation of the NTF is equivalent to minimizingL1. If theintegrator transfer function is replaced by equation (3), thenL1 becomes to equation (4).

L1 =L1,num+∑3

i=1µi

(∑2

j=0cµi , jzj)

+∑3i=1 εi

(∑2

j=0cεi , jzj)

L1,den+∑3i=1µi

(∑2

j=0dµi , jzj)

+∑3i=1 εi

(∑2

j=0dεi , jzj) (4)

Variable L1,den and L1,num denotes the denominator andnumerator of the ideal loop filter functionL1, respectively.cµi , j , dµi , j , cεi , j , dεi , j are the symbolic coefficients as functionsof signal path coefficients. To minimize the difference betweenL1 andL1, the following functionhm,k was added to the overallcost function (2) used in topology design:

hm,k =3

∑i=1

2

∑j=0

(∣∣cµi , j∣∣+

∣∣dµi , j∣∣+

∣∣cεi , j∣∣+

∣∣cεi , j∣∣) (5)

Circuit noise and nonlinearity: Considering the noise ofall integrating stages, the transfer function of the modulatorwas expressed as equation (6). And, equation (7) captures thecircuit noise in the cost function.

V = L0U +L1V +3

∑i=1

(∑3

j=0cthi , jzj

L1,den×Nth,i

)+Eq (6)

hm,k =N

∑i=1

N

∑j=0|cthi , j | (7)

In the frequency domain, nonlinearity can be modeled bycalculating the frequency responses at different harmonic. Forexample, let assume that only the second order nonlinearcomponent (k2) of the first stage is considered. Then, thefrequency response of the modulator can be expressed as

L1,o2 =L1,o2,num+k2

(∑3

j=0chd, jzj0

)

L1,o2,den+k2

(∑3

j=0dhd, jzj0

) (8)

The corresponding term in the cost function (2) is

hm,k =3

∑j=0

(|chd, j |+ |dhd, j |)

(9)

The forth cost function term minimizes the power con-sumption. It takes into account the static and dynamic powerconsumption of the switched-capacitor loop filter, which hasthe same form as that in [6].

By formulating the reconfigurable modulator topology syn-thesis problem as a MINLP problem, and including the above-mentioned four nonidealities into the cost function, a set oftopologies is generated.

III. C ASE STUDIES

A. Triple-mode reconfigurable∆Σ modulator topology design

We used the proposed design methodology to generateoptimized reconfigurable∆Σ modulator topologies that satisfymultiple specifications, and have reduced system complexity.The modulator operates in three modes that correspond toUMTS, CDMA2000, and GSM communication standards.The DR requirement for UMTS, CDMA2000, and GSM are11.5-bit, 13-bit, and 15-bit with the bandwidth of1.92MHz,615kHz, and190kHz, respectively [1].

Topology Np Np,r Nc,r Np,a ηd ηpnon-reconfigurable 33 – – 33 – –

opt1 < 4,4,4 > 25 18 7 30 24.2% 9.1%opt2 < 4,3,3 > 20 15 5 25 39.4% 24.2%

TABLE I

DESIGN COMPLEXITY

m1−0.0633

m2−0.4571

m3−1.0000

m1−0.2219

m2−0.9724

m3−1.0000

m1−0.3325

m2−0.1333

m3−0.0394

m1−

0.91

61

m2−

1.00

00

m3−

0.24

82

m3−

0.55

58

m2−

1.00

00

m2−0.5590

m1−0.9971

m3−1.0000

m1−0.9189

m2,m3

m1−0.2219

m2−0.9724

m3−1.0000 m1−0.6084

V

m1−0.1265

m3−0.0010

m2−0.0022

U

DAC

Fig. 2. Reconfigurable modulator topologyopt2

One of the optimized topologies are shown in Fig. 2.Table I presents the comparison of the two optimized topolo-gies obtained using the proposed methodology, and a non-reconfigurable topology that includes three single-mode modu-lators. The comparison is in terms of the topology complexity,reduction in design effort (ηd) and power consumption (ηp).Topology opt1 has orders< 4,4,4 > for the three modes.Topologiesopt2 has orders< 4,3,3 > for the three modes.The complexity of the system is analyzed with respect to thenumber of signal paths (Np), the number of non-reconfigurablecells (Np,r ), and the number of reconfigurable cells (Nc,r ).

Table I shows that reconfigurable ADCs are much morecompact than the modulator built out of three single-modearchitectures. For example, there are33 signal paths in thenon-reconfigurable topology, while there are only25, 20signalpaths in the generated topologiesopt1, opt2, respectively. Lessnumber of signal paths not only decreases the complexityof the circuit implementation, but also decreases the overallpower consumption and chip area. Design effort is estimatedfrom the number of signal paths and the number of reconfig-urable cells.

In order to analyze the robustness of the produced modulatortopologies, we simulated the second mode of topologiesopt2. Fig. 3 presents the performance comparison for mode 2 oftopologyopt2 and the corresponding∆Σ toolbox topology inthe presence of circuit noise and integrator leakage. The gen-erated topology performs better. If circuit noise is considered(Fig. 3(a)), the improvements of peak SNR for mode 2 oftopology opt2 is 3dB and 10dB as compared to the toolboxtopology for noise levels of−70dB and−60dB, respectively.The higher the noise level, the more the improvement. Fig. 3(b)shows the SNR comparison for integrator leakage. For exam-ple, if the OpAmp of the first integrator has finite gain of50dB or 60dB, the degradation of SNR because of integratorleakage for mode 2 of topologyopt2 is 3dB less than thatof the toolbox topology, as shown by the dashed line and thedashed-dotted line with plus markers, respectively. Therefore,although in the ideal case the generated topologies behave thesame as the topologies from the∆Σ toolbox, the optimizedtopologies are more robust in the presence of circuit noise. Theperformance improvement shows that the third cost functionterm is crucial to the performance of the final reconfigurabletopologies, as it captures the possible performance tradeoffsfor the topologies with respect to circuit nonidealities.

−90 −80 −70 −60 −50 −40 −30 −20 −10 0−40

−20

0

20

40

60

80

100

Input amplitude [dB]

SN

R [d

B]

(a) order = 3, SNR = 64, CDMA2000−mode

ideal, opt2ideal, toolboxnoise=−60dB, opt2noise=−60dB, toolboxnoise=−70dB, opt2noise=−70dB, toolbox

−90 −80 −70 −60 −50 −40 −30 −20 −10 0−40

−20

0

20

40

60

80

100

Input amplitude [dB]

SN

R [d

B]

(b) order = 3, OSR = 64, CDMA2000−mode

ideal, opt2ideal, toolboxA

0=50dB, opt2

A0=50dB, toolbox

A0=60dB, opt2

A0=60dB, toolbox

Fig. 3. SNR degradation by circuit nonidealities for topologyopt2 (mode 2)

CT

SC

SC

CT

SC

SC

CT

SC

SC

CT

SC

SC

Ref.sAnalog

Analog

MuxingInput

DigitalClocksfrom Core

To DigitalSystem

Analog Drivers

Port 0Port 2

Column 1Column 0 Column 2 Column 3

Analog PSoC Block ArrayANALOG SYSTEM

PSoC CORE

System Bus

Global Analog Interconnect

Fig. 4. PSoC analog system [11]

B. Implementation of reconfigurable∆Σ modulator on PSoC

The PSoCTM family consists of many mixed-signal arrayswith on-chip controller devices. The top level analog architec-ture is shown in Fig. 4. Analog PSoC block array consists offour analog columns, each of which consists of three analogblocks: one continuous-time (CT) block and two switched-capacitor (SC) blocks. The analog SC blocks support∆Σ,successive approximation, and incremental ADC conversion,capacitor DACs, and SC filters. They have three input arrays(ACAP, BCAP, andCCAP) and one feedback array (FCAP)of binary-weighted switched-capacitors, allowing user pro-grammability of the capacitor weights. This provides summingcapability of two scaled inputs and a non-switched capacitorinput. ACAP, BCAP, andCCAP range from1C to 32C, andFCAPhas value of16C or 32C, whereC is the unit capacitanceof the capacitor array [11].

A second-order∆Σ modulator can be implemented by usingtwo SC blocks as the integrators. We designed a dual-modesecond-order topology. The target peak SNR for the two modesare 10 bits (60dB) and 8 bits (48dB), respectively. The twomodes have five and six signal paths with OSR of64 and40,respectively. NTF types for the two modes are Butterworthtype, and Inverse Chebyshev type, respectively. When the

Φ1 Φ2

Φ1*

Φ1

Φ2

Φ2

Φ1

Φ1 Φ2,GeneratorΦ2

Φ1

11−bitTimer

Data

DecimatorDataLatch

DAC

Φ1 Φ2

Φ1*

Φ1

Φ2

Ref+

Ref−

ResetFCAP

SC PSoC Block 2SC PSoC Block 1

Vin

Source Clock

InterruptCPU

DataBus

Analog Column ComparatorBus

(b)

(a)

U

V

m1−0.2164m2−0.2147

m1−0.2164m2−0.2147

m1,m2−1.0000 m1,m2−1.0000b1

t1,2 t2,3

Ref+

Ref−

ResetFCAP

ACAPACAP

BCAP

m2−0.0020

t2,1

m2−0.5590m1−0.5585a1 a2

Fig. 5. Dual-mode second-order modulator (a) topology (b) PSoC imple-mentation

−70 −60 −50 −40 −30 −20 −10 0−20

−10

0

10

20

30

40

50

60

70

80SNR comparison of two modes

Input frequency [dB]

SN

R [d

B]

mode 1, idealmode 2, idealmode 1, nonidealmode 2, nonideal

Fig. 6. SNR comparison of the dual-mode second-order modulator

modulator is switched from one mode to another mode, foursignal paths need to be reconfigured: signal path coefficientsa1,a2,b1 need to be modified, and one more signal patht2,1needs to be switched on for the second mode, as shown inFig. 5(a).

The implementation of the topology on PSoC is shownin Fig. 5(b). The coefficients (a1,a2,b1) of the signal pathcan be modified by changing the capacitor arrays (ACAPandFCAP). The additional signal patht2,1, when the modulator isreconfigured, is implemented by using one more input array(BCAP) for the first SC block. The values of the capacitorarrays are shown in Table II.

Fig. 6 shows the simulation results. It shows that the peakSNR of the two modes equals to71dB and60dB for the idealmodulator, respectively. If circuit nonidealities are considered,the peak SNR drops to60dB and 54dB, respectively, whichcan still meet the design specifications. Fig. 7 shows the outputspectrum from the measurement. The input is2.1V peak-to-peak sinusoid wave with frequency of45kHz. For mode 1, thenoise floor level is about−55dB, and the SNR is about60dB.

SC block 1 SC block 2Mode ACAP BCAP FCAP ACAP BCAP FCAP

1 4C – 16C 8C – 16C2 8C 1C 32C 16C – 32C

TABLE II

VALUES FOR THE CAPACITOR ARRAYS

Fig. 7. Measurement result

For mode 2, the noise floor level is about−47dB, and theSNR is about53dB. Also, the notch of the Inverse ChebyshevNTF for the second mode is clearly shown in Fig. 7(b).

IV. CONCLUSION

This paper presents a systematic methodology for design ofoptimized topologies for reconfigurable single-loop switched-capacitor ∆Σ modulators. The methodology optimizes thetopologies for minimum complexity, maximum robustnessto performance degradation due to circuit nonidealities, andminimum power consumption. A case study on designinga three-mode reconfigurable∆Σ modulator shows that thecomplexity and power saving of the generated reconfigurablemodulators is about40% and 24.2% of that of three single-mode modulators obtained with∆Σ toolbox. Most importantly,the produced reconfigurable topologies are more robust tointegrator leakage and gain error, circuit noise, and non-linearity than the topologies from∆Σ toolbox. The dual-mode reconfigurable topology is also implemented on a PSoCdevice. Measurement results show that the modulator can meetthe design specifications.

V. ACKNOWLEDGEMENTS

The authors thank Cypress Semiconductor Corp. for gen-erously providing the hardware used in this work. We alsoacknowledge the help and assistance of Mr. G. Saul, Mr. D.Van Ess and Dr. E. Currie on designing and implementing thereconfigurable modulator using the PSoC architecture.

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