Reconfigurable Computing

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Reconfigurable Computing. Ender YILMAZ, Hasan Tahsin OĞUZ. Overview. Energy savings are in average 35% to 70%, and speedup is in average 3 to 7 times. Reduction in size and component Time to market Flexibility and upgradability. Three ways of supporting processing requirements. - PowerPoint PPT Presentation

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  • Reconfigurable ComputingEnder YILMAZ, Hasan Tahsin OUZ

    Reconfigurable Computing

  • OverviewEnergy savings are in average 35% to 70%, and speedup is in average 3 to 7 times.Reduction in size and componentTime to marketFlexibility and upgradability

    Reconfigurable Computing

  • Three ways of supporting processing requirementsHigh performance microprocessorsEven expensive Ps are not fast enough for many applicationsPower consumption(100W or more)Not convenient for embedded applicationsApplication specific ICs (ASICs)Provides a natural mechanism for large amount of parellalismDoes not suffer from serial instruction fetchConsumes less power than reconfigurable devicesNot general purposeTime to marketInfeasable for many embedded systems, only high volume of production makes it feasible

    Reconfigurable Computing

  • Three ways of supporing processing requirements(continued)Reconfigurable ComputingIn the middle of P and ASICs as performance and power consumptionParellalism due to hardware implementationCheaper for low volume productionDesign time and time to market is much lessFunctional units can change over timeGeneral Purpose

    Reconfigurable Computing

  • System Level ArchitecturesFive classes of reconfigurable systemsa External stand-alone processing unitb Attached processing unitc Co-processord Reconfigurable functional unite Processor embedded in a reconfigurable fabric

    Reconfigurable Computing

  • System Level Architectures

    Reconfigurable Computing

  • Reconfigurable Fabricconsists of reconfigurable functional units, reconfigurable interconnect and a flexible interface to the rest of the systemThere is a tradeoff between flexibility and efficiency.

    Reconfigurable Computing

  • Functional UnitsFine Grained: implements functions for single or small number of bitsCoarse Grained: larger, ALU, DSP

    Reconfigurable Computing

  • Emerging DirectionsLow power techniquesActivity reduction in power-aware design toolsLeakage current reductionDual supply voltage methodsAsynchronous architecturesFine grained asynchronous pipelinesQuasi delay insensitive architecturesGlobally async. Locally sync.Molecular microelectronicsPromising for increasing capacity and performance of reconf. Comp. Arch.

    Reconfigurable Computing

  • Main Trends in ArchitecturesCoarse grained fabricsCost of interconnection is increasing due to advancements in tech., granularity of LUs are increasing to reduce routing overheadHeterogeneous functionsDue to migration to more advanced tech., number of transistors devoted to the reconf. logic increases. Multipliers , DSP units can be addedSoft coresInstructions are programmableAlthough being less area and speed efficient, flexible

    Reconfigurable Computing

  • Design MethodsGeneral purpose designsAnnotation and constraint driven approachSource-directed compilation approachSpecial purpose designDigital Signal ProcessingThe word-length optimisationOther Design MethodsRun time customisationSoft instruction processorMulti FPGA compilation Hardware compilers for high-level descriptions are key to reduce the productivity gap for advanced circuit developmentDesign methods can be generally categorized into two; general design methods and special design methods

    Reconfigurable Computing

  • General Purpose DesignDesign methods and tools are based on general purpose programming languages such as C, C++ and JavaHDLs: VHDL and Verilog are also availableA number of compilers from C to hardware have been developedTarget hardware or hardware/softwareTwo different approached

    Annotation and constraint driven approachAnnotations are used in source-code + constraint filesOnly minor changes are needed to produce a compilable program from software descriptionSource-directed compilation approachSource languages are adopted to enable explicit description of parellelism, communication and other customisable hardware resources

    Reconfigurable Computing

  • Summary of General Purpose Hardware Compilers

    Reconfigurable Computing

  • Special Purpose DesignThere are many specific problem domains which deserve special considerationExploiting domain specific properties:Describe the computation (MATLAB-Simulink)Optimise the implementation

    Digital Signal ProcessingThe word-length optimisation

    Reconfigurable Computing

  • Digital Signal ProcessingOne of the most successful applications for reconfigurable computing is real-time digital signal processing(DSP)Inclusion of hardware support for DSP in FPGADSP problems share similar propertiesAlgorithms are numerically insensitive but have very simple control structuresControlled numerical error is acceptableSNR exist for measuring numeric precisionDesign is performed in SimulinkDesigner need not deal with low level implementation issues

    Reconfigurable Computing

  • The word-length optimisationUnlike mP based implementations size of each variable is customisable.Numerical accuracy, design size, speed and power cons.Most important decision is selection of an appropriate word-length and scaling for each signalThe accuracy is less sensitive to some variables than to othersConsidering error and area information, it is possible to achieve a highly efficient DSP implementationWord-length optimisation problem is NP-hardHeuristics are used, area/signal quality tradeoffAnalytic methods are faster but pessimistic

    Reconfigurable Computing

  • Other Design MethodsRun-time customisationSoft instruction processorsMulti-FPGA compilation

    Reconfigurable Computing

  • Run-time customisationOne part of the system continues to be operational, while other part is being reconfiguredAt compile time, an initial configuration bitstream and incremental bitstreams have to be producedRuntime design optimisation techniquesRuntime constraint propagation, producing a smaller circuit with higher performance by boolean algebra optimisationLibrary compilation, precompiled modules are loaded into reconfigurable resources by procedure call mechanismsExploiting information about program branch probabilitiesPromote utilization by dedicating more resources the branches which execute more frequentlyHardware compiler produces a collection of designs, each optimised for a particular branch probability, best one is selected at runtime

    Reconfigurable Computing

  • Soft Instruction ProcessorTwo examples of soft instruction processors are MizroBlaze and NiosCustomisation of resources and instructions is supportedTime for instruction fetch and decode is reduced, each custom instruction replaces several regular instructionsAdditional resources can be assigned to a custom instruction to improve the performance

    Reconfigurable Computing

  • Multi-FPGA CompilationCompiler can generate designs using speculative and lazy execution to improve the performanceA single program is partitioned between host and reconfigurable resources

    Reconfigurable Computing

  • Dynamic Instruction Set Computer

    Reconfigurable Computing

  • DISC-Example Code

    Reconfigurable Computing

  • DISC-Example Application

    Reconfigurable Computing