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Reconfigurable Computing
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Transcript of Reconfigurable Computing
Reconfigurable Computing
Reconfigurable Computing
Ender YILMAZ, Hasan Tahsin OĞUZ
Reconfigurable Computing
Overview
+ Energy savings are in average 35% to 70%, and speedup is in average 3 to 7 times.
+ Reduction in size and component+ Time to market+ Flexibility and upgradability
Reconfigurable Computing
Three ways of supporting processing requirements
High performance microprocessors Even expensive μPs are not fast enough for many
applications Power consumption(100W or more) Not convenient for embedded applications
Application specific ICs (ASICs) Provides a natural mechanism for large amount of
parellalism Does not suffer from serial instruction fetch Consumes less power than reconfigurable devices Not general purpose Time to market Infeasable for many embedded systems, only high volume
of production makes it feasible
Reconfigurable Computing
Three ways of supporing processing requirements(continued)
Reconfigurable Computing In the middle of μP and ASICs as performance and
power consumption Parellalism due to hardware implementation Cheaper for low volume production Design time and time to market is much less Functional units can change over time General Purpose
Reconfigurable Computing
System Level Architectures
Five classes of reconfigurable systemsa External stand-alone processing unitb Attached processing unitc Co-processord Reconfigurable functional unite Processor embedded in a reconfigurable fabric
Reconfigurable Computing
System Level Architectures
Reconfigurable Computing
Reconfigurable Fabric
consists of reconfigurable functional units, reconfigurable interconnect and a flexible interface to the rest of the systemThere is a tradeoff between flexibility and efficiency.
Reconfigurable Computing
Functional Units
Fine Grained: implements functions for single or small number of bitsCoarse Grained: larger, ALU, DSP
Reconfigurable Computing
Emerging Directions
Low power techniques Activity reduction in power-aware design tools Leakage current reduction Dual supply voltage methods
Asynchronous architectures Fine grained asynchronous pipelines Quasi delay insensitive architectures Globally async. Locally sync.
Molecular microelectronics Promising for increasing capacity and performance of
reconf. Comp. Arch.
Reconfigurable Computing
Main Trends in Architectures
Coarse grained fabrics Cost of interconnection is increasing due to advancements
in tech., granularity of LU’s are increasing to reduce routing overhead
Heterogeneous functions Due to migration to more advanced tech., number of
transistors devoted to the reconf. logic increases. Multipliers , DSP units can be added
Soft cores Instructions are programmable Although being less area and speed efficient, flexible
Reconfigurable Computing
Design Methods
General purpose designs Annotation and constraint driven approach Source-directed compilation approach
Special purpose design Digital Signal Processing The word-length optimisation
Other Design Methods Run time customisation Soft instruction processor Multi FPGA compilation
• Hardware compilers for high-level descriptions are key to reduce the productivity gap for advanced circuit development
• Design methods can be generally categorized into two; general design methods and special design methods
Reconfigurable Computing
General Purpose Design Design methods and tools are based on general purpose
programming languages such as C, C++ and Java HDLs: VHDL and Verilog are also available A number of compilers from C to hardware have been developed Target hardware or hardware/software Two different approached
Annotation and constraint driven approach Annotations are used in source-code + constraint files Only minor changes are needed to produce a compilable
program from software description
Source-directed compilation approach Source languages are adopted to enable explicit
description of parellelism, communication and other customisable hardware resources
Reconfigurable Computing
Summary of General Purpose Hardware Compilers
Reconfigurable Computing
Special Purpose DesignThere are many specific problem domains which deserve special considerationExploiting domain specific properties:
Describe the computation (MATLAB-Simulink)
Optimise the implementation
Digital Signal ProcessingThe word-length optimisation
Reconfigurable Computing
Digital Signal Processing
One of the most successful applications for reconfigurable computing is real-time digital signal processing(DSP)Inclusion of hardware support for DSP in FPGADSP problems share similar properties
Algorithms are numerically insensitive but have very simple control structures
Controlled numerical error is acceptable SNR exist for measuring numeric precision
Design is performed in SimulinkDesigner need not deal with low level implementation issues
Reconfigurable Computing
The word-length optimisationUnlike mP based implementations size of each variable is customisable.Numerical accuracy, design size, speed and power cons.Most important decision is selection of an appropriate word-length and scaling for each signalThe accuracy is less sensitive to some variables than to othersConsidering error and area information, it is possible to achieve a highly efficient DSP implementationWord-length optimisation problem is NP-hardHeuristics are used, area/signal quality tradeoffAnalytic methods are faster but pessimistic
Area % Speedup %
Bitwise 15-56 65
MATCH 80 20
Wadeker&Parker
15-40
Bitsize 20-30
Reconfigurable Computing
Other Design Methods
Run-time customisationSoft instruction processorsMulti-FPGA compilation
Reconfigurable Computing
Run-time customisation
One part of the system continues to be operational, while other part is being reconfiguredAt compile time, an initial configuration bitstream and incremental bitstreams have to be producedRuntime design optimisation techniques
Runtime constraint propagation, producing a smaller circuit with higher performance by boolean algebra optimisation
Library compilation, precompiled modules are loaded into reconfigurable resources by procedure call mechanisms
Exploiting information about program branch probabilities Promote utilization by dedicating more resources the
branches which execute more frequently Hardware compiler produces a collection of designs, each
optimised for a particular branch probability, best one is selected at runtime
Reconfigurable Computing
Soft Instruction Processor
Two examples of soft instruction processors are MizroBlaze and NiosCustomisation of resources and instructions is supportedTime for instruction fetch and decode is reduced, each custom instruction replaces several regular instructionsAdditional resources can be assigned to a custom instruction to improve the performance
Reconfigurable Computing
Multi-FPGA Compilation
Compiler can generate designs using speculative and lazy execution to improve the performanceA single program is partitioned between host and reconfigurable resources
Reconfigurable Computing
Dynamic Instruction Set Computer
Reconfigurable Computing
DISC-Example Code
Reconfigurable Computing
DISC-Example Application