P-Channel 2.5-V (G-S) MOSFET - Vishay - … · Document Number: 72749 S-09-0660-Rev. C, 20-Apr-09 5...

Vishay SiliconixSi3443BDV

Document Number: 72749S-09-0660-Rev. C, 20-Apr-09

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P-Channel 2.5-V (G-S) MOSFET

FEATURES • Halogen-free According to IEC 61249-2-21

Definition • TrenchFET® Power MOSFET • 100 % Rg Tested • Compliant to RoHS Directive 2002/95/EC

PRODUCT SUMMARY VDS (V) RDS(on) (Ω) ID (A)

- 20

0.060 at VGS = - 4.5 V - 4.7

0.090 at VGS = - 2.7 V - 3.8

0.100 at VGS = - 2.5 V - 3.7

TSOP-6Top V iew

6

4

1

2

3

5

2.85 mm

3 mm

Ordering Information:

Si3443BDV-T1-E3 (Lead (Pb)-free)Si3443BDV-T1-GE3 (Lead (Pb)-free and Halogen-free)

Part Marking Code: 3B

(4) S

(3) G

(1, 2, 5, 6) D

P-Channel MOSFET

Notes a. Surface Mounted on FR4 board, t ≤ 5 s.

For SPICE model information via the Worldwide Web: www.vishay.com/www/product/spice.htm

ABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise notedParameter Symbol 5 s Steady State Unit

Drain-Source Voltage VDS - 20V

Gate-Source Voltage VGS ± 12

Continuous Drain Current (TJ = 150 °C)aTA = 25 °C

ID- 4.7 - 3.6

ATA = 70 °C - 3.8 - 2.8

Pulsed Drain Current IDM - 20

Continuous Source Current (Diode Conduction)a IS - 1.7 - 0.9

Maximum Power DissipationaTA = 25 °C

PD2.0 1.1

WTA = 70 °C 1.3 0.7

Operating Junction and Storage Temperature Range TJ, Tstg - 55 to 150 °C

THERMAL RESISTANCE RATINGS Parameter Symbol Typical Maximum Unit

Maximum Junction-to-Ambientat ≤ 5 s

RthJA50 62.5

°C/WSteady State 90 110

Maximum Junction-to-Foot (Drain) Steady State RthJF 30 36

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Notesa. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %.b. Guaranteed by design, not subject to production testing.

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operationof the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximumrating conditions for extended periods may affect device reliability.

TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted

SPECIFICATIONS TJ = 25 °C, unless otherwise notedParameter Symbol Test Conditions Min. Typ. Max. Unit

Static

Gate Threshold Voltage VGS(th) VDS = VGS, ID = - 250 µA - 0.6 - 1.4 V

Gate-Body Leakage IGSS VDS = 0 V, VGS = ± 12 V ± 100 nA

Zero Gate Voltage Drain Current IDSSVDS = - 20 V, VGS = 0 V - 1

µAVDS = - 20 V, VGS = 0 V, TJ = 70 °C - 5

On-State Drain Currenta ID(on) VDS = - 5 V, VGS = - 4.5 V - 15 A

Drain-Source On-State Resistancea RDS(on)

VGS = - 4.5 V, ID = - 4.7 A 0.048 0.060

ΩVGS = - 2.7 V, ID = - 3.8 A 0.070 0.090

VGS = - 2.5 V, ID = - 1 A 0.080 0.100

Forward Transconductancea gfs VDS = - 10 V, ID = - 4.7 A 11 S

Diode Forward Voltagea VSD IS = - 1.7 A, VGS = 0 V - 0.8 - 1.2 V

Dynamicb

Total Gate Charge Qg

VDS = - 10 V, VGS = - 4.5 V, ID = - 4.7 A

6 9

nCGate-Source Charge Qgs 1.4

Gate-Drain Charge Qgd 1.9

Gate Resistance Rg f = 1 MHz 5 9.5 16.2 Ω

Turn-On Delay Time td(on)

VDD = - 10 V, RL = 10 Ω ID ≅ - 1.0 A, VGEN = - 4.5 V, Rg = 6 Ω

22 35

ns

Rise Time tr 35 55

Turn-Off Delay Time td(off) 45 70

Fall Time tf 25 40

Source-Drain Reverse Recovery Time

trr IF = - 1.7 A, dI/dt = 100 A/µs 25 50

Output Characteristics

0

4

8

12

16

20

0 1 2 3 4 5

VGS = 5 V thru 3.5 V

2.5 V

2 V

3 V

1.5 V

I D -

Dra

in C

urre

nt (

A)

VDS - Drain-to-Source Voltage (V)

Transfer Characteristics

0

4

8

12

16

20

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

TC = - 55 °C

125 °C

25 °C

I D -

Dra

in C

urre

nt (

A)

VGS - Gate-to-Source Voltage (V)


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On-Resistance vs. Drain Current

Gate Charge

Source-Drain Diode Forward Voltage

0.00

0.04

0.08

0.12

0.16

0.20

0 4 8 12 16 20

VGS = 2.7 V

VGS = 4.5 V

VGS = 2.5 V

ID - Drain Current (A)

- O

n-R

esis

tanc

e(Ω

)R

DS

(on)

0

1

2

3

4

5

0 1 2 3 4 5 6 7 8

ID = 4.7 A

VDS = 10 V

Qg - Total Gate Charge (nC)

VG

S -

Gat

e-to

-Sou

rce

Vol

tage

(V

)

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4

TJ = 150 °C

30

10

1

TJ = 25 °C

I S -

Sou

rce

Cur

rent

(A

)

VSD - Source-to-Drain Voltage (V)

Capacitance

On-Resistance vs. Junction Temperature

On-Resistance vs. Gate-to-Source Voltage

0

200

400

600

800

1000

0 4 8 12 16 20

Crss

Coss

Ciss

C -

Cap

acita

nce

(pF

)


0.6

0.7

0.8

0.9

1.0

1.1

1.2

1.3

1.4

1.5

1.6

- 50 - 25 0 25 50 75 100 125 150

ID = 4.7 A

VGS = 10 V

RD

S(o

n) -

On-

Res

ista

nce

(N

orm

aliz

ed)

TJ - Junction Temperature (°C)

0.00

0.04

0.08

0.12

0.16

0.20

0 1 2 3 4 5

ID = 4.7 A

ID = 1 A

VGS - Gate-to-Source Voltage (V)

- O

n-R

esis

tanc

e(Ω

)R

DS

(on)

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Threshold Voltage

- 0.4

- 0.2

0.0

0.2

0.4

0.6

- 50 - 25 0 25 50 75 100 125 150

ID = 250 µA

VG

S(t

h) V

aria

nce

(V)

TJ - Temperature (°C)

Single Pulse Power

0

50

10

Pow

er (

W)

Time (s)

20

1 100 6001010-110-210-3

30

40

Safe Operating Area

100

1

0.1 1 10 100

0.01

10

TA = 25 °CSingle Pulse

DC0.1

P(t) = 1 s, 10 s

P(t) = 0.1 s

P(t) = 0.01 s

P(t) = 0.001 s

I D -

Dra

in C

urre

nt (

A)


Limited by R(DS)on*

* VGS > minimum VGS at which RDS(on) is specified

ID(on)Limited

BVDSS Limited

IDM Limited

Normalized Thermal Transient Impedance, Junction-to-Ambient

10-3 10-2 1 10 60010-110-4 100

2

1

0.1

0.01

0.2

0.1

0.05

0.02

Single Pulse

Duty Cycle = 0.5

Square Wave Pulse Duration (s)

Nor

mal

ized

Effe

ctiv

e T

rans

ient

The

rmal

Impe

danc

e

1. Duty Cycle, D =

2. Per Unit Base = RthJA = 90 °C/W

3. TJM - TA = PDMZthJA(t)

t1t2

t1t2

Notes:

4. Surface Mounted

PDM


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Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for SiliconTechnology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, andreliability data, see www.vishay.com/ppg?72749.

Normalized Thermal Transient Impedance, Junction-to-Foot

10-3 10-2 1 1010-110-4

2

1

0.1

0.01

0.2

0.1

0.05

0.02

Single Pulse

Duty Cycle = 0.5

Square Wave Pulse Duration (s)

Nor

mal

ized

Effe

ctiv

e T

rans

ient

The

rmal

Impe

danc

e

Vishay SiliconixPackage Information

Document Number: 7120018-Dec-06

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1 2 3

Gauge Plane

L

5 4

R

R

C 0.15 M B A b

C 0.08

0.17 Ref

Seating Plane

-C-

Seating Plane

A 1

A 2 A

-A - D

-B -

E 1 E

L 2

(L 1 )

c

4x 1

4x 1

e

e1

1 2 3

6 5 4

C 0.15 M B A b

-B -

E 1 E

e

e1

5-LEAD TSOP 6-LEAD TSOP

TSOP: 5/6−LEADJEDEC Part Number: MO-193C

MILLIMETERS INCHES

Dim Min Nom Max Min Nom Max A 0.91 - 1.10 0.036 - 0.043

A 1 0.01 - 0.10 0.0004 - 0.004

A 2 0.90 - 1.00 0.035 0.038 0.039

b 0.30 0.32 0.45 0.012 0.013 0.018

c 0.10 0.15 0.20 0.004 0.006 0.008

D 2.95 3.05 3.10 0.116 0.120 0.122

E 2.70 2.85 2.98 0.106 0.112 0.117

E 1 1.55 1.65 1.70 0.061 0.065 0.067

e 0.95 BSC 0.0374 BSC

e 1 1.80 1.90 2.00 0.071 0.075 0.079

L 0.32 - 0.50 0.012 - 0.020

L 1 0.60 Ref 0.024 Ref

L 2 0.25 BSC 0.010 BSC

R 0.10 - - 0.004 - -

0 4 8 0 4 8

1 7 Nom 7 Nom

ECN: C-06593-Rev. I, 18-Dec-06DWG: 5540

AN823Vishay Siliconix

Document Number: 7174327-Feb-04

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Mounting LITTLE FOOT� TSOP-6 Power MOSFETs

Surface mounted power MOSFET packaging has been based onintegrated circuit and small signal packages. Those packageshave been modified to provide the improvements in heat transferrequired by power MOSFETs. Leadframe materials and design,molding compounds, and die attach materials have beenchanged. What has remained the same is the footprint of thepackages.

The basis of the pad design for surface mounted power MOSFETis the basic footprint for the package. For the TSOP-6 packageoutline drawing see http://www.vishay.com/doc?71200 and seehttp://www.vishay.com/doc?72610 for the minimum pad footprint.In converting the footprint to the pad set for a power MOSFET, youmust remember that not only do you want to make electricalconnection to the package, but you must made thermal connectionand provide a means to draw heat from the package, and move itaway from the package.

In the case of the TSOP-6 package, the electrical connections arevery simple. Pins 1, 2, 5, and 6 are the drain of the MOSFET andare connected together. For a small signal device or integratedcircuit, typical connections would be made with traces that are0.020 inches wide. Since the drain pins serve the additionalfunction of providing the thermal connection to the package, thislevel of connection is inadequate. The total cross section of thecopper may be adequate to carry the current required for theapplication, but it presents a large thermal impedance. Also, heatspreads in a circular fashion from the heat source. In this case thedrain pins are the heat sources when looking at heat spread on thePC board.

Figure 1 shows the copper spreading recommended footprint forthe TSOP-6 package. This pattern shows the starting point forutilizing the board area available for the heat spreading copper. Tocreate this pattern, a plane of copper overlays the basic pattern onpins 1,2,5, and 6. The copper plane connects the drain pinselectrically, but more importantly provides planar copper to drawheat from the drain leads and start the process of spreading theheat so it can be dissipated into the ambient air. Notice that theplanar copper is shaped like a “T” to move heat away from thedrain leads in all directions. This pattern uses all the available areaunderneath the body for this purpose.

FIGURE 1. Recommended Copper Spreading Footprint

0.0491.25

0.0100.25

0.0140.35

0.0741.875 0.122

3.1

0.0260.65

0.1674.25

0.0491.25

Since surface mounted packages are small, and reflow solderingis the most common form of soldering for surface mountcomponents, “thermal” connections from the planar copper to thepads have not been used. Even if additional planar copper area isused, there should be no problems in the soldering process. Theactual solder connections are defined by the solder maskopenings. By combining the basic footprint with the copper planeon the drain pins, the solder mask generation occurs automatically.

A final item to keep in mind is the width of the power traces. Theabsolute minimum power trace width must be determined by theamount of current it has to carry. For thermal reasons, thisminimum width should be at least 0.020 inches. The use of widetraces connected to the drain plane provides a low impedancepath for heat to move away from the device.

REFLOW SOLDERING

Vishay Siliconix surface-mount packages meet solder reflowreliability requirements. Devices are subjected to solder reflow as atest preconditioning and are then reliability-tested usingtemperature cycle, bias humidity, HAST, or pressure pot. Thesolder reflow temperature profile used, and the temperatures andtime duration, are shown in Figures 2 and 3.

Ramp-Up Rate +6�C/Second Maximum

Temperature @ 155 � 15�C 120 Seconds Maximum

Temperature Above 180�C 70 − 180 Seconds

Maximum Temperature 240 +5/−0�C

Time at Maximum Temperature 20 − 40 Seconds

Ramp-Down Rate +6�C/Second Maximum

FIGURE 2. Solder Reflow Temperature Profile

http://www.vishay.com/doc?71200

http://www.vishay.com/doc?72610

AN823Vishay Siliconix

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Document Number: 7174327-Feb-04

255 − 260�C

1�4�C/s (max) 3-6�C/s (max)

10 s (max)

Reflow ZonePre-Heating Zone

3�C/s (max)

140 − 170�C

Maximum peak temperature at 240�C is allowed.

FIGURE 3. Solder Reflow Temperature and Time Durations

60-120 s (min)

217�C

60 s (max)

THERMAL PERFORMANCE

A basic measure of a device’s thermal performance is thejunction-to-case thermal resistance, R�jc, or thejunction-to-foot thermal resistance, R�jf. This parameter ismeasured for the device mounted to an infinite heat sink andis therefore a characterization of the device only, in otherwords, independent of the properties of the object to which thedevice is mounted. Table 1 shows the thermal performanceof the TSOP-6.

TABLE 1.

Equivalent Steady State Performance—TSOP-6

Thermal Resistance R�jf 30�C/W

SYSTEM AND ELECTRICAL IMPACT OF

TSOP-6

In any design, one must take into account the change inMOSFET rDS(on) with temperature (Figure 4).

0.6

0.8

1.0

1.2

1.4

1.6

−50 −25 0 25 50 75 100 125 150

VGS = 4.5 VID = 6.1 A

On-Resistance vs. Junction Temperature

TJ − Junction Temperature (�C)

FIGURE 4. Si3434DV

r DS

(on)

− O

n-R

esiis

tanc

e(N

orm

aliz

ed)

Application Note 826Vishay Siliconix

www.vishay.com Document Number: 7261026 Revision: 21-Jan-08

A

PP

LIC

AT

ION

NO

TE

RECOMMENDED MINIMUM PADS FOR TSOP-6

0.11

9

(3.0

23)

Recommended Minimum PadsDimensions in Inches/(mm)

0.099

(2.510)

0.06

4

(1.6

26)

0.02

8

(0.6

99)

0.039

(1.001)

0.020

(0.508)

0.019

(0.493)

Return to Index

Return to Index

Legal Disclaimer Noticewww.vishay.com Vishay

Revision: 08-Feb-17 1 Document Number: 91000

DisclaimerALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.

Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product.

Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. To the maximum extent permitted by applicable law, Vishay disclaims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, including without limitation special, consequential or incidental damages, and (iii) any and all implied warranties, including warranties of fitness for particular purpose, non-infringement and merchantability.

Statements regarding the suitability of products for certain types of applications are based on Vishay’s knowledge of typical requirements that are often placed on Vishay products in generic applications. Such statements are not binding statements about the suitability of products for a particular application. It is the customer’s responsibility to validate that a particular product with the properties described in the product specification is suitable for use in a particular application. Parameters provided in datasheets and / or specifications may vary in different applications and performance may vary over time. All operating parameters, including typical parameters, must be validated for each customer application by the customer’s technical experts. Product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed therein.

Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the Vishay product could result in personal injury or death. Customers using or selling Vishay products not expressly indicated for use in such applications do so at their own risk. Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications.

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P-Channel 2.5-V (G-S) MOSFET - Vishay - … · Document Number: 72749 S-09-0660-Rev. C, 20-Apr-09 5...

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