Lecture 20-1

MOSFET transistor I-V characteristics

iD K 2 vGS Vt–( )vDS vDS2

–[ ]=

iD

vGS vDS--

++

iD K vGS Vt–( )2[ ] 1 λvDS+( )=

KW2L------Kn=

Kn Coxµn=iD K 2 vGS Vt–( )vDS[ ]=Linear region:

vDSsat

vGS Vt–=

vDS vGS Vt–«

Triode region:

vDS vGS Vt–<

(current) Saturation region:

vDS vGS Vt–≥

Lecture 20-2

Is the transistor in saturation region?

vDSsat

vGS Vt–=

VG 4V=

Vt 1V=

VS 2V=

VD 3.5V=

VG =

VS 2V=

VD 3.5V=

Lecture 20-3

Body Effect

• The source and bulk will not be at zero volts all of the time

• The p-type bulk will be connected to the lowest supply voltage for an IC

• Discrete MOSFETs may have bulk tied directly to the source

• But for ICs we can assume that there can be a positive VSB for NMOSFETs

VS2>0

VS1B=0

VB

VS2B=0

VS1B=0

VS2B>0

Lecture 20-4

Body Effect

• Positive VSB for NMOSFETs tends to increase QB, hence decrease QI, for a fixed VGS

VB

VGS > Vt

+

n+n+ QB0

VS>0 QI

VDS > 0

Lecture 20-5

Body Effect

• Modeled as a change in the threshold voltage as a function of VSB

• The source is, by definition for NMOSFET, at a lower positive potential than the drain, which is why we use it as our reference voltage

Vt Vt0 γ 2φf VSB+ 2φf–( )+=

• SPICE will calculate this variation in threshold voltage, or you can over-ride its calculation by directly specifying gamma

Lecture 20-6

Temperature Variations• The threshold voltage varies with temperature due to carrier generation in the

substrate --- tends to decrease with increasing temperature

• ~2mV for every 1ºC increase

• K also changes with temperature due to change in mobility

• Tends to dominate temperature variation for large iD

• Will i D increase or decrease with temperature?

Vt Vt0 γ 2φf VSB+ 2φf–( )+=

T1

T2 > T1

I12---µnC

oxWL----- vGS Vt–( )2∝

Lecture 20-7

Where is drain, where is source?

S

D

GB

D

GB

S

n-channel transistor p-channel transistor

Lecture 20-8

PMOSFETs

• All of the voltages are negative

• Carrier mobility is about half of what it is for n channels

p+

n

S DG

B

p+

• The bulk is now connected to the most positive potential in the circuit

• Strong inversion occurs when the channel becomes as p-type as it was n-type

• The inversion layer is a positive charge that is sourced by the larger potential and drained at the smallest potential

• The threshold voltage is negative for an enhancement PMOSFET

• Note that the flatband voltage (which is negative) effects now tend to increase the PFET threshold while they decreased the NFET threshold

Lecture 20-9

PMOS

• The equations are the same, but all of the voltages are negative

• Triode region:

iD K 2 vGS Vt–( ) vDS vDS2

–[ ]=

vGS Vt≥ vDS vGS Vt–≤

K12---µnCox

WL-----=

A

V2

-------

• iD is also negative --- positive charge flows into the drain

• Saturation expression is the same as it is for NFETs:

iDsat

K vGS Vt–( )2[ ] 1 λ vDS+( )=+V dd

Lecture 20-10

PMOS

• Characteristic appears to be the same, except that all of the voltages are negative

-5 -4 -3 -2 -1 0

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0

10

W=1 micronL=1 micronsV t0= -1 voltK p=2e-5 (A/v 2)phi =-0.6ND=1e15

I DS

(µA

)

VDS

VGS=-2.5V

VGS=-2.0V

VGS=-1.5V

VGS=-1.0V

VGS=-3.0V

Lecture 20-11

PMOS

• But it is generally displayed as:

W=1 micronL=1 micronsV t0= -1 voltK p=2e-5 (A/v 2)phi =-0.6ND=1e15

-ID

S (µ

A)

-VDS

VGS=-2.5V

VGS=-2.0V

VGS=-1.5V

VGS=-1.0V

VGS=-3.0V

0 1 2 3 4 5

-10

0

10

20

30

40

50

60

70

80

90

100

Lecture 20-12

Depletion Mode NMOSFET

• Depletion mode FETs have a channel implanted such that there is conduction with VGS=0

• The operation is the same as the enhancement mode FET, but the threshold voltage is shifted

• Vt is negative for depletion NMOS, and positive for depletion PMOS

VGS

n+n+

VS VDS

n+

p

Lecture 20-13

Depletion Mode NMOSFET

• Negative gate voltage is required to turn the channel off

W=1 micronL=1 micronsV t0= -2 voltK p=2e-5 (A/v 2)

I DS

(mA

)

VDS

VGS=1.0V

VGS=0.0V

VGS=-1.0V

VGS=-2.0V

VGS=2.0V

0 1 2 3 4 5

0.0

0.2

0.4

Lecture 20-14

Depletion Mode NMOSFET

• The iDS vs. vGS characteristic is still quadratic in saturation

W=1 micronL=1 micronsV t0= -2 voltK p=2e-5 (A/v 2)

I DS

(mA

)

VGS

-4 -3 -2 -1 0 1 2 3 4 5

0

1

2

Lecture 20-15

Examples

• Find the largest value that RD can have before the transistor fails to operate in saturation

5V

-5V

5kΩ

RD

Vt 2V=

Kn 20µA V2⁄=

L 10µm=

W 400µm=

λ 0=

Lecture 20-16

Examples

• Find the drain currents and voltages for both transistors

10V

10kΩ 15kΩ

Vt 2V=

Kn 20µA V2⁄=

L 10µm=

W 100µm=

λ 0=

10V

M2 M1

Lecture 20-17

Examples

• What is the effective resistance of the transistor in the triode region?

10V

24.8kΩ Vt 1V=

K 0.5mA V2⁄=

Lecture 20-18

Examples

• Select the R’s so that the gate voltage is 4V, the drain voltage is 4V and the current is 1mA.

10V

RD

Vt 2V=

K 1mA V2⁄=

λ 0=

RS

10V

RG1

RG2

Lecture 20-19

Examples

• Select the R’s so that the transistor is in saturation with a drain current of 1.0mA and a drain voltage of 5V

Vt 1– V=

K 0.5mA V2⁄=

λ 0=

RD

10V

RG1

RG2

Lecture 20-20

Examples

• Solve for the drain current and voltage

20V

32kΩ

Vt 2– V=

K 1mA V2⁄=

λ 0=

4kΩ 10MΩ