IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 41, NO. 5, MAY 1994 745

Metallized Ultra-Shallow-Junction Device Technology for Sub-0.1 pm Gate MOSFET’s

Digh Hisamoto, Member, IEEE, Kaori Nakamura, Masayoshi Saito, Member, IEEE, Nobuyoshi Kobayashi, Member, IEEE, Shin’ichiro Kimura, Member, IEEE, Ryo Nagai, Takashi Nishida, and Eiji Takeda, Senior Member, IEEE

Abstract-This paper describes a new ultra-thin SOI-CMOS structure offering reduced parasitic diffusion-layer resistance. It addresses ways to deal with the ultra-shallow junctions required by sub-0.1 pm MOSFET’s. Based on a CVD tungsten process we experimentally investigate the characteristics of selectively grown tungsten used in the source and drain region made in SO1 layers of various thicknesses ranging from 10 to 200 nm. We also investigate certain CMOS device characteristics. The SOI-CMOS structure, with low parasitic diffusion-layer resistance and good contact characteristics for ultra-shallow junction devices exhibits superior device performance and high scalability.

I. INTRODUCTION

NE of the most severe problems for MOSFET-device 0 scaling in the submicron regime is the reduction in device performance due to parasitic capacitance and parasitic resistance. This occurs mainly because device scaling strongly involves both ultra-shallow junction depth which induces high parasitic resistance and suppressed depletion-layer width due to increased substrate impurity concentration which induces large parasitic capacitance. Some modified device structures have been proposed to eliminate these effects [ll-[3]. How- ever, they involve complex fabrication processes that result in a loss of simplicity, a quality which gives MOSFET’s their special merit of improved performance due to device scaling.

Thus we paid attention to use ultra-thin SO1 substrates in order to ensure the simplicity. It is well known that using the SO1 substrate the parasitic capacitance is greatly reduced without superfluous processes [4]-[6]. In addition, an ultra- shallow junction, which cannot be made by conventional ion-implantation processes because of the spread of impurities, can be made. However, a problem still exists in that the shallow junctions increase parasitic resistance. The widely used self-aligned silicidation process for reducing parasitic resistance is not applicable to an ultra-thin SO1 substrate. This is because even minor material inhomogeneities present during the silicide-reaction may lead to fatal defects, such as cavities in the Si layer [7], even though silicides are stable at high temperatures and in some acids.

Therefore, we propose a new device structure that is based on the combination of an SO1 substrate and a CVD tungsten process [8]-[ 121 which eliminates the need for a reaction between the SOI-Si and the tungsten. The deposited tungsten

Manuscript received September 29, 1993; revised January 4, 1994. The

The authors are with the Central Research Laboratory, Hitachi, Ltd.,

IEEE Log Number 9400014.

review of this paper was arranged by Associate Editor J. R. Pfiester.

Kokubunji Tokyo 185, Japan.

layers offer low resistance and easily provide good contact with the interconnection layer. Using bonded SO1 wafers, the characteristics of the selectively grown CVD-tungsten layers were carefully investigated for SO1 layers of various thicknesses (10-200 nm). CMOS devices as small as 0.1 pm were fabricated to demonstrate the validity of the selectively deposited metal structures for using in future sub-0.1-pm devices.

11. DEVICE FABRICATION

In this section, we summarized the total process for the sake of understanding the device structure. The original material used was bonded SO1 (100) wafers with a I-pm buried oxide layer. The SO1 layer was thinned by oxidation and wet etching to thicknesses ranging from 10 to 200 nm. A 350-nm-thick LOCOS process was used for device isolation. The thickness of the gate oxide was 6 nm. The gate electrode was made from 60-nm poly Si with heavily doped phosphorus, 80-nm WSi, and 200-nm-thick CVD SiOz. After etching the gate materials, the first spacers were fabricated to reduce the overlap between the gate electrode and the source and drain diffusion layers. To cover the Si surface of the wafer’s peripheral area, CVD Si02 was deposited and a 60-nm-thick spacer was fabricated around the gate electrode.

After cleaning the Si active region surfaces, CVD tungsten was selectively deposited on the n- and p-junction areas simultaneously. Then, by the same process as that used in conventional structures, CVD-tungsten and CVD-TiNhungsten stacked layers were used for metallizations. All metallization processes are performed under 500°C

Fig. 1 compares the newly proposed stacked metal device structure to the conventional silicide structure giving the main features of each structure. The merits of new structure are very attractive for developing sub-0.1 pm MOSFET’s, though there are some difficulties to overcome. Fig. 2 shows an SEM of the typical device cross section.

111. SELECTIVE CVD TUNGSTEN PROPERTIES

Tungsten was deposited by applying selective tungsten processes (WFG/SiH4 [9]-[ 1 11) to SOI-CMOS. The selectivity of this process was so good that no tungsten layers formed on the Si02. Fig. 3 compares the growth rates of the n and p areas. The variation in thickness is mainly caused by protuberances of the rim areas. The n region is slightly thicker than the p region, but this difference causes no problem in

0018-9383/94$04.00 0 1994 IEEE

146

Silicide on SOI

-Complexity of Slmetal reaction contr0

-Thin ailldde layer cauaea InrufflClent raiatmco reduction difficulty in contact fabrication

+Stability at a high temperature

Stacked Metal on SO1

C SWetal maction free

CThlck metal layer otter8 sufficient mIMm reduction eaay contact hbrlcation

-Necessity for low temperature proaru

Fig. 1 . Comparison between conventional silicide structure and stacked metal structure.

-1.0 urn--

Fig. 2 . Cross sectional SEM picture of fabricated device structure.

400

300

200

- - - P

4

I N I P

Deposition Time ( sec ) Fig. 3. Relationship between deposition time and thickness on 1 1 - and psi.

CMOS devices. For transistor fabrication, CVD tungsten was deposited for 14 s at 28OOC.

A pure metal layer provides much lower sheet and contact resistance than silicides. The tungsten layers deposited on the n- and p-areas were 80 and 70 nm thick giving sheet resis- tances of 3.9 and 5.0 R/sq, respectively. Contact resistance of sub-pm diameter holes between the diffusion layer (selective tungsten) and the metal interconnection layer (tungsten) were shown in Fig. 4. These values are sufficiently small compared with channel resistances expected for sub-0.1 pm MOSFET's.

Fig. 5 shows SEM top views of the deposited tungsten layers and Fig. 6 shows cross sections. Grain boundaries are apparent in Fig. 5, but, as shown in Figs. 2 and 6, the Tungsten layers are continuous and uniform. Fig. 5 also shows the Si surface under the tungsten layers, as seen after removal of

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 41, NO. 5, MAY 1994

3 -

2 -

1 -

0.0 0.5 1 .o Contact Hole Diameter ( um )

Fig. 4. Contact resistance versus contact hole diameter.

I 1 a s d e p o 1 H202etch I

L 1 .O pm- Fig. 5. Top view SEM picture of the surface conditions.

tungsten with H 2 0 2 . Except for the small wrinkles, which are presumably caused by the reaction in the early steps of deposition, the Si surfaces are smooth. The small size of these wrinkles indicates that the reaction between Si and tungsten is sufficiently suppressed mainly because of the low deposition temperature of 28OOC. Fig. 6 shows a tungsten layer deposited on a 30-nm SO1 layer. The junction region of the 30-nm SO1 layer was polycrystalline, because solid-phase epitaxy does not occur in such a thin Si layer. However, the channel region acts as an epitaxial seed layer at the side of the gate, and thus causing no degradation of the p n junction and MOSFET's device characteristics.

Pn junction characteristics are measured using relatively thick SO1 devices, because there is no substrate contact for thin SO1 devices. The results are illustrated in Fig. 7. Satisfactory I-V characteristics of the n and p junctions were obtained as shown in Fig. 7. As shown in the SEM pictures, it can be conformed by electrical measurement that the reaction between Si and tungsten layer are suppressed completely.

Using bulk wafers, we studied if the tungsten layer affected the junction profiles. Fig. 8 shows the impurity distribution

HISAMOTO et al.: METALIZED ULTRA-SHALLOW-JUNCTION DEVICE TECHNOLOGY 141

Selective W

Ultra-Thin SO1

Buried Si02

U

0.1 pn

Fig. 6. Cross-sectional SEM pictures of the tungsten layer and the SO1 layer.

-2.0 0.0 2.0-2.0 0.0 2.0 vi (VI Vi (VI

Fig. 7. PN junction I-\’ characteristics

solid line la rele

s I

E 8

0 100 200 300 0 100 200 300 Depth (nm) Depth (nm)

(a) (b)

Fig. 8. layer using differential Hall measurement, (a) p+ region, (b) n+region.

Measured impurity distribution under selectively deposited tungsten

under the tungsten layers. Using the differential Hall mea- surement method, the concentration of n+ p-substrate and p+ n-substrate were measured and then compared with the refer- ences. Since the impurity profiles conformed to the references, the problem of impurity redistribution, a severe problem of the silicidation process, does not arise. Consequently, it seems that there are no problems involving metal-silicon interface contact.

IV. DEVICE CHARACTERISTICS

In this section, we aimed at evaluating the effects of the tungsten layer as device characteristics and the feasibility of this structure for a sub-0.1 -pm-MOSFET process was investi- gated by fabricating short channel devices. The channel width,

4.0 I I 4.0 I I

U E Y

c)

E 3

2.0k

0.0 0.0 -1 .o -2.0

Vd ( V )

Fig. 9. 5 pm.

I-\- characteristics of MOSFET’s with Lg = 0.16 pm and Wg =

2500, I

0.0 1 .o 2.0

Gate Length ( Fm )

Fig. 10. gate bias. Drain voltage is 0.1 V.

Channel resistance dependence on the gate length as a function of

Wg, is 5 pm. Fig. 9 shows the transistor I-V characteristics of N and PMOS SO1 devices both with an SO1 thickness of 100 nm and a gate length, Lg, 0.16 pm. The good results illustrated in Fig. 9 suggest that the selective tungsten layers induced no parasitic effects, such as localized high electric fields.

In order to see the parasitic resistance of the overall device, we measured total parasitic resistance, R, according to the Chem method [13]. By this method, the parasitic resistance is given as follow:

R = Rm + Rdif -k Rm’

where Rdif is diffusion layer resistance which we are con- cemed for and Rm and Rm’ is the other resistance such as the contact and the wire resistance. The total parasitic resistance of the source and drain electrodes for a channel width of 5 pm and a gate and contact tolerance of 2 pm is 70 R, as shown in Fig. 10. Since it seems that Rm + Rm’ account for about 50 R of this total parasitic resistance, the diffusion layer’s resistance is deemed to be negligible. And it also shows that compared with such a short-gate-length channel resistance, the parasitic resistance of the 60-nm spacer was sufficiently small.

Fig. 1 1 shows excellent NMOS subthreshold characteristics as compared with the SOI-NMOS without tungsten fabricated on the other wafer, which exhibits strong parasitic resistance at high gate voltage. The use of tungsten to reduce this resistance produced good relationships between channel current and gate length, as shown in Fig. 12.

Furthermore, the channel current when both the gate voltage and drain voltage are 1.5 V was decreased by only 0.9%, as the

748

I 1

n

U Y CI C

5 0

10-6

-8

-I

selective-W -

- Vd = 1.5 V

I I I I I I 1 I , I I -

2.0 I V -1 .o 0.0 1 .o

Fig. 1 1 . tional structure.

SOI-NMOS subthreshold characteristics compared with a conven-

n

U U

E t a

8 10 -* c I

0.1 1 .o 10 Gate Length ( pm )

Fig. 12. 1.5 V and Wg = 5 jtm.

Channel current dependence on the gate length with Vg - Vth =

distance between the gate and the contact hole increased from 1 pm to 4 pm. This shows that the CVD-tungsten process offers layout tolerance for interconnection and contact layer design because the diffusion layer with CVD-tungsten can be used as a low resistance interconnection layer.

V. DISCUSSION One drawback of this structure is that it causes parasitic

capacitance between the deposited tungsten layers and the gate. The elevated tungsten layer is separated from the gate by only the spacer layer. Since the other capacitance components are reduced, this capacitance becomes a severe load which must be driven.

Since it is difficult to estimate the capacitance associated with two-dimensional configuration, using two-dimensional numerical simulation we evaluated the parasitic capacitance between the deposited tungsten layer and the gate. Conse- quently, a simple empirical formulas for the parasitic capaci-

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 41, NO. 5, MAY 1994

1.5 r I 'I A Cj 1.00 fF/pd 0 Cj 0.25fF/pm2 t Cj 0.125 fFlpn?

Q)

.E 1.4 I- %

$ 1.3 1 d I n 'CI .- w 1.2 1 tl

A

1.1 1 zo B w Y

1.0 I I 1 10 100 1000

Tungsten Thickness (nm)

Fig. 13. time of the device without the deposited tungsten layer.

Simulated CMOS ring-oscillator delay time normalized by the delay

tance, Ct, is given as follows:

Ct K ( D / H ) 0 . 3 ( r / H ) - 0 . 6 5

where D is the tungsten deposition thickness, r is the space between deposited layer and gate edge and H is the gate height. When r is reduced, Ct increase rapidly. Therefore, the spacer thickness should be determined carefully in regards to load capacitance and increasing parasitic resistance.

Fig. 13 is a simulated relationship between D and the delay time of CMOS ring oscillators for r of 50 nm using the source and drain capacitance, Cj, as a parameter. Since the gate- tungsten layer capacitance is considerably larger than the other capacitance, the delay time rapidly increases. Consequently, for 50-nm spacer thickness and 100-nm deposition thickness, the degradation in delay time is about 10%.

Based on the this consideration, we fabricated CMOS ring- oscillators to demonstrate short-channel CMOS performance with multi-level metallization. Compared with the device without deposited tungsten layers, the additional parasitic capacitance due to the deposited tungsten layer is measured. The value of 0.25 fF/pm is slightly larger than expected one due to three-dimensional effect.

Fig. 14 shows a typical wave form for 51 stages in com- parison with bulk devices including the selective tungsten structure. For NPMOS gate lengths of 0.2/0.25 pm and supply voltage (Vcc) of 2 V, the delay time was 34 ps/stage. The delay times were much shorter than those of bulk devices, as shown in Fig. 14, in spite of only a small increase in the channel current for thinner SO1 devices. This improvement was mainly caused by the reduction in diffusion electrode parasitic capacitance due to the SO1 structure.

VI. CONCLUSION

As device feature sizes are scaled down, parasitic capaci- tance and resistance, which are anti-scaling factors, will cause severe constraints on MOSFET device performance. In order to solve this problem, we proposed a new device structure involving SO1 and selective CVD tungsten techniques. We

HISAMOTO et a/.: METALIZED ULTRA-SHALLOW-JUNCTION DEVICE TECHNOLOGY

Gate Length ( pm )

Fig. 14. (for comparison)

CMOS ring-oscillator delay time for ultra-thin SO1 and bulk devices

discussed the characteristics regarding applicability to ultra- shallow junctions, which determine device scalability.

We show that ultra-thin SO1 substrates can provide ultra- shallow junctions with low parasitic capacitance. Moreover, the CVD tungsten process eliminates the Si-Tungsten reaction inherent in silicidation processes, Tungsten layers can easily be deposited on the ultra-shallow junction without the influence of p n junction structures and electrical properties, such as cavity and leakage currents. We show this structure’s usefulness for CMOS fabrication and its superiority over the conventional silicidation process because there is no problem of contact fabrication with interconnection layers.

Consequently, we think these special features ensure high CMOS device scalability and will lead to superior sub-0.1 -pm MOSFET’s thus opening up new opportunities for Si-ULSI’s.

ACKNOWLEDGMENT

The authors wish to thank Mr. Natsuki Yokoyama and Mr. Katsunori Obata for their helpful support in the metalization process. Thanks are also due to the members of the Process Integration Center for device fabrication. They would also like to thank Dr. Makoto Ohkura, Mr. Hitoshi Kume, and Dr. Katsuhiro Shimohigashi for their helpful discussions and encouragement.

REFERENCES

H. Hone, T. Fukano, T. Ito, and H. Ishikawa, “Multiple self-alignment MOS technology (MUSA/MOST),” in IEDM Tech Dig., pp. 638-641, 1984. J. R. Pfiester, R. D. Sivan, H. Ming Liaw, C. A. Seelbach, and C. D. Gunderson, “A self-aligned elevated source/drain MOSFET,” IEEE Electron Der.. Lett.,, vo. 11, pp. 365-367, 1990. W. T. Lynch, “Self-aligned contact schemes for source-drains in submi- cron devices,” in IEDM Tech. Dig., pp. 354-357, 1987. J. P. Colinge, “Some properties of thin-film SO1 MOSFETs,” IEEE Circ. and Der.. Mag. 5 , p. 18, 1987. Y. Omura, S. Nakashima, K. Izumi, and T. Ishii, “0. I-pm-gate ultrathin- film CMOS devices using SIMOX substrate with 80-nm-thick buried oxide layer,” in D. Hisamoto, T. Kaga, and E. Takeda, “Impact of the vertical SO1 ‘DELTA’ structure on planar device technology,” IEEE Trans. Electron DeiYces, vol. 38, pp. 1419-1424, 1991. C.-Y. Lu et al . , “Process limitation and device design tradeoffs of self- aligned TiSiz junction formation in submicrometer CMOS devices,” IEEE Trans. Electron Devices, vol. 38, pp. 246254, 1991. D. Hisamoto, K. Nakamura, M. Saito, N. Kobayashi, S. Kimura, R. Nagai, T. Nishida, and E. Takeda, “Ultra-thin SO1 CMOS with selective CVD tungsten for low resistance source and drain,” in IEDM Tech. Dig., pp. 829-832, 1992. Y. Kusumoto, K. Takakuwa, H. Hashinouchi, T. Ikuta, and I. Nakayama, “A new approach to the suppression of tunneling,” Tungsten and other Refr-actor?. Metals for VLSI Applications, pp. 103-109, 1987.

lEDM Tech. Dig. , pp. 675-678, 1991.

149

T. Ohba, S. Inoue, and M. Maeda, “Selective CVD tungsten silicide for VLSI applications,” in IEDM Tech. Dig., pp. 213-216, 1987. H. Kotani, T. Tsutsumi, J . Komori, and S. Nagao, “A highly reliable selective CVD-tungsten utilizing SiH4 reduction for VLSI contacts,” in IEDM Tech. Dig. , pp. 217-220, 1987. V. V. Lee, S. A. Biellak, J. S. Cho, and S. Simon Wong, “Series resistance of devices with submicrometer source/drain areas,” IEEE Electron Dev. Lett., vol. 12, pp. 664466, 1991. J. G. J. Chem, P. Chang, R. F. Motta, and N. Godinho, “A new method to determine MOSFET channel length,” IEEE EIectron Dev. Lett., vol. EDL-I, pp. 17C173, 1980.

Digh Hisamoto (M‘OO) was bom in Tokyo, Japan, in 1960. He received the B.S. and M.S. degrees in Reaction Chemistry from the University of Tokyo, Japan, in 1984 and 1986, respectively.

In 1986, he joined Central Research Labora- tory of Hitachi Ltd., Tokyo, Japan, where he has been working on ULSI device physics and process technologies. His current research interests include semiconductor memories, thin-film SO1 materials, and deep submicron high speed MOSFET devices.

Mr. Hisamoto is a member of the JaDan Societv of Applied Physics and the Institute Electronics and Communication Engineers of Japan.

Kaori Nakamura was bom in Tokyo, Japan, in 1965. She received the B.S. degree in physics from Keio University, Kanagawa, Japan, in 1987 and the M.S. degree in physics from Ochanomizu University, Tokyo, Japan, in 1989.

In 1989 she joined the Central Research Labora- tory, Hitachi Ltd., Tokyo, Japan, where she has been engaged in the research and development of MOS devices.

Ms. Nakamura is a member of the Japan Society of Applied Physics.

Masayoshi Saito (S’78-M’84) received the B.S. . M.S., and Dr. Eng. degrees in electronics from Tohoku University, Sendai, Japan, -in 1978, 1980. and 1984, respectively.

He joined the Central Research Laboratory, Hi- tachi. Ltd. in 1984. Where he has engaged in research on MOS gate electrodes and the intercon- nections using refractory metal for ULSI. He has also been interested in and developing dielectric CVD process for multilevel interconnections.

Dr. Saito I S a member of IEEE Electron Devices Society, the Electrochemical Society and the Japan Society of Applied Physics.

750 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 41, NO. 5, MAY 1944

Nobuyoshi Kobayasbi (M’86) was born in Chiba, Japan, in 1951. He received the B.S., M.S., and Ph.D. degrees in physics from the University of Tokyo, Japan, in 1975, 1977, and 1980, respectively. His thesis theme was on the metal-nonmetal transi- tion in doped silicon at low temperatures.

In 1980, he joined the Central Research Labo- ratory, Hitachi, Ltd., Tokyo, Japan. Since 1980, he has engaged in the metalization of Si ULSI’s. He initially worked on the gate metal process for MOS- VLSI’s using pure tungsten. Then, he was involved

in the research and development of silicided shallow junctions for CMOS applications. From December 1985 to December 1986, he was a Visiting Scholar at Stanford Electronics Laboratories, Stanford, CA, where he studied surface characterization of tungsten CVD using AES. From 1987 until 1991, he was studying the tungsten CVD chemistry and its applications to sub- micron contacts and interconnections for Si ULSI. He is now senior researcher of the Central Research Laboratory.

Dr. Kobayashi is a member of the Electrochemical Society and the Japan Society of Applied Physics.

Shin’ichiro Kimura (M’89) was born in Miyagi, Japan, in 1955. He received the B.S. and M.S. de- grees in materials science from Tohoku University, Sendai, Japan, in 1978 and 1980, respectively, and the Ph.D. degree from the University of Tokyo, Japan, in 1989. The subject of his Ph.D. disserta- tion was low-temperature oxidation of silicon by microwave oxygen plasma.

In 1980, he joined the Central Research Labora- tory, Hitachi Ltd., Tokyo, Japan, where he was first involved in the research of high dielectric constant

insulators. He then worked on the plasma oxidation of silicon. From 1986 to 1988, he was working on the process design and device characterization for MOS dynamic memories for 16 Mb. During 1988 to 1989, he was a Visiting Research Associate at the University of Warwick, Coventry, U. K. He is current interests are new submicron MOSFET devices and processes.

Dr. Kimura is a member of the Japan Society of Applied Physics and the Materials Research Society.

Ryo Nagai was bom in Ehime, Japan, in 1953. He received the B.S. and M.S. degrees in metallurgy from the University of Tokyo, Tokyo, Japan, in 1975 and’ 1977, respectively.

In 1977 he joined the Semiconductor and Inte- grated Circuit Division, Hitachi Ltd., Tokyo, Japan, where he had been engaged in the development of CMOS device and process technology, and the reliability physics of MOS LSI’s. From 1985 to 1986 he was a Visiting Industrial Fellow at the Department of Electrical Engineering and Computer

Sciences, University of Califomia, Berkeley. Since 1990 he has been working on the research of deep submicrometer MOS devices at the Central Research Laboratory, Hitachi, Ltd.

Mr. Nagai is a member of the Japan Society of Applied Physics.

Takashi Nishida was born in Tokyo, Japan, in 1950. He received the B.S. and M.S. degrees in metallurgy from the University of Tokyo in 1972 and 1974, respectively.

He joined the Central Research Laboratory, Hi- tachi Ltd. in 1974, and then worked on the R&D of field emission cathode, CO2 laser assisted dielectric film deposition and InSb thin film transistor. Then, he worked on Si process technology, especially, on multilevel interconnection technology using both organic and inorganic interlevel dielectrics. He is

currently a senior researcher and in charge of LSI process facilities within CRL.

Mr. Nishida is a member of the Japan Society of Applied Physics and the Japan Institute of Metals.

Eiji Takeda (M‘82-SM‘87) was born in Ohita, Japan, in 1949. He received the B.S., the M.S., and the Ph.D. degrees in applied physics from the University of Tokyo, Tokyo, Japan, in 1972, 1975, and 1987, respectively.

He is now Department Manager in the ULSI Research Center of Central Research Laboratory, Hitachi Ltd., Japan. He has been managing VLSI memories (DRAM, SRAM’s, and EEPROM’s), Bi-CMOS, and advanced submicron MOS device- process groups. Since 1975, he has been working

for Central Research Laboratory, Hitachi Ltd., Tokyo, Japan, on VLSI device and process physics and technologies. His activities included EPROM, microfabrication, device physics, and reliability problems for VLSI’s. Since 1979, he has been working on VLSI device physics and process technologies and memory application including lM, 4M, 16M, and 64Mb DRAM’S. His activities in these area include the research and development of new submicron MOSFET structures with high reliability, in particular, double diffused drain (DDD) and gate drain overlapped drain (GOLD) structures and the analysis of hot camer effects. Since 1985, he has been also working on the alpha-particle induced soft error phenomena for VLSI’s. Recently, he has begun to work on novel devices such as thin film SOI’s, Si quantum devices, and nanometer lithography (e-beam and x-ray). He was a visiting research associate at Cambridge University, U.K. during 1983-1984. He has published and presented more than 120 intemational technical papers. Also, he published two books on hot-camer effects. His current research interests are in VLSI system reliability and architecture, as well as submicron semiconductor device physics, quantum devices and nanometer scale lithography.

Dr. Takeda was a member of the Solid State Device subcommittees of the 1986-1987 International Electron Device Meeting (IEDM), a program committees of 1988-1993 International Reliability Physics Symposium (IRPS) and a vice-program chairman of 1991-1992 SSD&M (Solid State Devices and Materials conference) He is also a program chairman of the 1994-1995 Symposium on VLSI Technology. He is a member of the Japan Society of Applied Physics, and the lnstitute of Electronics and Communication Engineers of Japan. He received the 1994 IEEE Cledo Brunetti Award for his work on hot-carrier effects.