Manual 1 3

/ & & Ver. 1, Rev. 3

91

2007

AT91

ii

2.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.1 . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.3 . . . . . . . . . . . . . . . . . . . . . 2.3.4 / . . . . . . . . . . . . . . . . . . . . . . 2.3.5 . . . . . . . . . . . . . . . . . . . . . . . . . . Assembly 91 3.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 GNU Assembler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.2 3.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5 5 8 14 14 15 20 28 32 33 33 36 37 38 44 44 45 46 50 53 55 59 59 59 63

3.3.1 32-bit . . . . . . . . . . . . . . . . . . 3.3.2 32-bit . . . . . . . . . . . . . . . . . . . . 3.3.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.4 8 bit 3.3.5 64 bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3.6 32 bit 16 bit . . . . . . . . . . 4.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 GNU tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii

AT91

69 69 69 72 77 78 78 79 80 81 82 83 84 85 86 87 88 89 90 92 94 95 96 98 99

5.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Instruction Set 6.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.1 ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.2 ADD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.3 AND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.4 BIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.5 CLZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.6 CMN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.7 CMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.8 EOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.9 MLA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.10MUL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.11ORR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.12RSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.13RSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.14SBC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.15SMLAL 6.1.16SMULL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.1.17SUB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.18TEQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.19TST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.20UMLAL

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

6.1.21UMULL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 6.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 6.2.1 LDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 6.2.2 LDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 6.2.3 LDRB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 6.2.4 LDRH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 6.2.5 LDRSB 6.2.6 LDRSH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

6.2.7 MCR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 6.2.8 MOV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 6.2.9 MRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 iv

AT91

6.2.10MRS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 6.2.11MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 6.2.12MVN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 6.2.13STM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 6.2.14STR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 6.2.15STRB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 6.2.16STRH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 6.2.17SWP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 6.2.18SWPB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 6.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 6.3.1 B,BL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 6.3.2 BX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

v

AT91

vi

AT91 & : . , : custom-made . (, , ...) . , . AT91 (AT91SAM9261EK ATMEL). AT91SAM9261, ATMEL ARM926EJ-S Advanced Risc Machines (ARM). . ( 2007) ( ) ARM PowerPC. , 70% . 200 MHz, (Harvard architecture - split caches) 16K, (MMU), (ARM / THUMB) (DSP) Jazelle Java. 1

AT91

1.

(210 MIPS) . , (GNU licensed) , . . ( Windows CE ), , ( , ) . . AT91 Linux 2.6.20. GNU : , assemblers, . GNU , (.. editors), (.. USB driver) , . AT91 , . . : . , . , . AT91, Keil / ARM GNU Microsoft. AT91 . , , , . ( , USB ) AT91 . 2

1.

AT91

AT91 . , AT91. . . . AT91 .

. / & , MSc.

. / & , PhD., .

3

AT91

1.

4

2.1 AT91SAM9261 ATMEL AT91 , ARM926EJ-S, 200 MHz. ARM926EJ-S ARM (embedded applications). ( 32bit RISC ) , ( , , video, .). (. 2.1, . 6).

RISC (Reduced Instruction Set Computer) , . , CISC (Complex Instruction Set Computer) , , .

(registers - R r) / 1 . 32 (bits) , . 2 . . 1 2

Arithmetic Logic Unit - - ALU RISC

5

AT91

2.1 -

2.1:

6

2.

AT91

, . , .

, (address bus) . . data bus, . 32 , 91 232 .

. . . . , . ( - address space). , 0 .

, . , (. ) . (resources) . Processor Modes (. 2.1 . 8). User. 7

AT91 Mode User FIQ IRQ Supervisor Abort Undened System

2.2 -

Fast Interrupt Interrupt

2.1: Processor Modes

2.2 37 , 31 6 . , 17 . 8 (r0 r7) , 7 ( , r8 Fiq User mode, r8 User). (. 2.2 . 8) ( 2.2, 9). .

Mode

User Mode Regs r0-r14, r15, CPSR r0-r7, r15, CPSR r0-r12, r15, CPSR r0-r12, r15, CPSR r0-r12, r15, CPSR r0-r12, r15, CPSR r0-r12, r15, CPSR

Additional Regs

User FIQ IRQ Supervisor Abort Undened System

r8_q-r14_q,SPSR_q r13_irq-r14_irq,SPSR_irq r13_svc-r14_svc,SPSR_svc r13_abt-r14_abt,SPSR_abt r13_und-r14_und,SPSR_und r13_sys-r14_sys,SPSR_sys

2.2: 32 , (word) 8

2.

AT91

2.2:

9

AT91

2.2 -

. , 16 ( - halfword) 8 (byte). r0 r12, . 3 , r13 r15, . , r15 (Program Counter - PC), r14 (Branch & Link) r13 (Stack Pointer). ( - Current Processor Status Register - CPSR) . , . , (status bits) 3 ( Status Register . 2.3, . 12, Status Register . 2.3, . 11. 0xWXYZ WXYZ #WXYZ WXYZ). CPSR . CPSR S .

r15 (PC) . , PC , . , PC . 4 . PC 4, 4 bytes. PC , 5 .3 4

: ... , Prefetch Abort 5 , , Undened

10

2.

AT91

Bit N Z C

1 1 1 1

V Q

1 (overow) , QADD ., CPSR. , .

J I

1 Jazelle mode Java. 1 (interrupts) IRQ. .

F

1 FIQ. I & F CPSR . .

T Mode

1 Thumb mode Thumb. 5 . 0x10 User 0x11 FIQ 0x12 FIQ 0x13 Supervisor 0x17 Abort 0x1B Undened 0x1F System 2.3: Status Register

11

AT91

2.2 -

2.3: Status Register

, 0x50000000 PC 0xC0005100, ( ) PC 0x50000000. , PC, 0x50000000 . , 0x50000000, PC , 0xC0005100. ( C . , ). , . PC . r14, PC 6 . , 0x50000000 PC, r14, Branch & Link. 0x50000000, Branch & Link PC, . , , .6

12

2.

AT91

, . , 12 , , . , (stack) . LIFO (Last In First Out) , . , , & ( ) , , , , & .

2.4: .

, , . r13 ( - Stack pointer). 32 4 bytes, 4. LIFO , 7 . Stack (. 2.4, . 13).7

13

AT91

2.3 -

2.3 , . , (. 2.3, . 14). & , . . . AND, OR, XOR. . . ,

2.4:

2.3.1

. (pipelining8). . (branch prediction) . ARM . . CPSR (Carry, Negative ) (. 2.3.1, . 15). (. ADDCS R0, R1, R2, Carry CPSR bit 1).8

pipelining .

, , . 5 , 5 , pipelining 1.

14

2. CS/HS CC/LO EQ NE VS VC MI PL GE GT HI LE LT LS C = 1 (Unsigned Higher or Same) C = 0 (Unsigned Lower) Z = 1 (Equal) Z = 0 (Not Equal) V=1 V=0 N = 1 (Minus) N = 0 (Plus) N = V (Signed Greater Than or Equal) Z = 0 N = V (Signed Greater Than) C = 1 Z = 0 (Unsigned Higher)

AT91

Z = 1 N != V (Signed Less Than or Equal) N != V (Signed Less Than) C = 0 Z = 1 (Unsigned Lower or Same)

2.5: CS ( CPSR 1) HS. . CMP, 9 . , , , 1 & 0 ( C = 1 & Z = 0 Unsigned Higher). , , CPSR .

2.3.2

:

, []9

, -

CPSR

15

AT91

2.3 -

, , [ ]. . 10 . ( (. 2.1, . 6)) (barrel shifter), . 32 ( ) 31 . (. 2.3.2, . 16).

LSL LSR ASR ROR RRX

2.6:

0 ( n n 0). n , (Carry bit) CPSR, / ( ). , 0x1035004A = 00010000 00110101 00000000 01001010 4 bits 00000011 01010000 00000100 10100000 = 0x035004A0. bit 1 ( . 2.5, . 17).10

. # , . #0x4 #25

16

2.

AT91

1 bit

N bits 32- bits

N 32- bits 0.......0

2.5:

0x49 = 0100_1001 = (4*16 + 9=73) ( x7 27 + x6 26 +. . . +x0 , x7 = 0, x6 = 1, x5 = 0, x4 = 0, x3 = 1, x2 = 0, x1 = 0, x0 = 1) xi xi+1 ( x0 0). 1001_0010 = 0x92 = (9*16 + 2 = 146), . xi 2 2. , xi 2i , 2i+1 , . , . 2 n 2n *(# ) ( 5 3 3*25 = 3*32=96). 32 , , , mod(2n *(# ), 232 ), mod 2n *(# ) 232 . 2, , . 17

AT91

2.3 -

xi xi1 ( x31 0). , xi 2i , 2i1 , . , . , n (#( )/2n ) ( 3 15 (15)/23 ) = 1). 2, . . ( . 2.6, . 18).

N bits 32- bits

N 0.......0 32- bits

1 bit

2.6:

, . 2 1 (. -15 8 1111_0001). -15 4 -4 ( -15 = -4*4 + 1, ), 2 (4 = 22 ) 0011_1100 = 60, . 1 . , 1111_1100 = -4. 18

2.

AT91

, . , N , 0 N 0, 1 N 1 ( . 2.7, . 19).

MSB 32--1 bits

N bits

N 32- bits

1 bit

2.7:

, , CPSR, . . , 0x97 = 1001_0111 CPSR x, 3 11x1_0010, 1. , 0 . , . n ( n > 1) 33-n. 1 , ADCS . . bit . 0, , CPSR ( , 1 19

AT91

2.3 -

0x49 = 0100_1001, 0x49 + 0x49 = 0x92 = 1001_0010, 0 1 1001_0011) ( . 2.8, . 20). , , .

N bits 32- bits -1 bits

N bits 32- bits

1 bit

2.8:

2.3.3

(. 2.3.3, . 21). , . , . 32 (word), 16 (halfword) 8 (byte). , . , :

Rd, [Rb, ] Rd (Register destination) r0. . . r12, Rb (Register base). Rd . Rb 20

2. LDM LDR MOV MRS MRC SWP block CoProcessor MCR CPSR MSR MVN STR STM

AT91 block CPSR CoProcessor

2.7: . , () . oset Rb. : : : r0. . . r12 ([Rb, Rx]) ([Rb, #val]). [0. . . 255] [0. . . 31] (. 0x35 0x35 left-shifted(4) = 0x350)

. bytes. , Rb Rx . , 0xC0000380, 0xC0000380 + 0, 0xC0000380 + 4 n 0xC0000380 + n - 1. 0 1! byte, 4 ( word). 0xC0000380 + 4 0xC0000380 + 8. , 0xC0000380 0xCAFEBABA 0xC0000384 21

AT91

2.3 -

0x12345678, 4 bytes Rb = 0xC0000380 Ro = 1 0x78CAFEBA. word , 4! halfword , 2. (alignment) .

. . . byte 2 , bytes. , 4 bytes bytes . ; Little Endian byte, byte byte. 0xDEADBEEF 0xC000450. 0xC000450 0xEF, 0xC000451 0xBE, 0xC000452 0xAD 0xC000453 0xDE. byte . , 0xC000450 0xDE, 0xC000451 0xAD, 0xC000452 0xBE 0xC000453 0xEF. Big Endian. bytes halfwords, 2 bytes ( 0xDEAD 0xAD 0xC000450 0xDE 0xC000451 Little Endian ). ARM , Linux Little Endian , Little Endian.

, , 2 (. 2, 4, 8, 16. . . ), ( 3 8, (3-1)*8 = 16), , (0 , 1 . . . ). 22

2.

AT91

, Rd, . ( , ), Rb, ( , ). ( ) Rb . , Rb . , . ! (. LDR R5, [R0, R2, LSL #2]! R0 R2*4, R0 ). [ ] Rb, (. LDR R5, [R0], R2, LSL #2 R0 R0 R2*4. !). Data Transfer (. 2.3.3, . 24).

block . AT91, STM ( LDM). block -- LDR, STR, (burst mode11 ). 11

Burst mode

.

23

AT91

2.3 -

R1 0x8000 R5 0x6. LDR R0, [R1] LDR R0, [R1, R5] LDR R0, [R1, #10] LDR R0, [R1, R5, LSL #2] LDR R0, [R1, R5, LSL #4]! 0x8000 R0. 0x8000 + 6 = 0x8006 R0. 0x8000 + 0xA = 0x800A R0. 0x8000 + 6*4 = 0x8018 R0. 0x8000 + 6*16 = 0x8060 R0 0x8060 R1. LDR R0, [R1], #12 0x8000 R0 0x8000 + 12 = 0x800C R1. STR R0, [R1] STR R0, [R1, #20] 0x8000 R0. 0x8000 + 20 = 0x8014 R0.

2.8: Data Transfer

24

2.

AT91

words. . , , . , , . :

Rb, {} Rb. {} ({r0, r5-r8, r15}). , , , ( r5-r8). , . 4 (Modes) :

- Increment Before (IB) , 4. - Increment After (IA) 4 . - Decrement Before (DB) , 4. - Decrement After (DA) 4 . , block, (Rb) ( Increment Rb Rb + 4 * (# ), Decrement Rb Rb - 4 * (# ). ! . 25

AT91

2.3 -

Rb , Rb ( ). Multiple Data Transfer (. 2.3.3, . 26).

R1 0x8000. LDMIB R1, {R0, R2-R5} 0x8004 R0, 0x8008 R2 . LDMDA R1, {R0, R2-R5} 0x8000 R5, 0x7FFC R4 0x7FF0 R0. LDMDA R1!, {R0, R2-R5} , R1 (0x8000 - 4*5 = 0x7FEC). STMIA R1, {R0, R2-R5} STMDB R1, {R0, R2-R5} 0x8000 R5, 0x8004 R2 . R5 0x7FFC, R4 0x7FF8 .

2.9: Multiple Data Transfer . , STMDA, LDMIB, STMIA LDMDB. , MOV, MOV Rd, . Rd , , . , 26

2.

AT91

8 ( 255 0xFF). ( 255) 31 . , 0xFF, 0xDA0000, 0xF0000000 0xFF , 0xDA 16 0xF0 24 . 0xDA0010, 0xF0003200, 0x254 , (8 ) * ( 2). MVN MOV, Rd ( bits 1 0 ). Register to Register Transfer (. 2.3.3, . 27).

MOV R1, R2 MOV R1, R2, LSL #5 MOVS R1, R2, LSL #5

R1 R2. R1 R2, 5 . , Carry bit CPSR bit .

MOV R1, #0x35 MVN R1, #0x35

R1 #0x35. R1 #0xFFFF_FFCA.

2.10: Register to Register Transfer

, CPSR (CoProcessor). CPSR , , bits [23-0] User mode. , CPSR MSR CPSR_f, Rm, _f . Rm CPSR. , R0 0x80000000 : MSR CPSR_f, R0 27

AT91

2.3 -

1 (Negative bit) 0 (bits Z, C, V, Q).

(CoProcessor) . , (Memory Management Unit - MMU), (Protection Unit) .

, SWP . SWP Rd, Rm, [Rb], Rd , Rm Rb , .

2.3.4

/

/ (. 2.3.4, . 29). (hardware) . (software). / Rd, Rn, , Rd , Rn , . , CPSR, . CLZ 0 Rn, 1 Rd (

). / (.2.3.4, . 30). CMP, CMN, TEQ & TST SUB, ADD, EOR, AND . CMP CPSR S . 28

2. ADC AND AND ADD BIC

AT91 AND NOT 2

CLZ CMP ORR RSC SUB TST MUL

0 OR ( - )

CMN EOR RSB SBC TEQ MLA SMLAL

-(2 ) XOR ( - 32bits

SMULL

32bits

-

UMLAL

- 32bits

UMULL

- 32bits

-

2.11:

Rn, , Rn , . , , , . (. 2.3.4, . 31).

, . 32 , 32 64 . 29

AT91 ADD R1, R1, #0x10 SUB R5, R1, R2, LSL #2 RSB R5, R1, R2, LSL #2 ADC R5, R1, R2

2.3 -

R1 0x10. R1 R2*4 R5 R2*4 R1 R5 R1 R2 CPSR R5.

AND R1, R1, #0x10

AND R1 0x10 R1.

2.12: /

32 64 , , 2 . 32 . , 5 x 6, 64 , 32 . 32 32 .

. MUL 2 32 . MLA 2 32 . . 64 . SMULL & SMLAL ( - ), . UMULL & UMLAL - . 64 . (. 2.3.4, . 31) 30

2.

AT91

CMP R2, R4

R2 R4. .

CMP R3, 0x8000

R3 0x8000. .

CMN R1, R2

R1 -R2 ( 2 R2) .

TEQS R1, R4

R1 R4. , CPSR 1.

2.13:

MUL R1, R2, R5

R2 R5 32 bits R1.

MLA R1, R1, R4, R6

R1 R4, R6 32 bits R1.

SMULL R0, R1, R4, R6

R4 R6 32 bits R0 32 bits R1.

UMLAL R1, R2, R4, R6

R4 R6 - , R1 + R2 * 232 32 bits R1 32 bits R2.

2.14:

31

AT91

2.3 -

2.3.5

Branches (. 2.3.5, . 32).

B BX

BL BLX

R15 R14 R15 R14

2.15: Branches , 32MBytes. R15 (PC). , ( . 3.2.1, . 37).

32

Assembly 913.1 . , . , , . :1. 2 2. 1 3. 1

4

, : 1. 2. 3. 0 1 (. 0111100111101111). 12 . , ( 12

,

.

33

AT91

3.1 -

). , 0 1 ( ) . ( ) . , ADD, . , 0 1 (Assembler). (Assembly). (). ARM946EJ-S Intel Pentium 4 80C196KB, . , , . , . , . , C, FORTRAN, BASIC .. , , 13 . , ( , C . C a = b + c;). 13

.

34

3. Assembly 91

AT91

, 14 . , {a = b + c; d = b + c;} compiler C :1. b 2. c 3. . 4. a. 5. b. 6. c. 7. . 8. d.

:1. b. 2. c. 3. . 4. a. 5. d.

, . C , 15 . , . , , . , ( ) , . 14 15

.

35

AT91

3.2 - GNU Assembler

, ( - debuggers) . . , , .

. . . i386 i686 (. Pentium 4 Athlon) , . , , . 486. , . , , , . (drivers) ( ). .

3.2 GNU Assembler 91 GNU Assembler (gas). gas 16 . : [ :] [ @ ] , [ ]. spaces tabs ( space). 16

36

3. Assembly 91

AT91

(. ADD, MUL, ORR ..) gas . gas . , . , . , @ . @ gas . , .

/*. . . */, /* & */ . :

/All this is a big comment MOV R2, R2, LSL #4 ADC R2, R1, #15 . . .

/

3.2.1

, , . . , , ( ), . , . , , . gas . , , gas 37

AT91 . :LOOP:MOV R0, R2 @ R2 > R0 . . . CMP R0, #4 @ R0 == 4 ??? BEQ LOOP @ If(R0 == 4) Goto LOOP

3.2 - GNU Assembler

A. . . Z, a. . . z, 0. . . 9, _ : . :

LOOP: LOOP : _LOOP123bf_DataAREA: @df.#Number926*:

( :) ( )

, . , , LOOP WHILE. , . A3bfd , . , .

3.2.2

gas , . . [params], [params] . (. 3.2.2, . 39)17 .17

gas www.gnu.org

38

3. Assembly 91 .abort .align .arm .asciz .byte .data .equ .global .hword .if .include .text .word .

AT91

. . strings . bytes. . . . halfwords. , . . . words.

3.16:

.abort gas, .

.align .align , , . , ( , words 4). .align , . , , . , .align 6 gas 6 ( 0x8000, 0x8004 3 ). 39

AT91 .arm

3.2 - GNU Assembler

gas 32 bits. . .asciz gas string. .asciz . , lesson string Assembly Cource CPU string AT91SAM9261: lesson: .asciz Assembly Cource CPU: .asciz AT91SAM9261 .byte gas bytes. .byte [,]*, 8 bit . , , , . , ( , , ). , bytes: .byte 0x35, 0x42, 0xaa, 0x68 .byte 0x12, 0x60, 0xba, 0xcd .data gas - 18 . .equ . ( ),18

- ,

40

3. Assembly 91

AT91

(). .equ , , . , .equ FunnyVal, #0x12345678, FunnyVal 0x12345678 FunnyVal . , gas , .

.global .global , . gas , . , . , ( object le). , object les ( ). ( - linking), ( , , ). object . , .

.hword .byte, 16 bit. , .byte :

.hword 0x4235, 0x68aa .byte 0x6012, 0xcdba bytes. , , byte halfword . 41

AT91 .if

3.2 - GNU Assembler

.if .equ. .equ, , gas , . , :.equ DEBUG, 1 . . . .if DEBUG MOV R0, #0x30 .else MOV R0, #0x10 .endif

1 DEBUG .if gas MOV R0, #0x30. , gas MOV R0, #0x10. : .if . . . .else . . . .endif .else , . .endif .if . , ( 0 ).

.include assembly . .include , . , rst.s :.data ByteArray: .word 0xcafebaba, 0xdeadbeef, . . . . . .

42

3. Assembly 91 second.s :.include rst.c . . . LDR R0, =ByteArray @ addr(ByteArray) > R0 . . .

AT91

gas second.s :.data ByteArray: .word 0xcafebaba, 0xdeadbeef, . . . . . . LDR R0, =ByteArray @ addr(ByteArray) > R0 . . .

.text gas , . , :.text . . . LDR R0, =ByteArray @ addr(ByteArray) > R0 . . . .data ByteArray: .byte 0x35, 0xaa, 0x22, . . . . . . .text LDR R1, [R0, #0x01] @ 0xaa > R1 . . .

.word .byte, 32 bit. , .byte :

43

AT91 .word 0x68aa4235 .word 0xcdba6012

3.3 -

3.3 Assembly . Assembly, .

3.3.1

32-bit

32-bit 1 2 3 4 5 6 7 8 9 10 11 12 13 LDR R0, =Result STR R1, [R0] LDMIA R13!, {R0-R12} MOV PC, R14 main: STMDB R13!, {R0-R12} LDR R0, =Value LDR R1, [R0] .arm .text .global main

@ @ R0 Value @ R1 R0 @ R0

@ R1 R0 @

@ main. , , Linux shell.

14 15 .data

@ "Data" ,

16 17 18 19

Value: .word 0xCAFEBABA Result: .word 0

@ 0xCAFEBABA Value

@ Value+4 Result

44

3. Assembly 91

AT91

32 bit Value Result. = Value Result. Stack , . , ( ) main .global, 19 .

3.3.2

32-bit

32-bit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 .data LDR R0, =Result STR R2, [R0] LDMIA R13!, {R0-R2} MOV PC, R14 main: STMDB R13!, {R0-R2} LDR R0, =Values LDR R1, [R0, #0] LDR R2, [R0, #4] ADD R2, R2, R1 .arm .text .global main

@ @ R0 Values

@ R1 R0

@ R1 4 R0

@ R2 R1 R2

@ R0 Result

@ R2 R0

@

@ main

@ "Data" ,

18

Values:

@ Values

19

main GNU .

45

AT91

3.3 -

19 20 21 22

.word 0xFFF00000 .word 0xCDEF Result: .word 0

@ Result

Values (Values+4). . , . , R1. , . , . , 4 bytes 20 . 4 bytes R0. R1, R2 R2. R2 , Result. R0 Result. ( R0 ) R2. Result (Values+8) Result.

3.3.3 1 2 3 4 5 6 720

.arm .text .global main nik main: STMDB R13!, {R0-R12, R14}

@

.

46

3. Assembly 91

AT91

8 9

LDR R12, =Start ADD R12, R12, 0x2C

@ R0 Start

@ 0x2c= 44. R12 12

10 11 12 13 14 15 16 17 18 19 20 21 22 23 LDMIA R13!, {R0-R12, PC} MOV R0, #0xF BL Pop MOV R0, #0xF BL Push MOV R0, #2 BL Pop MOV R0, #4 BL Push

@ 4 R0 @ Push, R0 4 @ 2 R0 @ Pop, R0 2 @ 15 R0 @ Push, R0 15 @ 15 R0 @ Pop, R0 15 @ PC R14, main

24 25 26 /* PUSH */ push:

@ Push.

27 28 29 30 31 32 33 34 35

STMDB R13!, {R4} LDR R4, =Start

@ @ R0 Start

PushLoop: CMP R4, R12 BHI PushOvr STR R0, [R12] SUB R12, R12, #4 SUBS R0, R0, #1

@ PushLoop @ R4 R12, , R4-R12

@ R4 > R12 PushOvr

@ R12 R0

@ 4 R12 @ 1 R0 (, , )

36

BHI PushLoop

@ , PushLoop

37

47

AT91

3.3 - @ PushEnd

38 39 40

B PushEnd PushOvr: MVN R0, #0

@ PushOvr. @ , R0 0xFFFFFFFF

41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 .data PopEnd: LDMIA R13!, {R4,R5} MOV PC, R14 B PopEnd PopUnd: MVN R0, #0 PopLoop: CMP R12, R4 BCS PopUnd ADD R12, R12, #4 LDR R5, [R12] SUBS R0, R0, #1 BHI PopLoop /* POP */ Pop: STMDB R13!, {R4,R5} LDR R4, Start ADD R4, R4, #0x02C PushEnd: LDMIA R13!, {R4} MOV PC, R14

@ PushEnd. @

@ push

@ @ R0 Start

@ R4 4 @ PopLoop @ R12 R4, R12-R4

@ R12 >= R4 PopUnd

@ R12 4 @ R5 , R12

@ 1 R0 @ R0 0 PopLoop

@ PopLoop

@ PopUnd @ R0 0xFFFFFFFF @ PopEnd @

@ pop

@ "Data" ,

48

3. Assembly 91

AT91

69 70 71

Start: .word 0,0,0,0,0,0 .word 0,0,0,0,0,0

@ Start

. , . , Last-In First-Out (LIFO) First-In First-Out (FIFO). LIFO LIFO (. 3.9, . 49). LIFO . , 0x8000, , 0x7FFC .

3.9: LIFO

LIFO, 32bit push, R0 ( 1 . 3 3,2,1). push , stack pointer, R12 . stack pointer 4, words. , R0, 0 . stack pointer, stack pointer . 49

AT91

3.3 -

, stack pointer , . 0x R0, . pop, stack pointer . stack pointer . stack pointer , stack pointer , 0x R0. LIFO. , R13 stack pointer block push & pop. STMDB STMIA ( R13).

3.3.4

8 bit

72 73 74 75 76 77 78 79 80 81 82 83 84 85 LDRB R2, [R0, #2] CMP R2, R1 MOVHI R1, R2 main: STMDB R13!, {R0-R12} LDR R0, =Values LDRB R1, [R0, #0] LDRB R2, [R0, #1] .arm .text .global main

@ @ R0 Values

@ R1 R0

@ R2 R0

@ R2 R1, R2-R1

@ R2 > R1 R1 R2 @ R2 R0

50

3. Assembly 91

AT91

86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102

CMP R2, R1 MOVHI R1, R2 LDRB R2, [R0, #3] CMP R2, R1 MOVHI R1, R2 LDRB R2, [R0, #4] CMP R2, R1 MOVHI R1, R2 LDR R0, =Result STRH R1, [R0] LDMIA R13!, {R0-R12} MOV PC, R14

@ R2 R1, R2-R1

@ R2 > R1 R1 R2 @ R2 3 R0

@ R2 R1, R2-R1

@ R2 > R1 R1 R2 @ R2 4 R0

@ R2 R1, R2-R1

@ R2 > R1 R1 R2 @ R0 Result

@ R1 R0 halfword

@

@ main

.data

@ "Data" ,

103 104 105 106 107

Values: .byte 0x10, 0x15, 0x20 .byte 0x25, 0x30 .align 2

@ Values

@ 2, halfwords

108 109

Result: .hword 0

@ Result

@

5 Result. 4 . , ( , ) 4 . 51

AT91

3.3 -

110 111 112 113 114 115 116 117 118 119 120 121 Loop: LDRB R2, [R0, #1]! main: STMDB R13!, {R0-R12} LDR R0, =Values LDRB R1, [R0, #0] ADD R3, R0, #4 .arm .text .global main

@ @ R0 Values

@ R1 R0

@ R3 4 R0

@ Loop @ R2 R0 R0 1

122 123 124 125 126

CMP R2, R1 MOVHI R1, R2 CMP R0, R3 BLO Loop

@ R2 R1, R2-R1

@ R2 > R1 R1 R2 @ R0 R3, R0-R3

@ Loop

127 128 129 130 131 132 133 .data LDR R0, =Result STRH R1, [R0] LDMIA R13!, {R0-R12} MOV PC, R14

@ R0 Result

@ R1 R0 halfword

@

@ main

@ "Data" ,

134 135 136 137

Values: .byte 0x10, 0x15, 0x20 .byte 0x25, 0x30

@ Values

52

3. Assembly 91

AT91

138

.align 2

@ 2, halfwords

139 140

Result: .hword 0

@ Result

@

folding . , , R0, . , R3 ( , , ). CMP CPSR bits Loop:, Result. , . : . . . , .

3.3.5

64 bit

141 142 143 144 145 146 147 148 main: STMDB R13!, {R0-R12} LDR R0, =Values LDR R1, [R0, #0] .arm .text .global main

@ @ R0 Values

@ R1 R0

53

AT91

3.3 - @ R1 8 R0

149 150

LDR R2, [R0, #8] ADDS R3, R1, R2

@ R1 & R2, R3 ,

151

STR R3, [R0, #0x10]

@ R3 , 16 R0

152 153 154 155 LDR R1, [R0, #4] LDR R2, [R0, #0xC] ADC R3, R1, R2

@ R1 4 R0

@ R1 12 R0

@ R1 & R2 R3

156

STR R3, [R0, #0x14]

@ R3 , 4 Result

157 158 159 160

LDMIA R13!, {R0-R12} MOV PC, R14

@

@ main

.data

@ "Data" ,

161 162 163 164 165 166 167

Values: .word 0x1, 0xFF000000 .word 0xFFFFFFFF .word 0xFFFFFE Result: .word 0,0

@ Values

@ Result

64 bit. 32 bit : 32 bits , . 2 ( ADC) CPSR. bits , .

54

3. Assembly 91

AT91

, CPSR Carry bit 0 ( ). , , . 64 bit , , 128 256 bit , .

3.10: 64 bit addition

. , .

3.3.6

32 bit 16 bit

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 MOV R3, #0 CLZ R6, R2 MOV R2, R2, LSL R6 LDR R1, [R0], #4 LDRH R2, [R0] CMP R2, #0 BEQ Err LDR R0, =Values main: STMDB R13!, {R0-R12} .arm .text .global main

@ @ R0 Values

@ R1 R0 R0 4

@ R1 R0 halfword

@ @ 0, Err

@ 0 R3 @ R6 0 R2

@ R2 , R6. 1

55

AT91

3.3 -

18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 .data LDMIA R13!, {R0-R12} MOV PC, R14 B Done Err: MVN R3, #0 Done: LDR R0, =Result STR R3, [R0], #4 STRH R1, [R0] MOV R2, R2, LSR #1 SUBS R6, R6, #1 BCS Loop Loop: MOV R3, R3, LSL #1 CMP R1, R2 ORRCS R3, R3, #1 SUBCS R1, R1, R2

@ Loop @ R3 1 @ R1 R2, R1-R2

@ R1 >= R2 R3 1

@ R1 >= R2 R2 R1 @ R2 1 @ R6 1 R6

@ R6 0, Loop

@ Done

@ Err @ R3 -1 @ Done @ R0 Result

@ R0 R3 R0 4

@ R0 R1 halfword

@

@ main

@ "Data" ,

41 42 43 44 45 46 47 48

Values: .word 0xFFFFFFFE .hword 0xF .align 4 Result: .word 0 .hword 0

@ Values

@ 4

@ Result

56

3. Assembly 91

AT91

. , , . , , 232 1 ( 232 1 1). :D = x31 * d * 231 + . . . + xi * d * 2i + . . . + r

D , d r . :q = x31 * 231 + . . . + xi * 2i + . . . + x0

D = xi * d * 2i , . 21 , 0, . . , 0xFE 3, 0xC0. 0xC0 0xFE, . x5 * d *

25 , x5 = 1. , ( ) x4 * d * 24 , . , , ( , ) . 2 , bit (. 5 5 bit ). bit . , , 1. , bit ( 0). , bit 5 , 4 .21

, , 1 31

57

AT91

3.3 -

58

, , .

4.1 91 , ATMEL. AT91SAM9261, ( , USB, Ethernet, ...) .

4.2 91, Linux (Snapgear distribution), 2.6.20. Linux ARM926EJ-S, , (LCD , USB , Flash ). (login) root support, . , shell , Linux. shell . Linux (. 4.2, . 60). 59

AT91Cmd as cat df ld make mount nm rm gas GNU Linker GNU Cmd cd cp kill ls mkdir mv ps

4.2 -

umount

4.24: Linux

cat cat . : cat < f ilename > < f ilename > . , cat /etc/motd .

cd cd . : cd < destination > < destination > . , cd .. , .

cp cp , . : cp < f ilename > < destination > < f ilename > < destination > . , cp /etc/motd /storage /etc/motd /storage. 60

4. df

AT91

df (le system). .

kill kill (software signals) . : kill -< signum > < pid > < signum > < pid > . , kill -9 38 9 38 ( 9 ).

ls ls . : ls [-alF] -alF .

make make Assembly . script , . : make < srcf ile > < destf ile > < srcf ile > < destf ile > . , make foo.S bar foo.S, bar.o (object ) bar. 61

AT91 mkdir

4.2 -

mkdir . : mkdir < f older > < f older > . , mkdir exer1 exer1 .

mount mount , USB stick . : mount < device > < f older > < device > < f older > , . , mount /dev/sda0 /mnt USB stick mnt. cd ls stick.

mv mv , . : mv < f ilename > < destination > < f ilename > < destination > . , mv /etc/motd /storage /etc/motd /storage . , (. mv /etc/motd /etc/hello.txt).

ps ps . . 62

4. rm

AT91

rm . : rm [-r] < f ilename > -r ( ) < f ilename > / (. rm ask1.s ask1.s). umount umount , USB stick. . : umount < f older > < f older > , . , umount /mnt USB stick mnt.

4.3 GNU tools Assembler, Linker, Debugger InfoViewer. make, Debugger gdb InfoViewer nm. Debugger 22 . gdb < executable >, < executable > . Debugger , . (breakpoints) (watchpoints), . Debugger, 22

91 shell,

(MMU) . . .

63

AT91 gdb < f ile >

4.3 - GNU tools

< f ile > . , Debugger, . run. Debugger . Debugger breakpoint . , , . breakpoints break. Breakpoints (. 4.3, . 64).Breakpoint break break break breakpoint . breakpoint . breakpoint .

4.25: , break main breakpoint , run . , 0x80c0 breakpoint , break *0x80c0. 15 , break 15. , breakpoint 3 (. main), break *(main+12), 12 12 bytes , 4 bytes. breakpoints , info break [n] , breakpoints23 . n, n breakpoint (. info break 3 breakpoint). breakpoint 23

, breakpoint , ,

...

64

4.

AT91

clear , line breakpoint

(. clear 12 breakpoint 12). breakpoint delete , breaknum breakpoint (. delete 2 2 breakpoint). x/nfu < address >, n , f

u . :x d u - o t a c ASCII s string

. :b 1 byte h 2 bytes (halfword) 2. w 4 bytes (word) 4. g 8 bytes (giantword) 8.

address (. x/wx 0x10544), (. x/wx (&Values + 2)). (. 4.3, . 68), . p/f < variable >,

(casting). word, . , p/x Values 65

AT91

4.3 - GNU tools

0x40302010. byte, p/x*((char*)&Values+2).

, p/f $< register >. , p/x $r0 R0, p/x $pc

R15 p/t $cpsr CPSR. info registers, . Debugger , set < expr >, expr , set Values = 0x450 Values 0x450. set $r0 = 0xFF, R0 255. , casting , set *((char*)&Values+2) = 0x45, byte 2 , 0x45. , ( ) ( breakpoint). , , continue c, step. , step , . next n, step, ( ). Debugger , list [] [,] , 10 , 10 2 . , list 15 10. . . 19, list 15,18 15. . . 18. disassemble [] 66

4.

AT91

[] ,

. , 10 . 10 2 . , disassemble (main+20) main main+40 ( 4 bytes). disassemble (main+8) (main+16) 3 . disassemble , .

, , . . gdb , . , , , . , , disassemble.

67

AT91

4.3 - GNU tools

.data :Values: .word 0x40302010, 0x80706050 .word 0x54204948, 0x45524548

x/2xw &Values x/3xb ((char*)&Values+1)

0x40302010 & 0x80706050 0x20, 0x30, 0x40. casting (char*) Debugger bytes b 1 byte . (char*) 0x50, 0x60, 0x70, 1 word Values byte, .

x/2xh ((short*)&Values+1)

0x4030, 0x6050. casting (short*) Debugger halfwords h 2 bytes . (short*) 0x6050, 0x8070, 1 word Values halfword, .

x/dh &Values

8208 ( halfword 0x2010). casting .

x/dh ((short*)&Values+3) x/uh ((short*)&Values+3) x/s &Values+2

-32656 ( ). 32880 (- ). string HI THERE.

4.27:

68

5.1 91 ( KEIL) ARM . , , . Microsoft Windows XP / Vista . . , . 91, . ( GNU Microsoft Windows XP / Vista ) , 91 .

5.2 , GNU ( C:Cygnus ). , Project menu Project New Project... . / 69

AT91

5.2 -

. Atmel AT91SAM9261( , . 5.11, . 70). project , .

5.11:

5.12: , menu File New..., . project , 70

5.

AT91

Save As... menu File , .s .c C ( , exer1.s, ask2.c ). , Project workspace Target 1 Source Group 1 Add Files to Group Source Group 1 ( , . 5.12, . 70). , Add, Project24. Close.

5.13: . GNU. GNU , manage Project menu Components, Environment, Books. Folders/Extensions tab ( , . 5.13, . 71). Use24

Assembly les of type: Asm source le(*.s; *.src; *.a*),

.

71

AT91

5.3 -

GNU compiler (GNU-Tool-Prex) arm-uclibc- (Cygnus Folder) GNU tools ( c:/cygnus ). Assembler. Project menu Options for Target. Assembler tab Misc Controls -mcpu=arm926ej. , .

5.3 Build target Project menu. . GNU assembler. error, ( , . 5.14, . 72).

5.14: , GNU assembler (. , ). , Start/Stop debug session Debug menu. ( ) PC. PC (R15) ( , ) F2.

72

5.

AT91

0x8000, PC 0x8000. ( , . 5.15, . 73).

5.15: Step Debug menu PC 4 . Step Over Debug menu Step, ( , ). , . Project . Sample1.s Project.Stack 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 .data Values: .word 0x10, 0xFFFFFFFF LDMIA R13!, {R0-R2, PC} LDR R1, =Values LDR R2, [R1,#0] MOV R2, R2, LSL #0x02 STR R2, [R1, #4] main: STMDB R13!, {R0-R2, R14} .arm .text .global main

Build target Project menu , 73

AT91

5.3 -

0 0 , linker start 0x8000. 1 , : R0=0xAA, R1=0xBB, R2=0xCC, R13 = 0x301000, R14 = 0x7777 R15=0x8000. 1 , . . R14 R2 - R0 . 0x301000. . Memory Window menu View 0x300FD0 Address. 1 . , , Values R1, R2, 4 . , 0x8000. 9. Values R1 0x8120. 3 Memory Window Address ( , . 5.16, . 74).

5.16: - 2 words . , 74

5.

AT91

13, 0x8124 0x00000040. , , Modify Memory. , ( byte, int ) pop-up menu Memory window, Unsigned, signed, decimal . 0x8120 PC 1 ( 0x8000) . .

75

AT91

5.3 -

76

Instruction Set . , , .

77

AT91

6.1 -

6.1 6.1.1 ADC31 28 27 26 00 25 24 23 22 21 0 1 0 1 20 S 19 16 15 12 11 0 cond Rn Rd Shifter operand

ADC (Add with Carry) Carry bit Rn. Rd. , . ADC{}{S} < Rd >, < Rn >, < shif ter _operand >

{} {S}

. , . . : Rd R15, N & Z C & V ( ) . . Rd R15, SPSR processor mode CPSR. User System mode , modes SPSR. -

< Rd > < Rn > < shif ter _operand > {cond}

. . ( . 2.3.2, . 2.3.2).

Rd = Rn + shifter_operand + C_ag S == 1 Rd == 15 CPSR = SPSR S == 1 N_ag = Rd[31] Z_ag = ( Rd == 0 1 0) C_ag = ( ) V_ag = ( ) 32 bits. , : ADDS R4, R0, R2 @R0 + R2 > R4 ADC R5, R1, R3 @R1 + R3 + Carry > R5 64bit R0 + R1 * 232 R2 + R3 * 232 . 32 bits, .

78

6.Instruction Set

AT91

6.1.2

ADD31 28 27 26 00 25 24 23 22 21 0 1 0 0 20 S 19 16 15 12 11 0 cond Rn Rd Shifter operand

ADD Rn Rd. , . ADD{}{S} < Rd >, < Rn >, < shif ter _operand >

{} {S}

. , . . : Rd R15, N & Z C & V ( ) . . Rd R15, SPSR processor mode CPSR. User System mode , modes SPSR. -


. . ( . 2.3.2, . 2.3.2).

Rd = Rn + shifter_operand S == 1 Rd == 15 CPSR = SPSR S == 1 N_ag = Rd[31] Z_ag = ( Rd == 0 1 0) C_ag = ( ) V_ag = ( ) 32 bits.

79

AT91

6.1 -

6.1.3

AND31 28 27 26 00 25 24 23 22 21 0 0 0 0 20 S 19 16 15 12 11 0 cond Rn Rd Shifter operand

AND Rn Rd. , . AND{}{S} < Rd >, < Rn >, < shif ter _operand >

{} {S}

. , . CPSR . : Rd R15, & C . . Rd R15, SPSR processor mode CPSR. User System mode , modes SPSR.

< Rd > < Rn > < shif ter _operand >

. . ( . 2.3.2, . 2.3.2).

{cond} Rd = Rn AND shifter_operand S == 1 Rd == 15 CPSR = SPSR S == 1 N_ag = Rd[31] Z_ag = ( Rd == 0 1 0) C_ag = (Bit ( ), 0) V_ag = () AND . , : MOV R4, #0x82 @#0x82 > R4 AND R5, R5, R4 @R5 AND R4 > R5 bits 7 1 ( bits 0, ) 125 .25

AND 1, .

80

6.Instruction Set

AT91

6.1.4

BIC31 28 27 26 00 25 24 23 22 21 1 1 1 0 20 S 19 16 15 12 11 0 cond Rn Rd Shifter operand

BIC (Bit Clear) AND Rn Rd. , . BIC{}{S} < Rd >, < Rn >, < shif ter _operand >

{} {S}

. , . . : Rd R15, & C . . Rd R15, SPSR processor mode CPSR. User System mode , modes SPSR.


. . ( . 2.3.2, . 2.3.2).

{cond} Rd = Rn AND NOT shifter_operand S == 1 Rd == 15 CPSR = SPSR S == 1 N_ag = Rd[31] Z_ag = ( Rd == 0 1 0) C_ag = (Bit ( ), 0) V_ag = () 0 . , : BIC R5, R5, #0x44 @R5 AND NOT #0x44 > R5 bits 6 2 R5.

81

AT91

6.1 -

6.1.5

CLZ31 28 27 26 25 24 23 22 21 20 0 0 0 1 0 1 1 0 19 16 15 12 11 8 7654 0001 3 0 Rm cond 0000 Rd 0000

CLZ (Count Leading Zeros) 0, Rm. Rd. CLZ{} < Rd >, < Rm >

{} < Rd > < Rm >

. , . . , 0.

{cond} Rm == 0 Rd = 32 Rd = 31 - #(bit position of most signicant 1) , 1 31, . . : CLZ R5, R4 @ leading_zeros(R4) > R5 MOV R4, R4, LSL R5 @ R4 * 2R5 > R4 R4 0x49, R5 25 ( 0x49 00000000_00000000_00000000_01001001) 0x92000000.

82

6.Instruction Set

AT91

6.1.6

CMN31 28 27 26 00 25 24 23 22 21 1 0 1 1 20 1 19 16 15 12 11 0 cond Rn 0000 Shifter operand

CMN (Compare Negative) Rn ( 2) . , ( ). CMN{} < Rn >, < shif ter _operand >

{} < Rn > < shif ter _operand > {cond}

. , . . ( . 2.3.2, . 2.3.2).

alu_out = Rn + shifter_operand N_ag = alu_out[31] Z_ag = ( alu_out == 0 1 0) C_ag = ( ) V_ag = ( ) ( , ), .

83

AT91

6.1 -

6.1.7

CMP31 28 27 26 00 25 24 23 22 21 1 0 1 0 20 1 19 16 15 12 11 0 cond Rn 0000 Shifter operand

CMP (Compare) Rn . , ( ). CMP{} < Rn >, < shif ter _operand >


. , . . ( . 2.3.2, . 2.3.2).

alu_out = Rn - shifter_operand N_ag = alu_out[31] Z_ag = ( alu_out == 0 1 0) C_ag = (NOT ) V_ag = ( )

84

6.Instruction Set

AT91

6.1.8

EOR31 28 27 26 00 25 24 23 22 21 0 0 0 1 20 S 19 16 15 12 11 0 cond Rn Rd Shifter operand

EOR - Rn Rd. , . EOR{}{S} < Rd >, < Rn >, < shif ter _operand >

{} {S}

. , . . : Rd R15, & C . . Rd R15, SPSR processor mode CPSR. User System mode , modes SPSR.


. . ( . 2.3.2, . 2.3.2).

{cond} Rd = Rn OR shifter_operand S == 1 Rd == 15 CPSR = SPSR S == 1 N_ag = Rd[31] Z_ag = ( Rd == 0 1 0) C_ag = (Bit ( ), 0) V_ag = () EOR . : MOV R4, #0xC0 @#0xC0 > R4 EOR R5, R5, R4 @R5 XOR R4 > R5 7 6 ( 0, ) R526 .26

EOR 2 0,

bit. 1, .

85

AT91

6.1 -

6.1.9

MLA31 28 27 26 25 24 23 22 21 0 0 0 0 0 0 1 20 S 19 16 15 12 11 Rs 8 7654 1001 3 0 cond Rd Rn Rm

MLA (MuLtiply and Accumulate) 32 , , Rd. , . MLA{}{S} < Rd >, < Rm >, < Rs >, < Rn >

{} {S} < Rd > < Rm > < Rs > < Rn >

. , . . & . . . . .

{cond} Rd = (Rm * Rs) + Rn S == 1 N_ag = Rd[31] Z_ag = ( Rd == 0 1 0) C_ag = () V_ag = () R15 Rd & Rm R15 < Rd >, < Rm >, < Rs >, < Rn > . < Rd > & < Rm > . MLA 32 64 , .

86

6.Instruction Set

AT91

6.1.1031

MUL28 27 26 25 24 23 22 21 0 0 0 0 0 0 0 20 S 19 16 15 12 11 Rs 8 7654 1001 3 0 cond Rd 0000 Rm

MUL (MULtiply) 32 Rd. , . MUL{}{S} < Rd >, < Rm >, < Rs >

{} {S} < Rd > < Rm > < Rs >

. , . . & . . . .

{cond} Rd = (Rm * Rs) S == 1 N_ag = Rd[31] Z_ag = ( Rd == 0 1 0) C_ag = () V_ag = () R15 Rd & Rm R15 < Rd >, < Rm >, < Rs > . < Rd > & < Rm > . MUL 32 64 , .

87

AT91

6.1 -

6.1.11

ORR31 28 27 26 00 25 24 23 22 21 1 1 0 0 20 S 19 16 15 12 11 0 cond Rn Rd Shifter operand

ORR Rn Rd. , . ORR{}{S} < Rd >, < Rn >, < shif ter _operand >

{} {S}

. , . . : Rd R15, bits N & Z C . Rd R15, SPSR processor mode CPSR. User System mode , modes SPSR.


. . ( . 2.3.2, . 2.3.2).

{cond} Rd = Rn OR shifter_operand S == 1 Rd == 15 CPSR = SPSR S == 1 N_ag = Rd[31] Z_ag = ( Rd == 0 1 0) C_ag = (Bit ( ), 0) V_ag = () ORR . , : MOV R4, #0xC0 @#0xC0 > R4 ORR R5, R5, R4 @R5 ORR R4 > R5 ( 1) 7 6 ( bits 0, ) R5.

88

6.Instruction Set

AT91

6.1.12

RSB31 28 27 26 00 25 24 23 22 21 0 0 1 1 20 S 19 16 15 12 11 0 cond Rn Rd Shifter operand

RSB (Reverse SuBtract) Rn Rd. , . RSB{}{S} < Rd >, < Rn >, < shif ter _operand >

{} {S}

. , . . : Rd R15, & C & V ( - ) . . Rd R15, SPSR processor mode CPSR. User System mode , modes SPSR.


. . ( . 2.3.2, . 2.3.2).

Rd = shifter_operand - Rn S == 1 Rd == 15 CPSR = SPSR S == 1 N_ag = Rd[31] Z_ag = ( Rd == 0 1 0) C_ag = ( ) V_ag = ( ) , 2 : RSB R4, R4, #0 @ -R4 > R4 (2n 1) Rn : RSB R4, R4, R4, LSL #8 @ (28 R4) R4 > R4

89

AT91

6.1 -

6.1.13

RSC31 28 27 26 00 25 24 23 22 21 0 1 1 1 20 S 19 16 15 12 11 0 cond Rn Rd Shifter operand

RSC (Reverse Subtract with Carry) (Rn + CPSR C bit) Rd. , . RSC{}{S} < Rd >, < Rn >, < shif ter _operand >

{} {S}

. , . . : Rd R15, & C & V ( - ) . . Rd R15, SPSR processor mode CPSR. User System mode , modes SPSR.


. . ( . 2.3.2, . 2.3.2).

{cond} Rd = shifter_operand - Rn - NOT(CPSR C bit S == 1 Rd == 15 CPSR = SPSR S == 1 N_ag = Rd[31] Z_ag = ( Rd == 0 1 0) C_ag = ( ) V_ag = ( ) 2 64 , R0 & R1, word R0, : RSBS R2, R0, #0 @ -R0 > R2 RSC R3, R1, #0 @ -R1 > R3

90

6.Instruction Set

AT91

( S), C : 1 0

, C (carry). . , SBC & RSC C (carry), 1 0 ( #( ) -1). HS & LO CS & CC .

91

AT91

6.1 -

6.1.14

SBC31 28 27 26 00 25 24 23 22 21 0 1 1 0 20 S 19 16 15 12 11 0 cond Rn Rd Shifter operand

SBC (SuBtract with Carry) [Rn + ( C] Rd. , . SBC{}{S} < Rd >, < Rn >, < shif ter _operand >

{} {S}

. , . . : Rd R15, N & Z C & V ( - ) . . Rd R15, SPSR processor mode CPSR. User System mode , modes SPSR.


. . ( . 2.3.2, . 2.3.2).

Rd = Rn - shifter_operand - NOT(CPSR C bit S == 1 Rd == 15 CPSR = SPSR S == 1 N_ag = Rd[31] Z_ag = ( Rd == 0 1 0) C_ag = ( ) V_ag = ( ) 32 . , R0 & R1 R2 & R3, : SUBS R2, R2, R0 @ R2 - R0 > R2 SBC R3, R3, R1 @ R3 - R1 > R3 ( S), C :

92

6.Instruction Set

AT91

1 0


93

AT91

6.1 -

6.1.1531

SMLAL28 27 26 25 24 23 22 21 0 0 0 0 1 1 1 20 S 19 16 15 12 11 Rs 8 7654 1001 3 0 cond RdHi RdLo Rm

SMLAL (Signed Multiply and Accumulate Long operands) 64 , 64 32 RdHi 32 RdLo. RdHi RdLo. SMLAL{}{S} < RdLo >, < RdHi >, < Rm >, < Rs >

{} {S}

. , . . & .

< RdLo > < RdHi > < Rm > < Rs >

word word . word word . . .

{cond} RdLo = (Rm * Rs)[31:0] + RdLo RdHi = (Rm * Rs)[63:32] + RdHi S == 1 N_ag = RdHi[31] Z_ag = ( RdHi == 0 RdLo == 0 1 0) C_ag = () V_ag = () R15 RdHi, RdLo & Rm R15 < RdHi >, < RdLo >, < Rm >, < Rs > . , .

94

6.Instruction Set

AT91

6.1.1631

SMULL28 27 26 25 24 23 22 21 0 0 0 0 1 1 0 20 S 19 16 15 12 11 Rs 8 7654 1001 3 0 Rm cond RdHi RdLo

SMULL (Signed MULtiply Long operands) 64 . RdHi RdLo. SMULL{}{S} < RdLo >, < RdHi >, < Rm >, < Rs >

{} {S}

. , . . & .

< RdLo > < RdHi > < Rm > < Rs >

word . word . . .

{cond} RdLo = (Rm * Rs)[31:0] RdHi = (Rm * Rs)[63:32] S == 1 N_ag = RdHi[31] Z_ag = ( RdHi == 0 RdLo == 0 1 0) C_ag = () V_ag = () R15 RdHi, RdLo & Rm R15 < RdHi >, < RdLo >, < Rm >, < Rs > . , .

95

AT91

6.1 -

6.1.17

SUB31 28 27 26 00 25 24 23 22 21 0 0 1 0 20 S 19 16 15 12 11 0 cond Rn Rd Shifter operand

SUB (SUBtract) Rn Rd. , . SUB{}{S} < Rd >, < Rn >, < shif ter _operand >

{} {S}

. , . . : Rd R15, N & Z C & V ( - ) . . Rd R15, SPSR processor mode CPSR. User System mode , modes SPSR.


. . ( . 2.3.2, . 2.3.2).

Rd = Rn - shifter_operand S == 1 Rd == 15 CPSR = SPSR S == 1 N_ag = Rd[31] Z_ag = ( Rd == 0 1 0) C_ag = ( ) V_ag = ( ) , CMP, SUBS . ( S), C : 1 0

96

6.Instruction Set

AT91


97

AT91

6.1 -

6.1.18

TEQ31 28 27 26 00 25 24 23 22 21 1 0 0 1 20 1 19 16 15 12 11 0 cond Rn 0000 Shifter operand

TEQ (Test EQuivalence) Rn . , . EOR. TEQ{} < Rn >, < shif ter _operand >


. , . . ( . 2.3.2, . 2.3.2).

alu_out = Rn EOR shifter_operand N_ag = alu_out[31] Z_ag = ( alu_out == 0 1 0) C_ag = (Bit ( ), 0) V_ag = () , V, CMP.

98

6.Instruction Set

AT91

6.1.19

TST31 28 27 26 00 25 24 23 22 21 1 0 0 0 20 1 19 16 15 12 11 0 cond Rn 0000 Shifter operand

TST (TeST) Rn . , . AND. TST{} < Rn >, < shif ter _operand >


. , . . ( . 2.3.2, . 2.3.2).

alu_out = Rn AND shifter_operand N_ag = alu_out[31] Z_ag = ( alu_out == 0 1 0) C_ag = (Bit ( ), 0) V_ag = () Rn .

99

AT91

6.1 -

6.1.2031

UMLAL28 27 26 25 24 23 22 21 0 0 0 0 1 0 1 20 S 19 16 15 12 11 Rs 8 7654 1001 3 0 cond RdHi RdLo Rm

UMLAL (Unsigned MuLtiply and Accumulate Long operands) - 64 , RdHi RdLo. RdHi RdLo. UMLAL{}{S} < RdLo >, < RdHi >, < Rm >, < Rs >

{} {S}

. , . . & .

< RdLo > < RdHi > < Rm > < Rs >

word word . word word . . .

{cond} RdLo = (Rm * Rs)[31:0] + RdLo RdHi = (Rm * Rs)[63:32] + RdHi S == 1 N_ag = RdHi[31] Z_ag = ( RdHi == 0 RdLo == 0 1 0) C_ag = () V_ag = () R15 RdHi, RdLo & Rm R15 < RdHi >, < RdLo >, < Rm >, < Rs > . , .

100

6.Instruction Set

AT91

6.1.2131

UMULL28 27 26 25 24 23 22 21 0 0 0 0 1 0 0 20 S 19 16 15 12 11 Rs 8 7654 1001 3 0 Rm cond RdHi RdLo

UMULL (Unsigned MULtiply Long operands) - 64 . RdHi RdLo. UMULL{}{S} < RdLo >, < RdHi >, < Rm >, < Rs >

{} {S} < RdLo > < RdHi > < Rm > < Rs >

. , . , . & , . word . word . . .

{cond} RdLo = (Rm * Rs)[31:0] RdHi = (Rm * Rs)[63:32] S == 1 N_ag = RdHi[31] Z_ag = ( RdHi == 0 RdLo == 0 1 0) C_ag = () V_ag = () R15 RdHi, RdLo & Rm R15 < RdHi >, < RdLo >, < Rm >, < Rs > . , .

101

AT91

6.2 -

6.2 6.2.1 LDM31 28 27 26 25 100 24 P 23 U 22 0 21 W 20 1 19 16 15 Register_list 0 cond Rn

LDM (LoaD Multiple) block . LDM{} < addressing _mode >< Rn > {!}, < registers >

{} {} < Rn >

. , . ( . 2.3.3, . 20). . R15 .

{!} < registers >

, Rn . , Rn . , { }. ( R0 R15) , . 0. . . 15 , .

{cond} address = start_address for i = 0 to 14 register_list[i] == 1 Ri = Memory[address,4] address = address + 4 register_list[15] == 1 value = Memory[address,4] pc = value AND 0xFFFFFFFE address = address + 4 Unaligned Rn , . Rd 4, Data Abord.

102

6.Instruction Set

AT91

6.2.2

LDR31 28 27 26 01 25 24 P 23 U 22 0 21 W 20 1 19 16 15 12 11 0 cond Rn Rd addr_mode

LDR (LoaD Register) 32 . addr_mode Rd. (aligned) 4, 8 * [1:0] ( 3, 24 ). Little Endian , byte word . Rd R15, word, program counter . LDR{} < Rd >, < addressing _mode >

{} < Rd > < addressing _mode >

. , . word . ( . 2.3.3, . 20).

{cond} address[1:0] == 2b00 value = Memory[address,4] address[1:0] == 2b01 value = Memory[address,4] Rotate_right 8 address[1:0] == 2b10 value = Memory[address,4] Rotate_right 16 address[1:0] == 2b11 value = Memory[address,4] Rotate_right 24 Rd is R15 pc = value AND 0xFFFFFFFE Rd = value R15 , (positionindependent) , , . , 85 bytes , PC 85 . , , .

103

AT91

6.2 -

< addressing _mode > Rd & Rn, Rd . Unaligned Rd 4, Data Abord.

104

6.Instruction Set

AT91

6.2.3

LDRB31 28 27 26 01 25 24 P 23 U 22 1 21 W 20 1 19 16 15 12 11 0 cond Rn Rd addr_mode

LDRB (LoaD Register with Byte) 8 , 32 24 0 . LDR{}B < Rd >, < addressing _mode >


. , . . ( . 2.3.3, . 20).

{cond} Rd = Memory[address, 1] < addressing _mode > Rd & Rn, Rd .

105

AT91

6.2 -

6.2.431 28 cond

LDRH27 26 25 000 24 P 23 U 22 21 W 20 1 19 16 15 12 11 8 7654 1011 3 0 addr_mode Rn Rd addr_mode

LDRH (LoaD Register with Halfword) 16 , 32 16 0 . LDR{}H < Rd >, < addressing _mode >


. , . . ( . 2.3.3, . 20).

{cond} address[0] == 0 data = Memory[address, 2] data = UNPREDICTABLE Rd = data < addressing _mode > Rd & Rn, Rd . Unaligned 2, Data Abort.

106

6.Instruction Set

AT91

6.2.531 28 cond

LDRSB27 26 25 000 24 P 23 U 22 21 W 20 1 19 16 15 12 Rd 11 8 7654 1101 3 0 addr_mode Rn addr_mode

LDRSB (LoaD Register with Signed Byte) 8 , 32 24 . LDR{}SB < Rd >, < addressing _mode >


. , . . ( . 2.3.3, . 20).

{cond} data = Memory[address, 1] Rd = SignExtend(data) < addressing _mode > Rd & Rn, Rd .

107

AT91

6.2 -

6.2.631 28 cond

LDRSH27 26 25 000 24 P 23 U 22 21 W 20 1 19 16 15 12 11 8 7654 1111 3 0 Rn Rd addr_mode addr_mode

LDRSH (LoaD Register with Signed Halfword) 16 , 32 16 . LDR{}SH < Rd >, < addressing _mode >


. , . . ( . 2.3.3, . 20).

{cond} address[0] == 0 data = Memory[address, 2] data = UNPREDICTABLE Rd = SignExtend(data) < addressing _mode > Rd & Rn, Rd . Unaligned 2, Data Abort.

108

6.Instruction Set

AT91

6.2.731 28 cond

MCR27 26 25 24 1110 23 21 20 0 19 16 15 12 11 8 7 5 4 1 3 0 opcode_1 CRn Rd cp_num opcode_2 CRm

MCR (Move to Coprocessor from Register) Rd, cpu_num. , Undened Instruction. MCR{} < coproc >, < opcod_1 >, < Rd >, < CRn >, < CRm > {, < opcod_2 >}

{} < coproc > < opcod_1 > < Rd >

. , . cp_num . p0 p15. . , . R15, .

< CRn > < CRm > < opcod_2 >

. . . , 0.

{cond} Send Rd to Coprocessor[cpu_num]

109

AT91

6.2 -

6.2.8

MOV31 28 27 26 00 25 24 23 22 21 1101 20 S 19 16 15 12 11 0 cond 0000 Rd Shift_operand

MOV (move) Rd. , . MOV{}{S} < Rd >, < shif ter _operand >

{} {S}

. , . , . : Rd R15, & C . . Rd R15, SPSR processor mode CPSR. User System mode , modes SPSR.

< Rd > < shif ter _operand > {cond}

. ( . 2.3.2, . 15).

Rd = shifter_operand S == 1 Rd == 15 CPSR = SPSR S == 1 N_ag = Rd[31] Z_ag = ( Rd == 0 1 0) C_ag = (Bit ( ), 0) V_ag = () , , Rd R15.

110

6.Instruction Set

AT91

6.2.931 28 cond

MRC27 26 25 24 1110 23 21 20 1 19 16 15 12 11 8 7 5 4 1 3 0 opcode_1 CRn Rd cp_num opcode_2 CRm

MRC (Move to Register from Coprocessor) cpu_num Rd. , Undened Instruction. MRC{} < coproc >, < opcod_1 >, < Rd >, < CRn >, < CRm > {, < opcod_2 >}

{} < coproc > < opcod_1 > < Rd >

. , . cp_num . p0 p15. . , . R15, .

< CRn > < CRm > < opcod_2 >

. . . , 0.

{cond} data = value from Coprocessor[cpu_num] Rd is R15 N_ag = data[31] Z_ag = data[30] C_ag = data[29] V_ag = data[27] Rd = data

111

AT91

6.2 -

6.2.1031

MRS28 27 26 25 24 23 00010 22 R 21 20 00 19 16 15 12 11 0 0000 Rd 000000000000

cond

MRS (Move PSR to Register) CPSR SPSR Rd. MRS{} < Rd >, CP SR MRS{} < Rd >, SP SR

{} < Rd >

. , . , PSR.

{cond} R == 1 Rd = SPSR Rd = CPSR

112

6.Instruction Set

AT91

6.2.11

MSR22 R 21 20 10 19 16 15 12 11 8 7 0

Immediate operand: 31 28 27 26 25 24 23 cond 00110

eld_mask

1111

rotate_imm

8_bit_immediate

Register operand: 31 28 27 26 25 24 23 00010 22 R 21 20 10 19 16 15 12 11 8 7654 0000 3 0 Rm cond eld_mask 1111 0000

MSR (Move to xPSR) ( Rd) CPSR SPSR. MSR{}CP SR_ < f ields >, # < immediate > MSR{}CP SR_ < f ields >, < Rm > MSR{}SP SR_ < f ields >, # < immediate > MSR{}SP SR_ < f ields >, < Rm >

{} < f ields >

. , . : c 16 (control). x 17 (extension). s 18 (status). f 19 (ags).

< immediate >

CPSR SPSR. 8 8 ( 0 31 ).

< Rm >

, CPSR SPSR.

{cond} opcode[25] == 1 operand = 8_bit_immediate ROR (rotate_imm*2) operand = Rm R == 0 eld[0] == 1 AND PrivilegedMode CPSR[23:0] = operand[23:0] eld[1] == 1 AND PrivilegedMode CPSR[15:8] = operand[15:8] eld[2] == 1 AND PrivilegedMode CPSR[23:16] = operand[23:16] eld[3] == 1

113

AT91

6.2 -

CPSR[31:24] = operand[31:24] eld[0] == 1 AND HasSPSR SPSR[23:0] = operand[23:0] eld[1] == 1 AND HasSPSR SPSR[15:8] = operand[15:8] eld[2] == 1 AND HasSPSR SPSR[23:16] = operand[23:16] eld[3] == 1 AND HasSPSR SPSR[31:24] = operand[31:24]

114

6.Instruction Set

AT91

6.2.12

MVN31 28 27 26 00 25 24 23 22 21 1111 20 S 19 16 15 12 11 0 cond 0000 Rd Shift_operand

MVN (MoVe Negative) 1 Rd. , . MVN{}{S} < Rd >, < shif ter _operand >

{} {S}

. , . , . : Rd R15, & C . . Rd R15, SPSR processor mode CPSR. User System mode , modes SPSR.

< Rd > < shif ter _operand > {cond}

. ( . 2.3.2, . 15).

Rd = NOT shifter_operand S == 1 Rd == 15 CPSR = SPSR S == 1 N_ag = Rd[31] Z_ag = ( Rd == 0 1 0) C_ag = (Bit ( ), 0) V_ag = () 1 .

115

AT91

6.2 -

6.2.13

STM31 28 27 26 25 100 24 P 23 U 22 0 21 W 20 0 19 16 15 Register_list 0 cond Rn

STM (STore Multiple) block . STM{} < addressing _mode >< Rn > {!}, < registers >

{} {} < Rn >

. , . ( . 2.3.3, . 20). . R15 .

{!} < registers >

, Rn . , Rn . , { }. ( R0 R15) , . 0. . . 15 , .

{cond} address = start_address for i = 0 to 14 register_list[i] == 1 Memory[address,4] = Ri address = address + 4 Unaligned Rn , . Rd 4, Data Abord.

116

6.Instruction Set

AT91

6.2.1431

STR28 27 26 01 25 24 P 23 U 22 0 21 W 20 1 19 16 15 12 11 0 cond Rn Rd addr_mode

STR (STore Register) (32 ) . addr_mode Rd. STR{} < Rd >, < addressing _mode >


. , . . ( . 2.3.3, . 20).

{cond} Memory[address,4] = Rd R15 , position-independent , , . , 85 bytes , pc 85 . , , . < addressing _mode > Rd & Rn, Rd . Unaligned Rd 4, Data Abord.

117

AT91

6.2 -

6.2.1531

STRB28 27 26 01 25 24 P 23 U 22 1 21 W 20 0 19 16 15 12 11 0 cond Rn Rd addr_mode

STRB (STore Register Byte) 8 . STR{}B < Rd >, < addressing _mode >


. , . . ( . 2.3.3, . 20).

{cond} Memory[address, 1] = Rd[7:0] < addressing _mode > Rd & Rn, Rd .

118

6.Instruction Set

AT91

6.2.1631 28 cond

STRH27 26 25 000 24 P 23 U 22 21 W 20 0 19 16 15 12 Rd 11 8 7654 1011 3 0 addr_mode Rn addr_mode

STRH (STore Register Halfword) 16 . STRH{}H < Rd >, < addressing _mode >


. , . . ( . 2.3.3, . 20).

{cond} address[0] == 0 data = Rd[15:0] data = UNPREDICTABLE Memory[address,2] = data < addressing _mode > Rd & Rn, Rd . Unaligned 2, Data Abort.

119

AT91

6.2 -

6.2.17

SWP31 28 27 26 25 24 23 22 21 20 00010000 19 16 15 12 11 8 7654 1001 3 0 cond Rn Rd 0000 Rm

SWP (SWaP) . Rm Rn Rd. Rn & Rm, . SWP{} < Rd >, < Rm >, [< Rn >]

{} < Rd > < Rm > < Rn >

. , . . . .

{cond} Rn[1:0] == 0b00 temp = Memory[Rn,4] Rn[1:0] == 0b01 temp = Memory[Rn,4] ROR 8 Rn[1:0] == 0b10 temp = Memory[Rn,4] ROR 16 Rn[1:0] == 0b11 temp = Memory[Rn,4] ROR 24

Memory[Rn,4] = Rm Rd = temp

120

6.Instruction Set

AT91

6.2.18

SWPB31 28 27 26 25 24 23 22 21 20 00010100 19 16 15 12 11 8 0000 7654 1001 3 0 Rm cond Rn Rd

SWPB (SWaP Byte) 8 ( ). Rm Rn Rd. Rn & Rm, . SWP{}B < Rd >, < Rm >, [< Rn >]

{} < Rd > < Rm > < Rn >

. , . . . .

{cond} temp = Memory[Rn,1] Memory[Rn,1] = Rm[7:0] Rd = temp SWP & SWPB .

121

AT91

6.3 -

6.3 6.3.1 B,BL31 28 cond 27 26 25 101 24 L 23 signed_immed_24 0

B (Branch) & BL (Branch and Link) . B{L}{} < target_address > L R14. . , . . : 1. < target_address > pou pareqetai sthn entolh (yhfia 23 ewc 0 tou kwdikou leitourgiac) apo ta 24 sta 32 yhfia . 2. 2 . 3. (PC + 8). 32M B PC. {cond} L == 1 LR = address of next instruction PC = PC + SignExtend(immed_24) LeftShift 2 BL . R14 R15. , Assembler .

{} < target_address >

122

6.Instruction Set

AT91

6.3.2

BX31 28 27 26 25 24 23 22 21 20 00010010 19 16 0000 15 12 11 8 7654 0001 3 0 Rm cond 0000 0000

BX (Branch and eXchange) Rm, ARM Thumb. 4. BX{} < Rm >

{} < Rm >

. , . .

{cond} T Flag == Rm[0] LR = address of next instruction PC = Rm AND 0xFFFFFFFE BX . ARM, Thumb, MOV PC.

123

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