1Motorola TMOS Power MOSFET Transistor Device Data

P–Channel Enhancement–Mode Silicon Gate

This high voltage MOSFET uses an advanced terminationscheme to provide enhanced voltage–blocking capability withoutdegrading performance over time. In addition, this advanced TMOSE–FET is designed to withstand high energy in the avalanche andcommutation modes. The new energy efficient design also offers adrain–to–source diode with a fast recovery time. Designed for highvoltage, high speed switching applications in power supplies,converters and PWM motor controls, these devices are particularlywell suited for bridge circuits where diode speed and commutatingsafe operating areas are critical and offer additional safety marginagainst unexpected voltage transients.

• Robust High Voltage Termination• Avalanche Energy Specified• Source–to–Drain Diode Recovery Time Comparable to a Discrete

Fast Recovery Diode• Diode is Characterized for Use in Bridge Circuits• IDSS and VDS(on) Specified at Elevated Temperature

MAXIMUM RATINGS (TC = 25°C unless otherwise noted)

Rating Symbol Value Unit

Drain–Source Voltage VDSS 500 Vdc

Drain–Gate Voltage (RGS = 1.0 MΩ) VDGR 500 Vdc

Gate–Source Voltage — ContinuousGate–Source Voltage — Non–Repetitive (tp ≤ 10 ms)

VGSVGSM

± 20± 40

VdcVpk

Drain Current — ContinuousDrain Current — Continuous @ 100°CDrain Current — Single Pulse (tp ≤ 10 µs)

IDID

IDM

2.01.66.0

Adc

Apk

Total Power DissipationDerate above 25°C

PD 750.6

WattsW/°C

Operating and Storage Temperature Range TJ, Tstg –55 to 150 °C

Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C(VDD = 100 Vdc, VGS = 10 Vdc, IL = 4.0 Apk, L = 10 mH, RG = 25 Ω)

EAS 80 mJ

Thermal Resistance — Junction to CaseThermal Resistance — Junction to Ambient

RθJCRθJA

1.6762.5

°C/W

Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds TL 260 °C

Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limitcurves — representing boundaries on device characteristics — are given to facilitate “worst case” design.

E–FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.

Preferred devices are Motorola recommended choices for future use and best overall value.

REV 2

Order this documentby MTP2P50E/D

SEMICONDUCTOR TECHNICAL DATA

Motorola, Inc. 1999

TMOS POWER FET2.0 AMPERES

500 VOLTSRDS(on) = 6.0 OHM

Motorola Preferred Device

CASE 221A–09, Style 5TO–220AB

D

S

G

2 Motorola TMOS Power MOSFET Transistor Device Data

ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)

Characteristic Symbol Min Typ Max Unit

OFF CHARACTERISTICS

Drain–Source Breakdown Voltage(VGS = 0 Vdc, ID = 250 µAdc)Temperature Coefficient (Positive)

V(BR)DSS500—

—564

——

VdcmV/°C

Zero Gate Voltage Drain Current(VDS = 500 Vdc, VGS = 0 Vdc)(VDS = 500 Vdc, VGS = 0 Vdc, TJ = 125°C)

IDSS——

——

10100

µAdc

Gate–Body Leakage Current (VGS = ±20 Vdc, VDS = 0) IGSS — — 100 nAdc

ON CHARACTERISTICS (1)

Gate Threshold Voltage(VDS = VGS, ID = 250 µAdc)Temperature Coefficient (Negative)

VGS(th)2.0—

3.04.0

4.0—

VdcmV/°C

Static Drain–Source On–Resistance (VGS = 10 Vdc, ID = 1.0 Adc) RDS(on) — 4.5 6.0 Ohm

Drain–Source On–Voltage (VGS = 10 Vdc)(ID = 2.0 Adc)(ID = 1.0 Adc, TJ = 125°C)

VDS(on)——

9.5—

14.412.6

Vdc

Forward Transconductance (VDS = 15 Vdc, ID = 1.0 Adc) gFS 0.5 — — mhos

DYNAMIC CHARACTERISTICS

Input Capacitance(V 25 Vd V 0 Vd

Ciss — 845 1183 pF

Output Capacitance (VDS = 25 Vdc, VGS = 0 Vdc,f = 1.0 MHz)

Coss — 100 140

Reverse Transfer Capacitancef 1.0 MHz)

Crss — 26 52

SWITCHING CHARACTERISTICS (2)

Turn–On Delay Time td(on) — 12 24 ns

Rise Time (VDD = 250 Vdc, ID = 2.0 Adc,VGS = 10 Vdc

tr — 14 28

Turn–Off Delay TimeVGS = 10 Vdc,

RG = 9.1 Ω) td(off) — 21 42

Fall TimeG

tf — 19 38

Gate Charge(See Fig re 8)

QT — 19 27 nC(See Figure 8)

(VDS = 400 Vdc, ID = 2.0 Adc, Q1 — 3.7 —( DS DVGS = 10 Vdc) Q2 — 7.9 —

Q3 — 9.9 —

SOURCE–DRAIN DIODE CHARACTERISTICS

Forward On–Voltage (1)(IS = 2.0 Adc, VGS = 0 Vdc)

(IS = 2.0 Adc, VGS = 0 Vdc, TJ = 125°C)

VSD——

2.31.85

3.5—

Vdc

Reverse Recovery Time(See Fig re 14)

trr — 223 — ns(See Figure 14)

(IS = 2.0 Adc, VGS = 0 Vdc, ta — 161 —( S GSdIS/dt = 100 A/µs) tb — 62 —

Reverse Recovery Stored Charge QRR — 1.92 — µC

INTERNAL PACKAGE INDUCTANCE

Internal Drain Inductance(Measured from contact screw on tab to center of die)(Measured from the drain lead 0.25″ from package to center of die)

LD——

3.54.5

——

nH

Internal Source Inductance(Measured from the source lead 0.25″ from package to source bond pad)

LS — 7.5 — nH

(1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.(2) Switching characteristics are independent of operating junction temperature.

3Motorola TMOS Power MOSFET Transistor Device Data

TYPICAL ELECTRICAL CHARACTERISTICS

0 4 8 280

1

2

3

4

VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)

Figure 1. On–Region Characteristics

I D, D

RAI

N C

UR

REN

T (A

MPS

)

2 3 4 5 6 70

1

2

3

4

I D, D

RAI

N C

UR

REN

T (A

MPS

)

VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)

Figure 2. Transfer Characteristics

0 1 2 2.5 3.5 40

2

6

10

RD

S(on

), DR

AIN

-TO

-SO

UR

CE

RES

ISTA

NC

E (O

HM

S)

0 1 2 3 44

4.5

5

5.5

6

ID, DRAIN CURRENT (AMPS)

Figure 3. On–Resistance versus Drain Currentand Temperature

ID, DRAIN CURRENT (AMPS)

Figure 4. On–Resistance versus Drain Currentand Gate Voltage

0.5

1

1.5

2

RD

S(on

)

1

10

100

1000

TJ, JUNCTION TEMPERATURE (°C)

Figure 5. On–Resistance Variation with Temperature

VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)

Figure 6. Drain–To–Source LeakageCurrent versus Voltage

, DR

AIN

-TO

-SO

UR

CE

RES

ISTA

NC

E (O

HM

S)

, DR

AIN

-TO

-SO

UR

CE

RES

ISTA

NC

E(N

OR

MAL

IZED

)

I DSS

, LEA

KAG

E (n

A)

TJ = 25°C VDS ≥ 10 V

TJ = – 55°C

25°C

100°C

TJ = 100°C

TJ = 25°C

VGS = 0 V

VGS = 10 V

VGS = 10 V

VGS = 10 VID = 1 A

12 16

6 V

5 V

3.5

2.5

1.5

0.5

2.5 3.5 4.5 5.5 6.5

4

8

31.50.5

25°C

– 55°C

VGS = 10 V

15 V

– 50 – 25 0 25 50 75 100 125 150 0 10050 150 200 250 500300 350 400 450

TJ = 125°C

100°C

25°C

0.5 1.5 2.5 3.5

3.5

2.5

1.5

0.5

20 24

4 V

8 V

7 V

5.75

5.25

4.75

4.25

RD

S(on

)

4 Motorola TMOS Power MOSFET Transistor Device Data

POWER MOSFET SWITCHING

Switching behavior is most easily modeled and predictedby recognizing that the power MOSFET is charge controlled.The lengths of various switching intervals (∆t) are deter-mined by how fast the FET input capacitance can be chargedby current from the generator.

The published capacitance data is difficult to use for calculat-ing rise and fall because drain–gate capacitance variesgreatly with applied voltage. Accordingly, gate charge data isused. In most cases, a satisfactory estimate of average inputcurrent (IG(AV)) can be made from a rudimentary analysis ofthe drive circuit so that

t = Q/IG(AV)During the rise and fall time interval when switching a resis-tive load, VGS remains virtually constant at a level known asthe plateau voltage, VSGP. Therefore, rise and fall times maybe approximated by the following:

tr = Q2 x RG/(VGG – VGSP)

tf = Q2 x RG/VGSPwhere

VGG = the gate drive voltage, which varies from zero to VGGRG = the gate drive resistance

and Q2 and VGSP are read from the gate charge curve.

During the turn–on and turn–off delay times, gate current isnot constant. The simplest calculation uses appropriate val-ues from the capacitance curves in a standard equation forvoltage change in an RC network. The equations are:

td(on) = RG Ciss In [VGG/(VGG – VGSP)]

td(off) = RG Ciss In (VGG/VGSP)

The capacitance (Ciss) is read from the capacitance curve ata voltage corresponding to the off–state condition when cal-culating td(on) and is read at a voltage corresponding to theon–state when calculating td(off).

At high switching speeds, parasitic circuit elements com-plicate the analysis. The inductance of the MOSFET sourcelead, inside the package and in the circuit wiring which iscommon to both the drain and gate current paths, produces avoltage at the source which reduces the gate drive current.The voltage is determined by Ldi/dt, but since di/dt is a func-tion of drain current, the mathematical solution is complex.The MOSFET output capacitance also complicates themathematics. And finally, MOSFETs have finite internal gateresistance which effectively adds to the resistance of thedriving source, but the internal resistance is difficult to mea-sure and, consequently, is not specified.

The resistive switching time variation versus gate resis-tance (Figure 9) shows how typical switching performance isaffected by the parasitic circuit elements. If the parasiticswere not present, the slope of the curves would maintain avalue of unity regardless of the switching speed. The circuitused to obtain the data is constructed to minimize commoninductance in the drain and gate circuit loops and is believedreadily achievable with board mounted components. Mostpower electronic loads are inductive; the data in the figure istaken with a resistive load, which approximates an optimallysnubbed inductive load. Power MOSFETs may be safely op-erated into an inductive load; however, snubbing reducesswitching losses.

GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS)

C, C

APAC

ITAN

CE

(pF)

Figure 7a. Capacitance Variation

1800

1600

1400

1200

1000

800

600

0

VGS VDS

Figure 7b. High Voltage CapacitanceVariation

VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)

1000

100

10

1

C, C

APAC

ITAN

CE

(pF)

VGS = 0 V

10 5 0 5 10 15 20 25

Crss

Ciss

Ciss

CossCrss

10 100 1000

Ciss

Coss

Crss

VGS = 0 VTJ = 25°C

400

200

VDS = 0 V TJ = 25°C

5Motorola TMOS Power MOSFET Transistor Device Data

DRAIN–TO–SOURCE DIODE CHARACTERISTICS

0.6 1 1.4 1.8 2.4

VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

I S, S

OU

RC

E C

UR

REN

T (A

MPS

)

Figure 9. Resistive Switching TimeVariation versus Gate Resistance

RG, GATE RESISTANCE (OHMS)

1000

t, TI

ME

(ns)

tr

tftd(off)

td(on)

VGS = 0 VTJ = 25°C

Figure 8. Gate–To–Source and Drain–To–SourceVoltage versus Total Charge

300

V GS,

GAT

E-TO

-SO

UR

CE

VOLT

AGE

(VO

LTS)

250

200

150

0

10

6

0

QT, TOTAL CHARGE (nC)

VDS

, DR

AIN-TO

-SOU

RC

E VOLTAG

E (VOLTS)

12

8

2

4

2

4 6 8 10 12 14 16 18 20

100

50

0

VDD = 250 VID = 2 AVGS = 10 VTJ = 25°C

100

101 10 100

2

1.6

1.2

0.8

0.4

00.8 1.2 1.6

Q1 Q2

QT

VDSQ3

2 2.2

VGS

ID = 2 ATJ = 25°C

SAFE OPERATING AREA

The Forward Biased Safe Operating Area curves definethe maximum simultaneous drain–to–source voltage anddrain current that a transistor can handle safely when it is for-ward biased. Curves are based upon maximum peak junc-tion temperature and a case temperature (TC) of 25°C. Peakrepetitive pulsed power limits are determined by using thethermal response data in conjunction with the proceduresdiscussed in AN569, “Transient Thermal Resistance–GeneralData and Its Use.”

Switching between the off–state and the on–state may tra-verse any load line provided neither rated peak current (IDM)nor rated voltage (VDSS) is exceeded and the transition time(tr,tf) do not exceed 10 µs. In addition the total power aver-aged over a complete switching cycle must not exceed(TJ(MAX) – TC)/(RθJC).

A Power MOSFET designated E–FET can be safely usedin switching circuits with unclamped inductive loads. For reli-

able operation, the stored energy from circuit inductance dis-sipated in the transistor while in avalanche must be less thanthe rated limit and adjusted for operating conditions differingfrom those specified. Although industry practice is to rate interms of energy, avalanche energy capability is not a con-stant. The energy rating decreases non–linearly with an in-crease of peak current in avalanche and peak junctiontemperature.

Although many E–FETs can withstand the stress of drain–to–source avalanche at currents up to rated pulsed current(IDM), the energy rating is specified at rated continuous cur-rent (ID), in accordance with industry custom. The energy rat-ing must be derated for temperature as shown in theaccompanying graph (Figure 12). Maximum energy at cur-rents below rated continuous ID can safely be assumed toequal the values indicated.

6 Motorola TMOS Power MOSFET Transistor Device Data

SAFE OPERATING AREA

TJ, STARTING JUNCTION TEMPERATURE (°C)

E AS, S

ING

LE P

ULS

E D

RAI

N–T

O–S

OU

RC

E

Figure 12. Maximum Avalanche Energy versusStarting Junction Temperature

0.1 10 1000

VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)

Figure 11. Maximum Rated Forward BiasedSafe Operating Area

10

AVAL

ANC

HE

ENER

GY

(mJ)

I D, D

RAI

N C

UR

REN

T (A

MPS

)

RDS(on) LIMITTHERMAL LIMITPACKAGE LIMIT

0.0125 50 75 100 125

80ID = 2 A

1

0.1

1 100 150

t, TIME (s)

Figure 13. Thermal Response

r(t),

NO

RM

ALIZ

ED E

FFEC

TIVE

TRAN

SIEN

T TH

ERM

AL R

ESIS

TAN

CE

RθJC(t) = r(t) RθJCD CURVES APPLY FOR POWERPULSE TRAIN SHOWNREAD TIME AT t1TJ(pk) – TC = P(pk) RθJC(t)

P(pk)

t1t2

DUTY CYCLE, D = t1/t2

Figure 14. Diode Reverse Recovery Waveform

di/dt

trrta

tp

IS

0.25 IS

TIME

IS

tb

1 ms

10 ms

100 µs

dc

60

40

20

0

1

0.1

0.011.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01

D = 0.5

0.2

0.1

0.05

0.020.01

SINGLE PULSE

10 µsVGS = 20 VSINGLE PULSETC = 25°C

7Motorola TMOS Power MOSFET Transistor Device Data

PACKAGE DIMENSIONS

CASE 221A–09ISSUE Z

STYLE 5:PIN 1. GATE

2. DRAIN3. SOURCE4. DRAIN

NOTES:1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.2. CONTROLLING DIMENSION: INCH.3. DIMENSION Z DEFINES A ZONE WHERE ALL

BODY AND LEAD IRREGULARITIES AREALLOWED.

DIM MIN MAX MIN MAXMILLIMETERSINCHES

A 0.570 0.620 14.48 15.75B 0.380 0.405 9.66 10.28C 0.160 0.190 4.07 4.82D 0.025 0.035 0.64 0.88F 0.142 0.147 3.61 3.73G 0.095 0.105 2.42 2.66H 0.110 0.155 2.80 3.93J 0.018 0.025 0.46 0.64K 0.500 0.562 12.70 14.27L 0.045 0.060 1.15 1.52N 0.190 0.210 4.83 5.33Q 0.100 0.120 2.54 3.04R 0.080 0.110 2.04 2.79S 0.045 0.055 1.15 1.39T 0.235 0.255 5.97 6.47U 0.000 0.050 0.00 1.27V 0.045 ––– 1.15 –––Z ––– 0.080 ––– 2.04

Q

H

Z

L

V

G

N

A

K

1 2 3

4

D

SEATINGPLANE–T–

CST

U

R

J

8 Motorola TMOS Power MOSFET Transistor Device Data

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regardingthe suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, andspecifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motoroladata sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights ofothers. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or otherapplications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injuryor death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorolaand its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney feesarising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges thatMotorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an EqualOpportunity/Affirmative Action Employer.

Mfax is a trademark of Motorola, Inc.How to reach us:USA/EUROPE/Locations Not Listed : Motorola Literature Distribution; JAPAN : Motorola Japan Ltd.; SPD, Strategic Planning Office, 141,P.O. Box 5405, Denver, Colorado 80217. 1–303–675–2140 or 1–800–441–2447 4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan. 81–3–5487–8488

Customer Focus Center: 1–800–521–6274

Mfax : RMFAX0@email.sps.mot.com – TOUCHTONE 1–602–244–6609 ASIA/PACIFIC : Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre,Motorola Fax Back System – US & Canada ONLY 1–800–774–1848 2, Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong.

– http://sps.motorola.com/mfax/ 852–26668334HOME PAGE: http://motorola.com/sps/

MTP2P50E/D◊