ISSCC94 I SESSION 3 I ANALOG TECHNIQUES I PAPER WP 3.8 -_ - -.___.

WP 3.8: A Switched-Capacitor Filter in 2pm CMOS using Parallelism to Sample at 80MHz

Steven K. Berg’, Paul J. Hurst, Stephen H. Lewis, Paul T. Wong’

University of Califomia, Davis, CA ‘Now with National Semiconductor, Santa Clara, CA

Switched-capacitor filters (SCFs) are usually used in low- frequency applications, where the ratio of sample rate to corner frequency is high enough so that only simple anti-alias filters are required. At video bandwidths in CMOS technolo- gies, however, op-amp settling time limits this ratio and increases the complexity of the anti-alias filter 111. Op amps and anti-aliasing are not needed with a continuous-time, transconductance-capacitor structure, but this approach re- quires complex tuning [2, 31. To avoid such tuning and to increase the sample-rate-to-corner-frequency ratio, this pa- per describes a prototype SCF that uses parallelism.

Figure 1 shows the transfer function and pole-zero diagram of a one-pole bilinear filter that samples at 40MHz. This serves as an example to describe the parallel filter concept. Here pis the pole of G(z), and z 1 represents a delay of T=1/40MHz. To double the sample rate without increasing the required op- amp speed, two identical bilinear sections can be time-inter- leaved. If they are perfectly matched, this approach doubles the frequency range for which no aliasing occurs to O-40MHz. However, because the overall transfer function of an N-path filter is equal to that of each path, this approach does not change the transfer function of the filter [41.

Figure 2 shows the transfer function and pole-zero diagram of the same filter from an 80MHz standpoint. The denominator has been factored into two terms, and z-”represents a delay of lB0MHz. A new pole arises a t -p” here, and the original pole shifts from p to p“. These two poles cause the magnitude response to be periodic with a period of 40MHz, as in Figure 1. To maintain the desiredlo~-passcharacteristicto40MHz, the new pole can be canceled with a zero generated by a two-tap FIR filter 151. To build the FIR filter with op amps that operate at 40MHz, two identical interleaved FIR filters can be used as shown in Figure 3. Here the outputs of the top FIR filter are sampledatnTand thoseofthebottomfilter,at(n+1/2)T, where n=0,1,2 ,... and T=1/40MHz.

Extension of this technique to higher-order filters requires more taps in the FIR filter. With biquadratic instead of bilinear sections operating in parallel, for example, Figure 1 would include two poles. As a result, Figure 2 would include four poles, two ofwhich must be canceled. Therefore, the FIR filter would need three taps instead of two. In general, the FIR filter requires one more tap than the order of the parallel filters. To limit the complexity of the FIR filter, parallel biquadratic and bilinear structures can be cascaded to realize higher-order filters.

The parallel filter technique is used to build a prototype 5th- order SCF with pass band from O-4MHz and stop band above 6MHz in a 2pm CMOS technology. Phase linearity is not a design goal, and a phase equalizer may be required in some applications. The filter consists of two parallel biquadratic sections (each with two poles and no zeros), together operating at an input sample rate of SOMHz, a three-tap FIR filter, and a 3rd-order post filter, operating at a 40MHz sample rate (Figure 3). Since the post filter only samples the output of the FIR filter a t 40MHz, only one FIR filter in Figure 3 is needed.

The post filter includes transmission zeros to increase stop- band attenuation. The parallel biquadraticfilters and the post filter use double sampling. As a result, for each to sample its input a t a 40MHz rate, the op-amp settling time must be less than 25x1s. Figure 4 shows a simplified block diagram of the FIR filter. It consists of three sample-and-sum sections. Each section contains three sample-and-hold circuits, a weighted summer, and several switches. Each switch opens at the labeled time and closes T before that, where n=0,1,2,.. and T=l/40MHz. So the first section samples the biquadratic outputsattimes3nT, (3n+1/2)T, and(3n+l)Tandproduces the FIR output at time (3n+2)T. The other sections behave sinii- larly. All three sample-and-sum sections share one op amp.

Eight identical op amps are used (two in each biquadratic filter, one in the FIR filter, and three in the post filter). To achieve high gain and fast settling time, the op amps use a telescopic cascode structure [61. The maximum capacitor ratio is only 5.4, allowing the use of a large unit capacitor (0.35pF) to achieve the matching, important to assure pole-zero cancel- lation and to limit fixed-pattern noise. The circuits are all parasitic-insensitive. To increase dynamic range and PSRR, and to reduce even-harmonic distortion, the filter is fully differential. This also reduces the effects of charge injection and clock feed-through, important because mismatches in these nonidealities contribute to fixed-pattern noise.

Figure 5 shows the measured filter frequency response from dc to 40MHz (solid) and from dc to 4MHz (dashed). The filter exhibits a magnitude response that is in agreement with simulations. Because the post filter samples at 40MHz, an input a t frequency f appears also at 4OMHz-f. Ofmost concern are signals in the 36 to 40MHz range because those frequen- cies alias into the pass band. Measured attenuation of signals in that range exceeds 30dB (compared to 36dB predicted by simulation). Figure 6 shows an output spectrum of the filter with zero input. Small components at 13.3MHz (= 40/3MHz, from mismatches in the three sample-and-sum stages in the FIR filter), 20MHz (= 40/2MHz, from mismatches in the double-sampled biquads), and 26.6MHz (second harmonic of 13.3MHz) are present. These tones contribute to fixed-pattern noise, and the magnitudes are together 1.2mVrms. Figure 7 is a chip micrograph. Table 1 summarizes performance.

Acknowledgment

This research was supported by UC MICRO Grant No. 92-063 and by NSF Grant No. MIP-9210071.

References

[l] Song, B.-S., “A 10.7-MHz Switched-Capacitor Bandpass Filter,” IEEE J. Solid-state Circuits, vol. 24, pp. 320-324, April 1989.

[21 Gopinathan, V., et. al.,”Design Considerations for High-Frequency Continuous-Time Filters and Implementation of an Antialiasing Filter for Digitalvide,” IEEE J. Solid-state Circuits, vol. 25, pp. 1368- 1378, Dec. 1990.

[31 Khoury J. M., “Design ofa 15MHz CMOS Continuous-Time Filter with On-Ckp Tuning,” IEEE J. Solid-state Circuits, vol. 26, pp. 1988- 1997, Dec. 1991.

[41 Gregorian, R. and Temes, G. C., “Analog MOS Integrated Circuits for Signal Processing,” Wiley, pp. 363-387, 1986.

[51 Martins, H. P., et. al., “An Optimum CMOS Switched-Capacitor Antialiasing Decimating Filter,” IEEE J. Solid-state Circuits. vol. 28, pp. 962-970, Sept. 1993.

[61 Nicollini, G., et. al.. “High-Frequency Fully Differential Filter Using Operational Amplifiers Without Common-Mode Feedback,” IEEE J. Solid-state Circuits, vol. 24, pp. 803-813, June 1989.

ISSCC94 I WEDNESDAY, FEBRUARY 16,1994 / SEA CLIFF /5:00 PM

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/ \ Mag , 1-1 (dB)

dashed -- Figure 1: Pole-zero diagram and transfer solid -- ---- function of a one-pole bilinear filter sampling at 40MHz. -60

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10 Figure 2 Pole-zero diagram and transfer function from

the standpoint of an 8 0 m z sampling rate.

40 MHz 40 MHz 1

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40 MHz 40 MHz

Pattern Noise = 1.2 mVrms

I I I I 0 10 20 30 40

Freq (MHz)

Figure 3: Filter block diagram with 0.01 ' time interleaving.

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Figure 6: Output spectrum of filter with zero input.

Figure 7: See page 311.

Technology 2pm CMOS Active area l lmmz

+Vf Power dissipation 19OmW Input sampling rate 80MHz Pass band 0-4MHz Pass-band ripple -3dB bandwidth 4.2MHz

Fixed-pattern noise1.2mV rms

PSRR (1001612) 55dB CMRR (100kHz) 74dB

i 1.3dB p-p

Dynamic range 57dB

THD (Vout = 2Vp-p) < -66dB

Table 1: Performance summary (5V and 25°C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . %+3-&+4+ . . . ._ . . . - - . . . - -J

Figure 4: FIR Filter.

DJGEST OF TECHNICAL PAPERS 63