Reliability Assessment of Voltage Controlled

Oscillators in 32nm High-κ Metal Gate Technology

Florian Raoul Chouard∗, Michael Fulde† and Doris Schmitt-Landsiedel∗

∗Lehrstuhl fur Technische Elektronik, Technische Universitat Munchen, Germany, Email: florian.chouard@tum.de†Infineon Technologies AG, Villach, Austria

Abstract— A general approach to handle end-of-lifetime relia-bility of voltage controlled LC oscillators in advanced technologynodes is presented. Investigations base upon a state-of-the artLC-VCO design for GSM applications, designed and fabricatedin a 32nm high-κ, metal gate technology. We find that mainlynon-destructive device degradation in the active bridge leads tosmall supply current degradation, which significantly increasesfor elevated supply voltages. Based on the easy accessableparameter ’startup supply voltage’, circuit aging is monitoredand a simplified model is derived that reveals the contributionof different aging mechanisms. Our approach to map realisticcircuit level aging in an accelerated test setup bases on thedominant aging contributor. Comparison of model, simulationand measurement results proves the coherence of this approachand the impact on the performance parameters of the investigatedVCO.

I. INTRODUCTION

Non-constant field scaling in advanced CMOS technology

nodes increases the emergence of well known electrical field

driven degradation effects like Negative Bias Temperature

Instability (NBTI) in pFETs and Hot-Carrier Injection (HCI).

Introduction of high-κ materials into MOS dielectrics induces

further degradation effects like Positive Bias Temperature

Instability (PBTI) in nFETs [1]. Device degradation impact

on digital and analog circuits, design-in reliability modeling

and countermeasures are treated in [2]–[6]. A new field of

interest arises from the need of circuit level aging test. Adapted

from single device testing, the state-of-the-art predictive circuit

reliability testing is stressing the circuit with elevated tem-

peratures and voltages. But diversity in aging effect physics

provides differing circuit behavior under stress conditions,

and end-of-lifetime aging under realistic circuit conditions is

not per se accurately predicted. A first approach to obtain

accelerated stress pattern to map realistic aging cases on an

differential amplifier is published in [7].

To meet challenging phasenoise specifications, LC-VCO cir-

cuits typically provide large voltage swings in the range of

the nominal supply voltage or above. To guarantee circuit

reliability, device degradations have to be taken into account.

In [8], [9] investigations show that aging mechanisms decrease

oscillation amplitude and as a result increase phasenoise levels.

The upcoming aging effect ’off-state stress/non-conductive

HCI (NCHCI)’ in advanced technologies was observed to be

a main contributor to VCO performance degradation [10]. The

study showed that HCI not only attenuates transistor current

characteristics but also increases device flicker noise and hence

directly influences close-in phasenoise.

In this work we first present the technology related aging

models we have used and discuss their usage in circuit age

prediction. Next, the investigated LC-VCO topology and influ-

ence of degradation on different circuit parts are discussed. A

parameter suitable as circuit aging monitor and corresponding

simplified model is introduced. Via this model a realistic

aging setup is derived and simulations as well as measurement

results are shown. In the outlook, trends in expected LC-VCO

reliability problems and corresponding design approaches are

discussed.

II. DEVICE DEGRADATION MECHANISMS

All investigated circuits are designed in a Hf-based 32nm

high-κ, metal gate (HK/MG) technology [11]. Regarding

device degradation, we account for BTI effects as well as

HCI mechanisms for conductive and non-conductive transistor

state. Degradation prediction is performed via semi-empirical

modeling based on [2], [3], [5]. Both types of BTI effects are

modeled as a shift of threshold voltage

∆Vth = A · (Vgs

tinv)m · e(

∆E

kT) · Lα ·W β · tn. (1)

HCI degradation for both nMOS and pMOS is considered as

a decrease of drain current and is predicted via

∆Id

Id= B · V p

ds · e(∆H

kT) · Lχ · tq (2)

for conductive and non-conductive state with a distinct param-

eter set. To account for time varying voltage stress, the models

are implemented for simulation with the aging tool RelXpert™

[12]. RelXpert™ is used to derive correction factors mapping

the AC degradation in oscillators to corresponding DC stress.

III. LC VOLTAGE CONTROLLED OSCILLATORS

A. Circuit Topology

The following modeling, simulations and measurements

base on a state-of-the-art differential LC-VCO topology de-

signed for GSM applications (fig. 1). The circuit is imple-

mented in 32nm HK/MG technology providing medium oxide

devices to sustain high voltage swing and meet the GSM

phasenoise specification. The design provides a combined

tuning scheme of coarse and analog tuning to achieve the wide

tuning range of the 3.0-4.3 GHz band. The current-reusing

topology is employed to reduce power consumption. For

978-1-4244-6664-1/10/$26.00 ©2010 IEEE 410

Mp1 Mn1

Mp2 Mn2

VDD VSS

LtailLtail

ACTIVE BRIDGESWITCHED CAPS

VARACTORS

COIL

outp

outn

Fig. 1. Schematic of the differential LC-VCO

0 0.05 0.1 0.15 0.2 0.25 0.3

0

0.2

0.4

0.6

0.8

1

HCIMp Mn

PBTI Mn1NCHCI Mn2

PBTI Varactor

NBTI Mp2NCHCI Mp1

HCIMp Mn

PBTI Mn2NCHCI Mn1

PBTI Varactor

NBTI Mp1NCHCI Mp2

Time [ns]

Vo

lta

ge

[V

DD

]

outpoutn

Fig. 2. VCO oscillation sequence: separation in device stress intervals

further details on the circuit specifications and measurement

setup refer to [13]. In the following investigations coarse

tuning of the VCO is fixed and circuit characteristics are

evaluated around 3 GHz.

B. VCO Aging

In principle, all MOS devices in the VCO core are affected

by degradation. As depicted in figure 2, the stress conditions

can be devided into two main regions. In the first one, when

outputs reach peak voltages, devices of the active bridge are

exposed either to BTI or to NCHCI stress, and inversion mode

MOS Varactors to BTI. In the region of transition, all active

bridge devices are exposed to conductive HCI. All following

figures depict simulations as well as measurement results,

where the latter will be discussed in section III-E. Fig. 3 shows

simulated analog frequency tuning behavior for the virgin and

an exemplary aging case at elevated supply voltage. Closer

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.82.95

3

3.05

3.1

Fre

qu

en

cy [

GH

z]

measurement virgin

measurement accelerated aging 1000s, 2.68 V, 25 °C

simulation virginsimulation aged: 10y, 125% V

DD, 25 °C

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.811.5

12

12.5

13

13.5

∆Icore

= 0.30 mA

∆Icore

= 0.29 mA

I core

[m

A]

Vtune

[V]

Fig. 3. VCO analog tuning: simulation for virgin circuit and after 10y ofoperation with 125%VDD at 25°C; measurement results with an equivalentaccelerated aging setup

104

105

106

107

−150

−140

−130

−120

−110

−100

−90

−80

−70

Ph

ase

no

ise

[d

Bc/H

z]

Frequency offset [Hz]

measurement virgin

measurement accelerated aging: 1000s, 2.78 V, 25 °C

simulation virginsimulation aged: 10y, 130% V

DD, 25 °C

simulation accelerated aging: 1000s, 2.78 V, 25 °C

Fig. 4. VCO phase noise simulation for virgin and aged (10y, 130%VDD ,25°C) circuit as well as measurement results with an equivalent acceleratedaging setup

investigation revealed that mainly degradation of the active

bridge transitors leads to a change in circuit behavior. The

decrease in transistor current reduces supply current of the

LC core and oscillation amplitude decreases. According to the

phase noise definition

L(∆ω) = 10 log10(Psideband(ωc +∆ω)

Pcarrier(ωc)) (3)

a drop in carrier power Pcarrier and a coeval variation in

Psideband, due to the drift of operating points, would affect

phase noise levels L. In fact, even for tough stress cases,

simulations in figure 4 show only minor phase noise degrada-

tions due to device aging. This is related to the small induced

variations in Pcarrier and Psideband due to the robust design.

In the worst case, for large degradations of the active bridge

devices, startup ability of the oscillation can be affected.

However, if the circuit operates in the nominal and worst-

case supply voltage range current degradations are small

and impacts can be easily covered by design margins. Our

investigations regarding the aging of varactors revealed that

degradation induced threshold voltage shift hardly affects the

equivalent capacitance. In fact, amplitude degradations due

to aging of the active bridge impacts the equivalent varactor

capacitance to a larger extent. These findings are consistent

with [8] and can also be deduced from the frequency stability

in figure 3. As simulated and measured shifts in frequency are

very low we neglect degradation of varactors in the further

considerations.

C. VCO Aging Model

To monitor VCO aging we chose to map oscillator aging

onto the ∆VDD,start that is necessary for proper oscillation

startup. The advantage of this aging monitor in contrast to the

supply current in oscillation is the simple modelling of this

operating point as well as the easy measurement. To determine

the startup operating point, one branch of the circuit in fig. 1

can be reduced to the schematic in fig. 5. In this operating

point,

gm,start = gm,n,start + gm,p,start, (4)

411

Mp Mn

VDD

VS

VSS

Fig. 5. VCO startup model

30 40 50 60 70 80 90 100 110 1200

5

10

Temperature [°C]

∆V

DD

,sta

rt [

mV

]

1.8 1.9 2 2.1 2.2 2.3 2.4 2.50

100

200

Core supply voltage [V]

∆V

DD

,sta

rt [

mV

]

ModelPBTI ModelNBTI ModelRelXpert SimulationAccelerated SetupMeasurement

Fig. 6. VCO aging model: ∆VDD,start behavior due to temperature (VDD)and supply voltage rise (25°C) after 10y of operation

whereas gm,start represents gm of the branch for VDD,start,

the lowest supply voltage to start oscillation. For startup of

the virgin and the aged circuit we have to fulfill that

gm,start,virgin = gm,start,aged. (5)

From 4 and 5 we can deduce in detail

µnCox(W

L)n(VGSn,v − Vthn)+

µpCox(W

L)p(|VGSp,v| − |Vthp|) =

µnCox(W

L)n(VGSn,a − Vthn −∆Vthn)+

µpCox(W

L)p(|VGSp,a| − |Vthp| − |∆Vthp|)

(6)

and VGSn,v = VS , |VGSp,v| = VDD,start−VS , VGSn,a = VS+∆VS and |VGSp,a| = VDD,start + ∆VDD,start − VS −∆VS .

For symmetric bridge design, µnCox(WL)n ≈ µpCox(

WL)p eq.

6 reduces to a simple VCO aging model

∆VDD,start = ∆Vthn + |∆Vthp|. (7)

By deriving degradation AC factors as well as circuit ampli-

tude behavior due to supply and temperature rise and inclusion

of those into eq. 7, VCO aging behavior due to supply voltage

and temperature rise can be easily evaluated as depicted in

fig. 6. The model shows good matching with the RelXpert™

simulation results. It also reveals that considerable circuit

aging only occurs for elevated supply voltages. The rise of

temperature even reduces degradation of the current design.

This can be related to a reduction of voltage amplitude induced

by the temperature rise via reduced mobility. A main benefit

of this model is the direct access to the composition of

the aging monitor ∆VDD,start. Contributions resulting from

NBTI/pMOS and PBTI/nMOS are shown in fig. 6. Fig. 7

illustrates the composition of ∆VDD,start in dependence of

30 40 50 60 70 80 90 100 110 1200

50

100

Temperature [°C]

% ∆

VD

D,s

tart

PBTINBTI

1.8 1.9 2 2.1 2.2 2.3 2.4 2.580

90

100

2.57 V

2.49 V 2.68 V

2.59 V 2.78 V

2.70 V

Core supply voltage [V]

% ∆

VD

D,s

tart

Fig. 7. VCO aging model: Composition of ∆VDD,start of NBTI/pMOSand PBTI/nMOS, behavior due to temperature (VDD) and supply voltage rise(25°C) after 10y of operation, and equivalent stress voltages for stress timesof 103s and 104s

the stress parameters temperature and supply voltage. For

both stress cases circuit aging is dominated by PBTI, but

for temperature rise the ratio of PBTI and NBTI varies

considerably, as the NBTI effect exhibits a larger temperature

sensitivity as PBTI.

D. Realistic VCO Aging Concept

To map circuit aging of a realistic operation case onto an

accelerated stress setup requires the same composition in the

aging output monitor. A best fit can be achieved if stress

conditions are derived from the dominant aging mechanism

[7], that means its degradation values are equal:

∆Dreal(Treal, Vreal, treal)!= ∆Dacc(Tacc, Vacc, tacc). (8)

As an example to prove this concept we map VCO aging

cases for circuit operation with elevated supply voltage of

120%VDD, 125%VDD and 130%VDD at room temperature

after 10y of operation. Elevation of temperature is not used

for the accelerated stress setup, as it significantly shifts aging

effect composition. For stress times of 103s and 104s, supply

stress voltages are derived according to eq. 8. The obtained

equivalent stress voltages and related stress contributions are

also given in fig. 7. To judge mapping quality, the ∆VDD,start

obtained with the 103s stress setup is compared to the model

representing the 10y aging in fig. 6. The accelerated aging is

close to the 10y case proving good age mapping.

E. Measurement Results

To validate the aging concept, circuit measurements were

performed. In a first step output frequency and supply current

over the analog tuning range, phase noise for selected points

in the tuning range and corresponding startup supply voltage

was measured at the virgin circuits for nominal supply voltage

and at room temperature. In the second step equivalent stress

supply voltages were applied to the circuits for the defined

stress duration of tstress = 103s to perform accelerated circuit

aging. To avoid errors from relaxation phenomena due to the

accelerated stress condition, the circuit is switched off for

trelax = tstress before characterisation of the ’aged’ circuit is

repeated. Fig. 6 shows the good agreement between modeled

412

30 40 50 60 70 80 90 100 110 1200

2

4

6

Temperature [°C]

∆V

DD

,sta

rt [

mV

]

1 1.1 1.2 1.3 1.4 1.50

50

100

Core supply voltage [V]

∆V

DD

,sta

rt [

mV

]

ModelModel nMOS PBTIModel nMOS NCHCIModel pMOS NBTIRelXpert Simulation

Fig. 8. VCO thin oxide aging model: ∆VDD,start due to temperature(VDD) and supply voltage rise (25°C) after 10y of operation

and measured aging values for ∆VDD,start, validating the

correctness of the age acceleration approach.

Measured frequency tuning characteristic shows little degra-

dation impact and is consistent with the 10y aging simulation

(fig. 3). Absolute values of Icore show deviations in simulation

and measurement, but the mean values of current degrada-

tion ∆Icore of the virgin and the aged circuit are in good

agreement. The phase noise simulations in figure 4 show good

agreement for the 10y, 130%VDD aging and the corresponding

equivalent aging setup. Comparing simulation and measure-

ment, good matching in the thermal, but general deviance

in the 1f

-upconversion region is observed. We interpret this

behavior with an underestimation of 1f

-noise in the device

modeling. Furtheron, the measurement of the virgin and the

aged circuit shows an explicit larger degradation in the close-

in region compared to the simulation. Simulations revealed

that 1f

-noise of nMOS transistors in the active bridge is the

dominant contributor to the close-in phase noise. Obviously,

the PBTI device stress leads to an increase of 1f

-device noise.

A similar degradation induced increase in 1f

-noise, related to

NCHCI, was also reported in [10].

F. Outlook

To estimate a trend for future low power approaches,

a VCO design using thin oxide transistors with minimum

gate length in the active bridge and correspondingly reduced

supply voltage was designed, and a similar aging model

was evaluated. The resulting stress behavior is depicted in

fig. 8. With thin oxide devices, NCHCI evolves as a main

degradation mechanism that, for elevated supply voltages,

leads to significant supply current degradations. Total degra-

dations are smaller for the thin oxide version, but the circuit

is considerably more sensitive, as supply current is related

to the transistors’ overdrive voltage and the total voltage

headroom is significantly reduced. To guarantee proper startup

for all investigated stress cases additional margins have to be

incorporated to cover the increasing degradation sensitivity.

The option to increase transistor gate length significantly

reduces NCHCI and relaxes circuit degradation. Nevertheless,

regarding future design options reliability aspects essentially

have to be considered during the design process.

IV. CONCLUSION

We demonstrated that end-of-lifetime device aging in a

state-of-the-art LC-VCO leads to performance degradations,

which are low in the allowed supply voltage region, but

significantly increase for elevated supply voltages. We identi-

fied the active bridge as the degradation-critical circuit part,

whereas aging of inversion mode MOS varactors is negligible.

Device degradation of the active bridge decreases core current.

Resulting voltage amplitude degradation increases phase noise,

but can be covered by robust design. For large degradations

startup ability may be affected. With the easy accessable

parameter ’startup supply voltage’, we introduced a both prac-

tical and meaningful output monitor for circuit degradation.

Evaluation of our circuit model based on this monitor easily

reveals the contributions of the divers aging effects. We proved

via simulation and measurement that our approach of aging

acceleration for testing, based on the dominant degradation ef-

fect, provides realistic end-of-lifetime equivalent circuit aging.

Phase noise measurement revealed that device degradation also

affects noise behavior, which is not yet considered in today’s

age modeling. Our investigation regarding future trends in

LC VCO design predicts the increasing sensitivity of circuit

performance on degradation effects and confirms the need to

consider reliability aspects during the design process.

ACKNOWLEDGMENT

The authors would like to thank the entire reliability team

at Infineon for their contributions to these studies. Furtheron,

we would like to thank Mr. Thomas Puaschitz for the friendly

support regarding the RF measurements.

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