Quantum Voltage Comparator for 0.07 µm CMOS Flash A/D Converters

Jincheol Yoo, Kyusun Choi, and Jahan GhaznaviDepartment of Computer Science & Engineering

The Pennsylvania State UniversityUniversity Park, PA 16802

{jyoo, kyusun, ghaznavi}@cse.psu.edu

Abstract

This paper presents a new voltage comparator designcalled Quantum Voltage (QV) comparator for the next gen-eration deep sub-micron low voltage CMOS flash A/D con-verter (ADC). Unlike the traditional differential voltagecomparators designed to minimize input-offset voltage er-ror due to the mismatches in a differential transistor pair,the QV comparators are designed to optimize the input-offset voltages by systematically and uniformly varying thetransistor sizes of the differential transistor pair. The QVcomparators allow very small voltage comparison, com-plete elimination of resistor ladder circuit, and dramaticimprovement of linearity in an ADC.

1. Introduction

One of the major problems in the Threshold InverterQuantization (TIQ) flash ADC [4] is a noise susceptibilityof the TIQ comparator. Because the TIQ comparator, whichconsists of two cascaded inverters, has a single-ended input,the comparator is very sensitive to power supply noise. Inaddition to the power supply voltage variation, temperaturevariation makes the DNL and the INL increased in the TIQflash ADC.

To overcome these problems, we propose a new com-parator called Quantum Voltage (QV) comparator. The QVcomparator does not use a resistor ladder circuit. The QVcomparator has been devised from the differential compara-tor [3] with the application of the TIQ comparator conceptto generate the internal reference voltages. A 0.7 V 6-bitflash ADC and an 8-bit flash ADC have been designed with0.07 µm CMOS technology [1] to implement the QV com-parator.

2. The QV comparator

The main idea of the TIQ comparator is that the refer-ence voltage is internally fixed by the transistor size of theinverter [2]. Hence, no additional circuits are needed for

the reference voltage. This idea has been applied to a dif-ferential comparator. The schematic diagram and voltagetransfer characteristic (VTC) of the proposed QV compara-tor are shown in Figure 1(a).

In conventional differential comparators, the transistorsizes are standardized and input Va is taken from a Vrefgenerated by a resistor ladder circuit. Therefore, all 2n − 1comparators for n-bit flash ADC are identical. On the otherhand, the QV comparator has different transistor sizes oftransistorsQ3 andQ4, while transistorQ1 andQ2 are iden-tical. With this intentional mismatch in the differential pair,the reference voltages can be internally created to the com-parators. On the account of this mismatch, 2n − 1 differentsizes of QV comparators are needed for the flash ADC im-plementation. By systematic increasing and decreasing sizeof transistors Q3 and Q4, each of the 2n − 1 comparatorshas a different reference voltage. Figure 1(b) shows an 8-bitflash ADC layout using QV comparators. One may noticethat the differential pair’s transistor sizes are systematicallyincreasing and decreasing.

3. Simulation results and comparisons

For a 0.7 V power supply voltage, the 6-bit and the 8-bitADC simulation results are shown in Table 1. The ADCswith the QV comparators show lower sampling rates, lowerpower consumption, and lower noise sensitivity than theADCs with the TIQ comparators.

3.1. Power consumption comparisons

The power dissipation in the flash ADC can be signifi-cantly reduced by using the QV comparator. Table 2 shows

Table 1. Simulation results of the QVC ADCADC resolution 6-bit 8-bitCMOS technology 0.07 µm 0.07 µmVDD 0.7 V 0.7 Vsampling rate 2.7 GSPS 2.0 GSPSpower consumption 4.952mW 19.094mWarea 0.029mm2 0.109mm2

VLSB 3.802mV 0.946mVDNL 0.0502 LSB 0.2996 LSBINL 0.0287 LSB 0.1581 LSB

Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI’03) 0-7695-1904-0/03 $17.00 © 2003 IEEE

Table 3. Power supply voltage and temperature variation resultsADC variation min Vm(V ) max Vm(V ) VLSB(V ) DNL (LSB) INL (LSB)TIQ 8-bit default 0.25103569 0.45655458 0.00080913 0.1684 0.1234

0.665 V (-5%) 0.23787332 (-5.2%) 0.42706004 (-6.5%) 0.00074483 (-7.9%) 0.1901 0.79860.735 V (+5%) 0.26318532 (+4.8%) 0.48702675 (+6.7%) 0.00088127 (+8.9%) 0.1416 1.1406−40oC 0.27685383 (+10.3%) 0.42349234 (-7.2%) 0.00057732 (-28.6%) 0.2345 2.128085oC 0.22646139 (-9.8%) 0.49024182 (+7.4%) 0.00103851 (+28.3%) 0.1745 2.9707

QVC 8-bit default 0.23858866 0.47875197 0.00094552 0.2996 0.15810.665 V (-5%) 0.23308409 (-2.3%) 0.47232453 (-1.3%) 0.00094189 (-0.4%) 0.2859 0.38070.735 V (+5%) 0.24406446 (+2.3%) 0.48479614 (+1.3%) 0.00094776 (+0.2%) 0.3066 0.3502−40oC 0.25889330 (+8.5%) 0.45531032 (-4.9%) 0.00077330 (-18.2%) 0.2740 0.450185oC 0.22132918 (-7.2%) 0.49972095 (+4.4%) 0.00109603 (+15.9%) 0.3230 0.4180

Va

Vb Qb

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(a) Schematic and VTC

generator

encoderfat treetwo cascaded

QV comparators

boostergain ‘01’

(b) Layout (c) Comparison summary chart

Figure 1. The quantum voltage (QV) comparator

Table 2. Power consumption analysisADC TIQ 6b QVC 6b TIQ 8b QVC 8bcomparator 10.618 4.446 47.983 18.175gain booster 0.043 0.125 0.083 0.417‘01’ generator 0.088 0.053 0.085 0.064encoder 0.565 0.328 0.731 0.438total 11.314 4.952 48.589 19.094

the power consumption in each circuit of both TIQ flashADC and the QVC flash ADC. The comparator in the QVCflash ADC consumes much less power than the one in theTIQ flash ADC. The QVC flash ADC can save power dis-sipation by 58.1% in the 6-bit and 62.1% in the 8-bit com-pared to the TIQ flash ADC.

3.2. Noise comparisons

The noise degrades both performance and precision ofthe TIQ flash ADC. The proposed QV comparator has beendesigned to reduce these noise problems. To check the noisesusceptibility, power supply voltage variation and temper-ature variation are applied to the QVC flash ADCs. Thesimulation results of these variations are shown in Table 3.

In the Table 3, “default” means a 0.7 V power supplyand a 25oC temperature. Both the TIQ comparator and theQV comparator were designed with these default parame-ters. Each percentage shows the difference from the de-fault value. The QV comparator shows that the variationin power supply voltage and temperature are much smallerthan the TIQ comparator. The QV comparator’s linearity(DNL and INL) is less than 0.5 LSB, however, the linearityof the TIQ comparator is much larger than 0.5 LSB eventhough its default DNL and INL are much smaller thanthose of the QV comparator. Therefore, the QV compara-

tor is more useful in low noise applications than the TIQcomparator.

4. Conclusion

The new QV comparator has been designed and simu-lated to verify the low voltage operation. Both the 6-bitQVC flash ADC and the 8-bit QVC flash ADC are correctlyoperating with high speed and low power consumption. Thesimulation results with a 0.7 V power supply shows that theQV comparator has a great advantage in power consump-tion and noise rejection. Figure 1(c) shows the summarychart, comparing the QVC flash ADC with the TIQ flashADC. The QV comparators enables a flash ADC to achievedramatic linearity improvement and large power saving.

5. Acknowledgment

The authors wish to thank the BPTM which is providedby the Device Group at UC Berkeley for offering the 0.07µm SPICE model.

References

[1] BPTM. 0.07 µm SPICE model cards. http://www-device.eecs.berkeley.edu/ p̃tm/70nm nominal.txt, 2001.

[2] D. Lee, J. Yoo, and K. Choi, “Design Method and Automa-tion of Comparator Generation for Flash A/D Converter,” InISQED, pp. 138–142, 2002.

[3] C. Mead, “Analog VLSI and Neural Systems,” Addison-Wesley, Reading, Mass, 1989.

[4] J. Yoo, D. Lee, K. Choi, and A. Tangel, “Future-Ready Ul-trafast 8Bit CMOS ADC for System-on-Chip Applications,”In ASIC/SOC Conference, pp. 455–459, 2001.

Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI’03) 0-7695-1904-0/03 $17.00 © 2003 IEEE