A 10.6μm x 10.6μm CMOS SPAD with Integrated Readout

Khandaker A. Al Mamun, Mohammad Habib Ullah Habib, David Bishai, Nicole McFarlane

Department of Electrical Engineering and Computer Science, The University of Tennessee, Knoxville, TN, USA,

kmamun@utk.edu

Abstract—Single photon avalanche diodes (SPAD) are sensitive optical sensing tools. Incoming photons trigger avalanche events resulting in large device currents. In this paper, we show experimental results for a 10.6 μm x 10.6 μm perimeter gated SPAD with integrated readout circuitry in 0.5 μm 2 poly, 3 metal standard CMOS process. The dark count rate demonstrates a functional relationship with the gate and the excess bias voltage. A compact readout topology is used which takes advantage of the Miller effect to reduce the readout area footprint, thus increasing the pixel fill factor.

I. INTRODUCTION Temporal weak optical signal detection is challenging as it

requires highly efficient sensor circuitry. Avalanche diodes are typically used to detect such temporal decaying signals. When a reverse voltage greater than the reverse breakdown voltage is applied across an avalanche diode, a high electric field results across the p-n junction which accelerates electron-hole pairs near the junction. Any impinging photons or, thermally generated electron-hole pairs, at the junction can generate multiple electron-hole pairs through collision with neighboring atoms, triggering an avalanche event. A single photon avalanche diode (SPAD) is a solid state device that uses a controlled mechanism to trigger an avalanche event during a single photon impact. As the trigger instance is an indication of photon impact at the junction, SPADs can precisely detect the arrival time of a single photon. Thus a SPAD sensor is capable of sensing very weak optical signals, and thus finds numerous applications in areas such as fluorescence imaging, astronomy, biochemiluminescence application and in vision systems [1].

An avalanche event results in a large device current which is potentially harmful for a device and could destroy the device physical structure if the avalanche current is not quickly quenched. During an avalanche event the diode enters into a state where it is unable to detect any further photons. To make the device ready for the next photon impact, the avalanche event needs to be quenched. A quenching event lowers the diode reverse bias voltage below the breakdown voltage and thus inhibits the avalanche event. By re-applying

the breakdown voltage across the device, the device gets ready to trigger a new avalanche event.

One of the major issues of SPAD sensors that is unavoidable in standard CMOS process is the premature breakdown at edges [2]. Due to the strong electric field at the junction edges, the junction edges are susceptible to early breakdown compared to the lateral regions. Premature breakdown reduces the device breakdown voltage and thus decreases the detector sensitivity. In literature, several sensor architectures based on shallow trench isolation and avalanche junction buried inside n-well regions have been proposed to reduce the early perimeter breakdown and increase the breakdown voltage to get increased photon detection efficiency [3-4]. One alternative way to accomplished this is the implementation of guard rings in the device. As in the standard n-well process it is difficult to realize a guard ring, another alternative way is to employ the lateral diffusion regions around the edges which neutralize the strong electric field and thereby reduce the early breakdown [5]. Dandin et al. proposed a novel technique based on perimeter polysilicon gate to reduce the early breakdown event [6]. Application of a reverse gate potential forms a depletion region at the perimeter region which can reduce the strong electric potential build up at the edges and effectively reduces the probability of premature breakdown. It has been proven that perimeter gate works best compared to the guard ring in suppressing the early breakdown in SPAD [2].

Afterpulsing in avalanche diodes is one of the major causes which reduce the sensor detection limit. Afterpulsing is a phenomenon which occurs when an avalanche event is not fully quenched and the trapped charges retrigger a subsequent avalanche event [6]. This phenomenon therefore introduces errors in correlating incident light to sensor output. To reduce afterpulsing effects in a SPAD, a time delay between the quenching and resetting event is required. Typical readout delay blocks require large capacitors and resistors. However it is well known that resistors and capacitors in integrated circuits could occupy substantial chip real estate. Thus, for a Lab-on-a-chip or portable application, a SPAD array must have small device footprint with a high fill factor [7-8]. A compact readout is thus necessary for those applications.

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In this paper, a perimeter gated SPAD is fabricated with integrated readout. As guard ring implementation is difficult in the fabrication process used for SPADs, only perimeter gate was provided in the SPAD to reduce the device premature breakdown. The readout topology also takes advantage of the miller effect to relax the size of large capacitors in the delay block. The paper is outlined as follows. Section II presents the design of the SPAD diode and readout unit, and operation of readout circuit. Experimental results of the SPAD dark count rate, functional dependencies of the SPAD count rates on excess bias and gate voltages, breakdown voltage dependencies on the gate voltage are discussed in Section III and the conclusion is given in section IV.

II. CIRCUIT OPERATION A. SPAD and Readout Design The SPAD shown in Figure 1 was designed in 3 metal 2 poly 0.5µm standard CMOS process. The SPAD is formed from a p+/nwell diode. A polysilicon layer has been implemented around the perimeter of the junction which acts as the gate of the device. Perimeter gates have been successfully implemented previously to reduce the SPAD dark count rate [4]. To reduce the contact resistance, distributed vias are placed at the contacts on the active regions and at the poly contact. A quenching resistor, realized by biasing a transistor in triode region, was used in series with the SPAD. The cathode of the fabricated SPAD was connected to the input of the readout unit. A parasitic diode is formed between the cathode and the substrate. However, as the p+ active region (anode) has been kept at a much higher potential (-10.5V) compared to the substrate (0V), the p+/nwell diode has a reverse bias voltage above the breakdown potential and the parasitic diode has a very low reverse bias potential (~5V). The parasitic diode hence does not hamper the activity of the SPAD. The readout unit consists of a comparator, quenching and reset transistors, inverters and a delay unit. The comparator is used to compare the analog signal with a predetermined threshold voltage, and generates a trigger pulse for the quenching unit. The quenching logic unit, delay unit and the reset unit work synchronously once a SPAD triggers upon arrival of a photon or thermally generated event. B. Readout operation A reverse bias voltage close to the SPAD breakdown voltage was applied across the SPAD. The breakdown voltage of the SPAD was calculated from the current voltage characteristic of the SPAD and found to be -13.76V for an applied gate voltage of zero volts (Figure 6). Once a triggering event occurs, the series passive resistor immediately starts quenching the event as the large avalanche current flows through the resistor. The analog voltage was compared with a predetermined voltage level, 2.5V, set at the comparator input. A two stage operational amplifier was used for a comparator. If the analog voltage goes below the threshold level, an output pulse generates which triggers the active

quenching transistor. The transistor provides a low resistive path to ground and quenches the avalanche event by reducing the reverse voltage across the SPAD. The delay unit provides the delay required between the quenching and reset pulse. Delay between the quench and reset pulse is must as without the dead time after- pulsing events can trigger. A reset pulse is required to turn on the SPAD to detect the next triggering event. For the delay unit a large capacitor and resistor is required to generate a millisecond time delay. To realize the delay unit, a high gain cascaded common source amplifier was used with a feedback capacitor. The capacitance of the unit is multiplied by the two stage cascaded common source amplifier gain which relaxes the need for a large valued capacitor in the circuit. The amplifier gain is approximately 1000 or 60dB. The reset transistor is designed to have large dimensions (twenty times the quenching transistor) so that while the triggering pulse is sensed, it can supply a large current to charge the cathode and thereby pull up the cathode potential. Once the cathode potential rises above the comparator threshold, the quenching transistor turns off after a certain amount of delay time, which turns off the reset unit. After the delay, the SPAD is ready for detecting a new incoming photon. The total delay is given by twice times the

Figure 2. Chip Photomicrograph of chip on left showing SPADs with integrated readout and a single SPAD on the right.

Figure 1. Cross section view of the perimeter gated SPAD.

delay unit time plus twice times the inverter delay and the delay caused by the comparator and SPAD capacitor discharge time. Thus there is an inherent maximum count rate which is limited by the SPAD and the readout structure implemented. However because the interest is in low light level applications such as fluorescence, decreasing the dark count rate and afterpulsing effects are of paramount importance.

III. RESULTS AND DISCUSSION Figure 1 shows the cross sectional view of the SPAD used in this work. A 10.6μm x 10.6μm p+/nwell polysilicon gated SPAD is designed for the work. A photomicrograph of the SPADs is shown in Figure 2. Figure 3 shows the complete readout topology with the delay unit. Using the Miller capacitance of a high gain multistage amplifier (10pF), a compact delay unit is implemented which improves the fill factor of the SPAD pixel compared to a delay unit utilizing a passive capacitor. Figure 4 shows the time domain dark count rate for the SPAD pixel. To fully quench the avalanche, a combination of passive (MOSFET in triode) and active quenching is used for the work. Here, in a 0.5ms time frame 21 avalanche events are recorded using a high speed oscilloscope. The Inset shows the zoomed view of the avalanche event. Each avalanche event starts with a sharp transition of voltage from 5V and tapered down due to the discharge of the SPAD capacitance until it reaches to 2.5V, the comparator threshold. After it crosses the threshold, active quenching comes into effect and bypass the discharging path and pulls down the cathode voltage to ground potential. The dead time is controlled by the delay unit of the circuit. The reset transistor rapidly charges the diode capacitor to 5V which is evident from the very low reset rise time. The avalanche event could be triggered by thermal event, radiation or by an incoming photon. As the test has been performed under dark conditions where incoming light is not allowed to reach the p-n junction, the avalanche events recorded are caused by thermally generated electron hole pairs (dark count rate). The dark count rate was calculated from the average of 2 frames each lasting 100ms (10Hz bandwidth). The dark count rate was measured by sweeping the gate voltage from -11V to -20V and also changing the reverse bias voltage across the SPAD from -17.5V to -21V. The DCR ranges from 5 kHz to 95kHz over the entire variation. The excess bias is the difference between the applied reverse bias and the breakdown voltage. Figure 5 shows the dark count rate as a function of applied gate voltages and excess bias. The DCR increases with excess bias while decreases with gate voltage. It is evident from the plot that as the gate voltage increases the perimeter breakdown reduced due to the inhibition of the strong electric field at the edges which improves the DCR. Again, the DCR is also a function of the excess bias voltage. As the excess bias increases the DCR tends to increase.

Changes in the SPAD breakdown voltage for varying gate voltages are shown in Figure 6 and 7. Figure 6 shows the current voltage characteristic under reverse bias conditions for varying gate voltages from 0V to -15V. The breakdown voltage is calculated as the gate voltage where the maximum of the derivative of the I-V characteristic in occurs. The breakdown voltage increases with gate voltage up to a certain limit. The relationship between breakdown voltage and gate voltage is linear before the breakdown voltage reaches the limit -15.4 V (Figure 7). Equation 1 defines the linear model used to fit the breakdown voltage (Vb) vs. gate voltage (Vg) curve in Figure 7 using coefficients with 95% confidence bounds and acceptable goodness of fit (SSE: 0.01594, R-square: 0.9973, Adjusted R-square: 0.9972, RMSE: 0.02823). All parameters used in Equation 1 are in Volts. 0.1646 13.76 1 This equation is valid for applied gate voltages between 0 and 10V. In this range the breakdown voltage is increased from 13.76V to 15.4V. After 10V, the applied gate voltage has no effect on the breakdown voltage. This increase in breakdown voltage is directly correlated to the decrease in dark count rate for increasing gate applied gate voltages.

Figure 4. Avalanche events (Inset: Zoom view of an avalanche events showing passive and active quenching with reset).

Comparator Delay unit

VL

VG

VDD

Cathode

Quenching Transistor

Reset Transistor

Passive Quenching

Resistor

High Gain Amp.

Cap.

CMiller=Cap.(1+|A|)

RDelay input

Delay output

Figure 3. SPAD readout circuitry with the delay block.

IV. CONCLUSION

A perimeter gated SPAD with integrated readout has been implemented in 3 metal, 2 poly 0.5μm commercial CMOS process. The avalanche events were successfully quenched as designed and the functional dependencies of the dark counts with the gate voltage and excess bias have been experimentally verified. The breakdown voltage increases linearly with increasing gate voltage, lowering the dark count rate and eliminating premature breakdown. To increase the fill factor, miller capacitor proves to be useful in reducing the size of large capacitors in the pixel. The applicability of miller capacitance in pixel readout has been verified in this paper which will help increase the pixel fill factor much higher. In this paper we have shown experimental results of an integrated perimeter gated SPAD pixel with readout circuitry. The SPAD structure shown is suitable for lab on chip and other portable applications.

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Figure 7. Breakdown voltage increases with increasing gate voltage.

Figure 6. Effect of gate voltage on the reverse bias current-voltage characteristic.

Figure 5. Dark count rate as a function of excess bias and gate voltage.