A 1.2 mW 67.5 dB SQDR VCO-Based Σ∆ ADCwith Non-linearity Cancellation Technique

Rohit Yadav and Nan SunDepartment of Electrical and Computer Engineering

University of Texas at Austin, TX 78712, USAEmail: rohityadav@utexas.edu, nansun@mail.utexas.edu

Abstract—Shorter technology enable us to create higher speedoscillators which can provide better resolution in time domain.Therefore, a simple ADC using voltage (or current) controlledoscillator (VCO) and a counter can be implemented using thisapproach. Conceptually, the operation order in this ADC issimilar to a conventional Σ∆ modulator. The CCO integratesfrequency to produce output in the form of phase. And thenumber of stages in the CCO determines the quantization levels(or phase resolution). The difference of quantized phase outputproduces a frequency proportional to the input signal. Therefore,unlike, a conventional Σ∆ modulator no feedback is requiredfor a first order noise shaping. In order to achieve a low powerfor moderate performance two key techniques have been used:a) a cross-coupled voltage to current (V/I) converter to achievenon-linearity cancellation (mainly 3rd-order harmonic), and b)a stack structure to share current between V/I converter andCCO to reduce power. This ADC has been simulated usingmodels of typical 130nm CMOS technology. In SPICE simulation,SQDR/SFDR of 67.5 dB/71 dB is achieved over a total signalbandwidth of 5 MHz for an input swing of 300mV (Vpp) fortypical corner at room temperature. The analog blocks consumeda total of 96.5µW from a regulated 1.2V supply, whereas, thedigital blocks consumed an estimated power of 1.1 mW. Since,the major circuit blocks are digital in nature, the presented circuitis highly amenable with technology scaling.

I. INTRODUCTION

Sigma-Delta (Σ∆) modulator based ADCs provide highresolution for low input signal bandwidth. Fig. 1(a) showsa basic continuous-time (CT ) Σ∆ ADC architecture whereinternal low pass filter perform the anti-aliasing filtering task,and thus relaxes analog filtering constraints and saves a con-siderable amount of power and the area [1]. Conventionally,Σ∆ architecture implementation require several high precisionblocks such as high accuracy analog integrators, low offsetanalog comparators, high-linearity feedback DAC, low noiseand low impedance reference voltages, and a low-jitter clock.The design of these circuits progressively becomes a chal-lenging task as technology scales, due to low supply voltage,small transistor intrinsic gain, increased device leakages, andincreased 1/f noise [2]–[4].

One alternative approach to design a Σ∆ ADC is basedon voltage (or current) controlled oscillator (V CO) integratorand quantizer. Fig. 1(b) shows the block diagram of a basicCT Σ∆ ADC based on V CO [5], [6]. This design provides afirst order noise shaping and utilizes mainly blocks which aredigital in nature, and thus, avoids any requirement to use theearlier mentioned high-precision analog blocks proving itself

to be highly amenable to technology scaling. Unfortunately,the V CO suffers from severe non-linearity problem, thuslimits the performance of such designs. There have beenseveral attempts earlier to circumvent the non-linearity issuesassociated with the V CO. In one published work, V CO-based Σ∆ modulator is used as the last stage of an otherwiseconventional analog Σ∆ modulator [7]. Since, this approachagain requires all the high performance analog blocks provingit to be scaling unfriendly. In another work, digital backgroundcorrection is used to cancel V CO non-linearity [4]. This workmainly use digital blocks but requires a high precision op-amp and high voltage devices to implement the V/I converter.Therefore, it not amenable to scaling. Additionally, it requireslarge number of digital blocks for calibration making it powerhungry and area consuming.

In this paper a CCO-based Σ∆ ADC is implemented

H(s)

DAC

ClkN

NDOUT

VCO

Clk

1-z

First OrderDifference

DOUT

QuantizerNN

(a)

(b)

VIN -1

LPF Quantizer

VIN

Fig. 1. Block diagram of a noise-shaped Σ∆ ADC.

versus a V CO to achieve better linearity [8], [9]. Therefore,design of a highly linear V/I converter is a critical partin this design. In order to achieve this goal a fully differ-ential structure is adopted to cancel even-order harmonics.Additionally, a well known technique of odd-order non-linearterms cancellation is implemented using two different sizePMOS differential pairs crossly-coupled to suppress mainly3rd harmonics [10]. Further, a stacked structure with V/Iconverter and the CCO sharing currents has been chosen tolower the power consumption at the expense of lower inputsignal swing. However, in applications with large input signalswing this can be used as second stage ADC in a two-stageADC architecture [11]. Such architecture taps MSB usingconventional ADC architecture and a lower residue of inputvoltage is fed to the second stage VCO. In this circuit design,

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no high voltage devices have been used and all the blocks usedare digital in nature, thus scalable, except the V/I converter.This paper consists of two main sections: section II containsdetailed implementation of the full CCO-based ADC circuitfollowed by the simulation results in section III and conclusionin section IV.

II. CIRCUIT IMPLEMENTATION AND OPERATION

A. Current Controlled Oscillator Based Quantizer Operation

Fig. 2(b) shows the ADC implemented in this work. Theoperation flow is this circuit is similar to a conventional Σ∆modulator but does not require a feedback path to achievea first order noise shaping. Higher order noise shaping canbe obtained by using conventional architecture of Σ∆ usinga DAC in feedback [2], [7]. However, the linearity in sucharchitectures is dominated by DAC and requires conventionalanalog blocks. Here in this open loop design, the CCO inte-grates frequency to produce output in the form of phase. Andthe number of stages in the CCO determines the quantizationlevels (or phase resolution) [2], [7], [8]. The difference ofphase output produces a frequency proportional to the inputsignal. This implementation is fully differential to ensurecomplete even order harmonic cancellation. As shown, in theleft, a differential analog voltage VIN is applied to a V/Iconverter (Fig. 2(a), explained in section II-C), which feedstwo fully differential CCOs (Fig. 2(c)). The circuitry followedby CCO implements the quantized estimate of the frequencychange by counting the number of edges traveled within eachperiod of the reference clock. The clocked comparator actas quantizer by capturing the output phase of the CCO,and at the same edge DFFs load the previous state phaseoutput bits. The number of 1s after the XOR operation, afirst order difference operation in this case, on the currentphase output from comparator and previous state output fromDFF represents the estimate of the edges traversed in a singlereference clock cycle. Following the XOR, the numbers of1s are added for both branches. And finally, the outputs ofthe adders from both branches are subtracted to obtain atrue digital representation of the input signal VIN . It shouldbe noticed that in this given topology, the number of edgestraveled in a single reference clock period should not exceedthe number of V CO stages, otherwise overflow may occur[2]. With additional digital circuitry phase wrapping can bemanaged but may lead to a complicated structure.

B. Frequency Domain Model of the CCO-based QuantizerOperation

Fig. 3 shows an equivalent frequency domain model ofthe implemented ADC described in section II-A. The non-linear voltage to frequency transfer characteristic from V/Iconverter and CCO can be modeled as Kv . Since, the CCOperform the operation of integrating the frequency to producephase as output, therefore, it can be approximately modeledas an integrator. Additionally, contribution from thermal and1/f noise in the V/I converter and CCO can be modeledas nV CO. A detailed analysis of the phase noise contribution

iA(t)

11-Stage Ring Oscillator

1x

4x4x1x

In+In-Out+ Out-

(a)

(c)

(d)

I2__2

I2__2

M1VIN+

M2M3 M4

AB

iA(t)

I1__2

I1__2

iB(t)

VIN-

R1

R2

(b)

DOUT

iA(t)

iB(t)

GmVIN+

VIN- Clk

+__

2N

D Q

DQ

N

N

N

2N

2N

2N

2N

2N

2N

2N

2N

+

Fig. 2. (a) Cross-coupled V/I converter, (b) complete implemented Σ∆circuit, (c) 11-stage fully differential ring oscillator, and (d) fully differentialinverter.

from various sources in a ring oscillator circuit is availablein [12]. In addition, the sampler, clocked comparator in ourdesign, adds white quantization noise, qsamp. Finally, thefirst order difference operation performed by the differentiatorachieves a first order noise shaping. A higher order noise-shaping can be achieved by using this block if implementedwith feedback [2].

V/I Conv + CCO Non-linearity

Kv

VCO Integrator

2___s

nvco

Sampler

qsamp

1-z

Differentiator

VIN DOUT-1

Frequency

-20dB/dec

nvco

qsam

p white noise

Frequency

nout

First Order Noise Shaping

Frequency

20dB/dec

Fig. 3. Frequency domain model of the VCO-based ADC.

C. Harmonic Cancellation in V/I Converter

A V/I converter or trans-conductors are interchangeablyused to represent the circuits that convert the input appliedvoltages into output current. Fig. 2(a) shows a cross-coupledfully differential V/I converter circuit utilized in the imple-mented ADC. The transfer function i0 = f(vi), for this V/I

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converter can be expanded using Taylor series in the followingform.

i0 = a1vi + a3v3i + a5v

5i + a7v

7i + ..... (1)

where vi and io are the input voltage and output current respec-tively, and the ai coefficients are specific to an implementation.The ai coefficients for the presented V/I converter can beunderstood by considering the total current added at node A.At a given instant of time the small signal current at A, iA(t)for a given differential signal 2vi(t), is the sum of small signalcurrent through M1 and M4. Using Eq. (1).

iM1(t) = a1,M1vi + a3,M1v3i + a5,M1v

5i + a7,M1v

7i + .....

(2a)

iM4(t) = −a1,M4vi − a3,M4v3i − a5,M1v

5i − a7,M1v

7i + .....

(2b)

iA(t) = (a1,M1 − a1,M4)vi + (a3,M1 − a3,M4)v3i

+ (a5,M1 − a5,M4)v5i + .. (2c)

In order to achieve high linearity, a1,M4 � a1,M1 to preservethe input signal but a3,M4 ≈ a3,M1, a5,M4 ≈ a5,M4 andso on for higher-order harmonic cancellation. In a practicalcircuit, 3rd and 5th order harmonic cancellation are enough.According to [10], the relative values of ai coefficients areessentially dependent on the ratio of the current, input signalMOS sizes and the feedback resistances. If the ratios aredefined as:

I2I1

= p,β2β1

= q,R1

R1= x (3)

the output current in Eq. 2 can be rewritten in following form:

i0 = ρ[p, q, x]vi + φ[p, q, x]v3i + ω[p, q, x]v5i + ... (4)

where, ai coefficients are now represented as function ofp, q, and x. The cross-coupled V/I converter [Fig. 2(a)] insimulation results achieves a transconductance linearity of 72dB with ratio of p = 0.15, q = 0.25 and x = 4. Whereas,a reference V/I converter simulated for comparison withoutM3 −M4 pair reaches a maximum of only 65 dB. In con-ventional approach 6dB improvement would require 4x powerand area. The impact of this additional linearity is discussedin Sec. III. The I1 and I2 current sources are implementedusing cascode topology. The PMOS implementation of thistrans-conductor provides another advantage in terms of lowerflicker noise contribution compared to NMOS implemented in[10].

The design of this block involved several tradeoffs in-cluding the input voltage swing, trans-conductance, powerconsumption, and the noise. The major non-idealities thatare considered carefully in designing this circuit are: thermaland flicker noise, mismatches and parasitic effects. The noisegenerated in the input pairs, the tail current sources, the activeload, and the degeneration resistors contribute to the totalthermal output noise current of the V/I converter. In thesubmicron process, the flicker noise also has a significantimpact in the frequency range of interest. Therefore, for theinput transistor pairs lch = 4 times lmin is used. Increased

device sizes help in reducing the flicker noise besides reducingthe channel length modulation and ensuring better devicematching. Additionally, while choosing the values it is ensuredthat the reactive components do not become large in thefrequency of interest. Since, in the implemented circuit V/Iconverter and ring oscillator are stacked (Fig. 2(a)) to share thecurrent, makes the design optimization task more challenging.

D. Fully Differential Ring Oscillator

Fig. 2(c) shows the circuit of an 11-stage fully differentialring oscillator used as CCO. A single differential inverter usedin the ring oscillator is shown in Fig. 2(d). The 1x representsthe minimum sized inverter with no skew. The 4x invertersare four times wider than the minimum size inverter. Thering oscillator length optimization involves several trades-offsin the stacked structure as chosen here. For a chosen V/Iconverter circuit, minimum required input swing and powerconsumption limit sets the maximum allowed voltage at theoutput node. And for a given length oscillator, the supply nodevoltage requirement goes high as the input current increases.And the input current for a fixed length oscillator determinesthe current to frequency transfer magnitude which eventuallydetermine the SQDR. Therefore, several iterations may berequired to meet V/I converter specs and ring oscillator todecide the optimum length and inverter sizes for the mostoptimum performance. The length of ring oscillator plays yetanother crucial role in deciding the frequency for a givencurrent. This involves the input signal swing and bandwidthmaximization, and overall ADC SNR and SQDR.

III. SIMULATION RESULTS

In order to analyze the impact of non-linearity cancellationon the overall performance of the ADC, two circuits havebeen implemented using different V/I converters. In caseA, the ADC utilizes a reference V/I converter withoutM3−M4 differential pair and case B uses the cross-coupleddifferential V/I converter (Fig. 2(a)). The transient noise hasbeen turned off to analyze the effect of odd-order cancellationeffect. The transient noise will be shaped to first order inboth the cases. FFT plots for case A and B are shown inFig. 4 for a single tone input signal at 1.37 MHz. In caseA, SQDR/SFDR equal to 61.8 dB/62.8 dB is achieved (Fig.4(a)). This implies the third-order harmonic dominates theSQDR performance of the circuit in case A. However incase B, the SQDR/SFDR of 67.5 dB/71 dB is obtained. Asvisible from Fig. 4(b), the third-order harmonic lies within thequantization noise. Thus, an overall 5.7 dB of improvementin SQDR by using cross-coupled V/I converter at the cost of15% additional analog power and an approximate 4x area forthe resistor and 25% MOS area.

The results presented here have been simulated intypical 0.13-µm CMOS technology with two separate 1.2Vsupplies for analog and digital blocks. The analog blockincludes bias circuits, V/I converter and CCO, and digitalblocks consist of clock, comparator, CCO buffers, andother digital circuits. Table I summarizes the simulation

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results. The conversion efficiency of this circuit is limitedby digital circuits. Thus, it will improve as technology scales.

106

107

108

−100

−80

−60

−40

−20

0

-62.83dBFS@4.11MHz3rd Harmonic

0dBFS@f =1.37MHz0

(a)

20dB/dec

BW=5MHz

-62.8

FFT Plots

Frequency

Mag

nitu

de(d

BFS

)

106

107

108

−100

−80

−60

−40

−20

0

-71.2dBFS@4.11MHz3rd Harmonic

(f = 5MHz)c

0dBFS@f =1.37MHz0

(b)

20dB/dec

BW=5MHz

-71

Frequency

Mag

nitu

de(d

BFS

)

Fig. 4. (a) FFT plot of ADC output with V/I converter having no non-linearity cancellation, (b) FFT plot of ADC output with V/I converter havingnon-linearity cancellation.

TABLE IRESULTS SUMMARY

Specification ValueTechnology 0.13-µm CMOSSupply Voltage 1.2 VInput Signal Swing (Vp−p) 300 mVInput Bandwidth 5 MHzSampling Frequency 1.6 GHzPeak SFDR 71 dBPeak SQDR 67.5 dBAnalog Power 96.5 µWDigital Power 1.1 mWTotal Power 1.2 mW

IV. CONCLUSION

In this work we have demonstrated a continuous-timeCCO-based ADC in 0.13-µm CMOS technology. Twoimportant techniques are incorporated: a V/I converter withtwo different size PMOS differential pairs crossly-coupledto achieve non-linearity cancellation, and a stack structure

with V/I converter and the CCO sharing currents to achievelow power consumption. In this design, no high voltagedevice have been used and all the blocks used are digital innature thus scalable except the V/I converter. This prototypeADC achieves a peak SQDR/SFDR of 67.5 dB/71 dBover a bandwidth of 5 MHz, and dissipate overall powerof only 1.2 mW from a 1.2V supply. This CCO basedarchitecture provides competitive performance for the givenpower compared to the classical multi-bit quantizer. Thus,this scaling friendly architecture may enable us to designhigh performance continuous time (CT ) ADC in the futureadvanced technology nodes.

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