� Abstract—The paper deals with a design of the 12-bit sigma

delta (��) modulator using switched capacitor technique (SC). It is a part of the system for vibration sensor output processing. Processing system consists of pre-amplifier, delta-sigma modulator and decimation digital filter. Detailed description of design process of the �� modulator is described in article. The design process starts by parameter requirements determination, continuing by structure proposal, design method and coefficients selection, selecting of compensation methods and concluding by design on the chip. ONSemi I2T100 700 nm CMOS technology was used for design. The value of SNDR = 81.1 dB (ENOB = 13.2 bits) was achieved.

Keywords—SC technique, CDS technique, MATLAB, opera-tional amplifier, �� modulator

I. INTRODUCTION ETECTION of the vibration produced by rotating machines e.g. motors is very important to avoid its damage or power loss. The mechanical problem can be

recognized well in advance by continuous vibration processing. Source of the vibration can be founded out by spectral analysis of the vibration sensor output. The bandwidth of 5 kHz is sufficient for common vibration sensor used for 50/60 Hz motors [1]. Unlikely, the motors perform source of the interference especially when are driven by frequency changers.

Manuscript received February 11, 2013. This work was supported in part by the SIX project; the registration number CZ.1.05/2.1.00/03.0072, the operational program Research and Development for Innovation and has been supported by Czech Science Foundation as project 102/11/1379 and by project: “Prospective applications of new sensor technologies and circuits for processing of sensor signals”, No. FEKT-S-11-16. Cadence software was used with support through the Cadence Academic Network.

M. Pavlik is with the Department of microelectronics, Brno University of technology, Technická 10, Brno 616 00, Czech Republic, e-mail: pavlik@feec.vutbr.cz, tel: +420541146167, fax: +420541146298.

V. Kledrowetz is with the Department of microelectronics, Brno University of technology, Technická 10, Brno 616 00, Czech Republic, e-mail: kledrowetz@phd.feec.vutbr.cz

J.Háze is with the Department of microelectronics, Brno University of technology, Technická 10, Brno 616 00, Czech Republic, e-mail: haze@feec.vutbr.cz

M.Pristach is with the Department of microelectronics, Brno University of technology, Technická 10, Brno 616 00, Czech Republic, e-mail: xprist00@stud.feec.vutbr.cz

R.Prokop is with the Department of microelectronics, Brno University of technology, Technická 10, Brno 616 00, Czech Republic, e-mail: prokop@feec.vutbr.cz

L. Fujcik is with the Department of microelectronics, Brno University of technology, Technická 10, Brno 616 00, Czech Republic, e-mail: fujci@feec.vutbr.cz

F. Khateb is with the Department of microelectronics, Brno University of technology, Technická 10, Brno 616 00, Czech Republic, e-mail: khateb@feec.vutbr.cz

The system was designed to process output signal of the vibration sensor in device ATW08 produced by Viditech Ltd. [17]. Vibration sensor in ATW08 is based on CCLD accelerometer with output sensitivity of 50 mV/g. Bandwidth of the sensor is 10 kHz, nevertheless according to [1] and requirement from Viditech, the processed bandwidth is 5 kHz.

The integration or noise-shaping converters should be used. There are many structures and topologies of integration or noise-shaping converters. We used the second order delta-sigma (��) modulator accordingly to our previous work [1]. Also the cascaded integrator with distributed input and feedback structure (CIDIDF) [6], [8] was used. The modulator was realized using switched capacitor (SC) technique with correlated double sampling (CDS) compensation method.

II. DEFINITION OF CONVERTER PARAMETERS Required parameters of the �� modulator are based on processing system requirements. The fundamental requirement is to reach at least 12 bit ENOB of the converter. It approximately matches with resolution of other commercial systems e.g. ADXL344 produced by Analog Devices.

The CIDIDF structure (Fig. 1) was chosen for design as mentioned above. Zero coefficients b2 and b3 were chosen to simplify circuit implementation. Even if, it increases modulator stability it decreases obtainable SNR in the same way. Nevertheless, theoretical value of the SNR can be up to 104 dB. The STF and NTF become

1)2()()()(

21122222

211

�������

ccacacazz

ccbzXzYzSTF , (1)

� 1)2(

1)()()(

21122222

2

�����

���

ccacacazz

zzEzYzNTF , (2)

where X(z) is input signal, Y(z) is output signal and E(z) represents quantization noise source of the internal DAC.

TABLE I SPECIFIED MODULATOR PARAMETERS

Parameter Symbol Value Unit

Effective number of bits ENOB 12 - Input signal bandwidth fBW 5 kHz Sampling frequency fs 2 MHz Oversampling ratio OSR 200 - Supply voltage VSupply 5 V Common mode voltage VCM 2,5 V Input signal amplitude vINmax 2 V

SC �� Converter for Vibration Sensor Processing System

Michal Pavlík, Vilém Kledrowetz, Ji�í Háze, Marián Pristach, Roman Prokop, Lukáš Fujcik, and Fabian Khateb

D

392978-1-4799-0404-4/13/$31.00 ©2013 IEEE TSP 2013

Fig. 1. CIDIDF structure of the second order �� modulator

There are some approaches to calculate rest of coefficients

[7]-[9]. However, there is no exact method that takes into account real behavior of the circuit on transistor level. Nevertheless, all poles of the NTF must lie in unit circle. Stability of the modulator is satisfied as much as close to central point of the unit circle the poles lay. Coefficients were chosen as was mentioned in [8], in very first approach.

III. BASIC BLOCKS DESIGN REQUIREMENTS Required value of SNDR is important condition that affects

parameters of modulator’s basic blocks. The most crucial block of the �� modulator is first integrator in cascade [2]. It consists of operational amplifier (OA or opamp) and analog switches.

A. Noise and offset of the operational amplifier The offset of the opamp can be typically up to millivolts.

It’s much more than one LBS of the 12bit converter with 5 V reference. Even if the offset voltage can be eliminated by digital part of the converter, offset voltage is commonly time dependent. Due to this fact, the periodical calibration should be processed. It should causes periodical loses of the output signal that cannot be acceptable for integrator. Direct offset and noise compensation in analog part of circuit was used. When suppose zero noise of switches, it is possible to describe modulator output (Fig. 2a)

)(

111)(

11)( 1

01 zv

zCCzX

zzY n

SCC

I

S ���

���

��

���

�� ��, (3)

where vn is voltage vnoise + voffset. Many techniques for offset and noise suppression exist. The most important, described in [8]-[12], are:

- chopper stabilization (CHS), - auto-zeroing (AZ), - correlated double sampling (CDS).

Integrator that uses CDS technique for offset and noise

suppression is shown in Fig. 2b). The capacitor C0 is charged to voltage vnoise + voffset during the clock phase �2. Next, the integration is performed and voltage vnoise + voffset on capacitor C0 is subtracted during phase �1. Output of the integrator is described by (4).

� ).(1

1

11)(1

1)(

2/1

101

zvz

zCC

zXz

zY

n

SCC

I

S

�

���

���

�

���

���

�

�� (4)

Fig. 2. a) Switched capacitor integrator b) Switched capacitor integrator with CDS compensation method

The voltage asymmetry is completely canceled and 1/f

noise is filtered by 1 – z-1/2 function and considerably attenuated at low frequencies at the output [9]. The value of the compensation capacitor C0 should be same as sampling capacitor CS and must be much higher than input capacity of the opamp.

B. Finite DC gain of the opamp The next equation describes SC integrator transfer function

in ideal case

11

1)()()(

����

zCC

zXzYzSTF

I

S . (5)

The equation (5) is valid only for operation amplifier with endless gain. Value of the pole (p) and zero (o) can be calculated with next equations

01

11

1

ACC

p

I

S�

�� . (6)

���

���

���

�

111

1

0 I

SCC

A

o . (7)

Change of the NTF’s zeros and poles position results in decreasing of SNR. The finite gain of the opamp increases influence on SNR with order of �� modulator [11]. The designed modulator has to have higher gain than A0 � 62 dB. This value depends on used modulator coefficients and desired LSB.

C. Gain bandwidth of the opamp Important issue in SC circuits is settling time �. The settling

time of the described integrator depends directly on the opamp bandwidth.

393

t [µs]

�1

t [µs]

�2

t [µs]

�1d

t [µs]

�2d

Fig. 3. Waveforms of the clock signals

In case of the �� modulator, the settling time is crucial.

Settling time has to be much lower than sampling period TPS. When the condition is not satisfied, the modulator should be unstable [9]. The slew rate (SR) of the opamp must be adequately high to removing all charge from sampling capacitor CS to feedback capacitor CI within half of TPS. In case of the specified sampling frequency, the SR must be higher than SR � 10 V/μs.

D. Compensation of the SC technique nonidealites Dominant nonidealities of the SC technique are clock feed-

through, charge injection, stray capacities, matching of the capacitors, jitter and synchronization error of the clock. Thus, the fully differential circuitry was chosen to minimize these parasites. The circuitry shown in Fig. 2 needs non-overlapped clock signal for proper function. The waveform diagram of the required clock signal is drawn in Fig. 3. There are two fundamental signals �1 and �2 and two derived signals �1d and �2d which are set to log. 0 about 5 ns before its fundamental signals.

IV. VERIFICATION OF MODULATOR BEHAVIOR IN MATLAB Appropriate modulator architecture and realization

technique were chosen in previous chapter. The requirements on the critical devices of the circuitry were also defined. Impact of the device’s (especially opamp) real behavior on the modulator was validated in MATLAB Simulink [2], [9].

Fig. 4. Dependence of the modulator SNDR on the input signal frequency

Fig. 5. Dependence of SNDR on the input signal frequency (optimized coefficients values)

The third harmonic tone is present in ideal modulator

output signal spectrum especially in case of low order modulators (1st and 2nd order). When the modulator parameters are tested with input signal frequency near the bandwidth fin = fBW the third harmonic tone is out of the band and its energy is not taken into calculation of SNDR [2]. The correct approach is testing modulator parameters with input signal frequency of 1/3fBW and/or 1/5fBW (respective with nearest lower frequency). The problem was discussed in few publications [13]-[16].

The third harmonic tone presence is most frequently explained by opamp or switches nonlinearity. However, as mentioned above, the third harmonic tone is present in ideal modulator spectrum. It can be explained that the quantization noise correlates with input signal. The harmonic tones appear when output bitstream stays in log 0 or 1 for considerable number of clock signal periods. The quantization noise than cannot be shaped into high frequencies.

A. Optimization of the Transfer Coefficients The coefficient setup for selected structures CIDIDF was

described in the chapter 2. There is not universal approach how to choose these coefficients. It was experimentally founded that SNDR of the �� modulator depends on NTF coefficients. Coefficients values affect form of the �� modulator output bitstream. It does not stay long time in the H or L level. As a result, the higher harmonic tones are minimized. The heuristic method was used to determine modulator’s coefficients.

Improvement of SNR by 10 dB and minimizing higher harmonics tones was reached. It is obvious by comparing Fig. 4 (SNDR = 73.8 dB) and Fig. 5 (SNDR = 83 dB).

V. DESIGN OF �� MODULATOR ON TRANSISTOR LEVEL The last and most important design phase is design of the

�� modulator at transistor level and finally chip layout of opamp, comparator, DAC, integrator, etc. It is necessary to prove that design on transistor level is correct for whole temperature range and process deviations.

A. Operational amplifier The requirements on opamp were determined in the

previous chapter and they are summarized in Table 2.

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TABLE II PARAMETERS OF THE OPERATIONAL AMPLIFIER

Parameter Symbol Required Real Units

Voltage gain AV > 62 82.5 dB Gain bandwidth GBW > 15 21.6 MHz Phase margin PM - 73.5 ° Offset Voff - 4 mV Slew rate SR 10 18 V/μs Max. output current IOUTmax - 300 μA Power dissipation Pdiss - 4.3 mW Area SCH - 0.092 mm2

Fig. 6. The �� modulator in SC technique and CDS compensation It is fully differential two stage structure opamp. Stability of opamp ensures Miller compensation capacitor and nulling resistor for controlling right half-plane zero. This opamp is used in both integrators and the input circuit, which converted single signal into fully differential.

B. Modulator �� The designed second order �� modulator circuitry is in

Fig. 6. It consists of two integrators, comparator and 1-bit DAC. The ratio of the corresponding capacity CS and CI is determined by modulator coefficients. The compensation capacitor C0 has to be 2.5 pF, which is large enough to suppress offset and opamp noise. Input capacity of the opamp is 0.88 pF. The �� modulator operates with maximum amplitude 2 V of the input signal. It performs voltage swing of 0.5 V to 4.5 V. The DAC reference voltages are VREF+ = 5 V and VREF- = 0 V. Overall size of the �� modulator die is 0.75 mm2.

VI. MEASUREMENT RESULTS OF THE �� MODULATOR When chip has been fabricated, the properties of the

�� modulator were measured. It was necessary to set the same circuit and working conditions as much as possible to eliminate disturbing influences to allow relevant comparisons with simulated structures. Therefore, the measured chip was supplied from lead accumulator and it was galvanic isolated from the �� modulator output stream processing circuit. The precision optocouplers HCPL092J with very low operating current of the transmitter were used for this purpose.

Digital and analog power supply of the modulator chip was also separated. Internal clock derived from the frequency of the external crystal 4 MHz was used for measuring. There is measured power spectral density of the fabricated �� modulator in Fig. 7. Achieved SNDR of the 10 modulators is 81.1 dB on average. Layout of the fabricated �� modulator is shown in Fig.8.

Fig. 7.Measured power spectral density of the second order �� modulator - real chip

Fig. 8 Fabricated �� modulator layout

TABLE II COMPARISON OF SNR RESULTS

Model SNDR [dB]

ENOB[-]

Ideal 104* 16.9 Matlab (include non-idealities) 73.8 11.9 Matlab (optimized coefficients) 83 13.4 Cadence (typical parameters) 82.2 13.3 Cadence (the worst case) 79 12.8 Real chip 81.1 13.2

* it is theoretic SNR in this case

VII. CONCLUSION This paper describes one part of the system for vibration

sensor signal processing �� modulator realized in I2T100 technology. The design is based on the ideal MATLAB Simulink model. Mathematically, using the Z-transform were described partial errors occurring in the circuit of the �� modulator. Based on this knowledge there was created MATLAB model that allow study of the impact of many non-idealities and makes time needed to verify real properties of �� modulator shorter. The paper also analyzed the effects of higher harmonics tones, particularly the third harmonics, which significantly reduces overall SNDR. Coefficients optimizing succeeded in increase the SNDR by almost 10 dB. After fabrication �� modulator has ENOB 13.2. Die size of the modulator is 0.75 mm2 (area of the overall chip is approx. 6.4 mm2).

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