A Unified 3D Device Simulation of Random Dopant, Interface Trap and Work Function Fluctuations on High-κ/Metal Gate Device

Yiming Li*, Hui-Wen Cheng, Yung-Yueh Chiu, Chun-Yen Yiu, and Hsin-Wen Su

Department of Electrical Engineering, National Chiao Tung University,

1001 Ta-Hsueh Road, Hsinchu City, Hsinchu 300, Taiwan *Tel: 886-3-5712121 ext. 52974; Fax: 886-3-5726639; Email: ymli@faculty.nctu.edu.tw

Abstracts

In this work, we for the first time estimate total fluctuation resulting from random dopants (RDs), interface trap (ITs) and work functions (WKs) using experimentally calibrated 3D device simulation on 16-nm-gate high-κ/metal gate devices. The total 3D simulated threshold voltage fluctuation (σVth), induced by the aforementioned random sources simultaneously, is 55.5 mV for NMOS; however, a statistical total sum of these fluctuations is 12.3% overestimation because independence assumption on random variables is invalid owing to strong interactions among RDs, ITs and WKs. Device’s DC/AC and CMOS SRAM circuit fluctuations have similar observation. FinFET-based structure innovation possessing large fluctuation suppression (σVth = 30.2 mV; 45.6% reduction), compared with process efforts on planar one, is further discussed.

Introduction

Random dopant, interface trap and work function on MOS devices were reported [1-9]. Unfortunately, fluctuation induced by all RDs, ITs and WKs on high-κ/metal gate (HKMG) devices have not been examined yet. In this study, for the first time, all RDs, ITs and WKs on device and SRAM’s characteristics are studied and compared with their statistical sum in a unified way by experimentally calibrated 3D quantum-corrected device simulation [1-3]. Statistical sums of σVth, σCG and σSNM are 12.3%, 18.5% and 20% overestimations, respectively, compared with total 3D simulations. For all random sources, 16 nm HKMG bulk FinFET has large fluctuation suppression on σVth (σVth = 30.2 mV; 45.6% reduction), compared with other process efforts on planar one, such as size’s reduction of metal grains and minimize ITs’ density. Structure innovation thus provides a promising way for sub-16-nm HKMG era. Total 3D device simulation with all RDs, ITs and WKs is necessary for characterizing variability in HKMG devices.

Simulation Methodology

Schematic plot of studied 16-nm-gate MOSFET (width: 16 nm) with 4x4 nm2 amorphous-based TiN/HfO2 gate stack and EOT of 0.8 nm is shown in Fig. 1(a), where RDs, ITs and WKs are considered simultaneously. The experimentally validated nominal channel doping concentration is about 1.5x1018 cm-3 [3] and Vth = 250 mV is calibrated following ITRS roadmap for low operating power. For WKs fluctuation [1-2], the TiN gate is composed of a small number of grains, as shown in Fig. 1(b), where WKs of <200> and <111> orientations with green and blue colors are 4.6 and 4.4 eV, according to material properties listed in the table of Fig. 1(b). The generated large gate area (224 nm)2 is partitioned into about 200 sub-regions according to an averaged grain size, where the numbers of <200> and <111> orientations of each sub-region vary from 0 to 16 and the average numbers are 9 and 7, respectively. For RDs fluctuation [3], 1327 dopants are randomly generated in a large cube, in which the equivalent doping concentration is 1.5x1018 cm-3, as shown in Fig. 1(c). The large cube is then partitioned into about 200 sub-cubes, where the number of dopants may vary from 0 to 14, and the average is 6. For ITs fluctuation, we generate 753 acceptor-like traps in a large plane in Fig. 1(d), where ITs’ concentration in the large plane is about 1.5x1012 cm-2 which follows the Poisson distribution experimentally [1,6,7]. The statistically generated large plane is partitioned into many sub-planes, where the number of traps in the sub-planes may vary from 0 to 8 and the average is 4. IT’s energy on each sub-plane is assigned via the distribution of trap density. Completely random sub-cubes / sub-planes / sub-regions with RDs, ITs and WKs are equivalently mapped into device’s channel for coupled device-circuit SRAM simulation, as shown in Figs. 1(e)-(f) [2]. Fluctuations are estimated with all as well as pairwise RDs, ITs and WKs.

5.5.1 IEDM11-107978-1-4577-0505-2/11/$26.00 ©2011 IEEE

Results and Discussion

Fig. 2(a) is the Cumulative probability of Vth of N-MOSFET fluctuated by RDs (red color), ITs (pink color) and WKs (green color), respectively, and by all random sources (i.e., total 3D simulation with considering RDs, ITs and WKs simultaneously; denoted as ALL), where the inset is the scatter plot of Vth,RDs, Vth,ITs and Vth,WKs. The ball-shape-liked distribution shows their statistical independence. For the case of ALL, the line slope differs from other steep lines. The σVth induced by RDs, ITs, WKs, ALL, and statistical sum (SUM) is shown in Fig. 2(b), respectively. Compared with 3D simulation, the SUM of (σ2Vth,RDs+σ2Vth,ITs+σ2Vth,WKs)0.5 is of 12.3% overestimation. Similarly, the 3D simulated σVth of pairwise random sources, such as RDs&ITs, RDs&WKs and ITs&WKs, are smaller than statistically calculated σVth respectively, where the statistically calculated σVth for RDs&ITs, RDs&WKs and ITs&WKs are 50.4, 56.5 and 45.2 mV, respectively, as shown in Fig. 2(c). Warped surface potentials are affected to different extents by remote dipole and coulomb/phonon scatterings induced by RDs, ITs and WKs. These estimations point out the necessity of 3D simulation with overall random sources because it reflects the canceling out effect of fluctuated surface potentials, as shown in Figs. 5(d)-5(d’’), which is beyond the individually even pairwised statistical sum calculations. The definition of error between SUM and ALL for different pairs of random sources and overall randomness is (Statistical sum - 3D simulation)/3D simulation x 100%), where the corresponding errors for RDs&ITs, RDs&WKs, ITs&WKs and ALL are 11, 16.1, 16.7 and 12.3%, respectively. The result of RDs&ITs is the 3D simulation with only considering the random dopants and random interface traps and fixing the work function at nominal value; similarly for RDs&WKs and ITs&WKs. Note that large overestimation (> 16%) appears in the cases of RDs&WKs and ITs&WKs owing to significant canceling out of localized WKs fluctuated potential barriers in the total 3D simulation; therefore the difference is large. For the case of RD&ITs, the magnitude of canceling out is limited at high bias regions. Fig. 3 shows the ID-VG resulting from total 3D simulation with RDs, ITs, and WKs at the same time. The inset is the plot of the normalized drain current fluctuations (σID) vs. gate bias (VG), the normalized σID decreases drastically as VG increases owing to screening effect [1,2]. Fig. 4 is the scatter plot of ION-IOFF for the fluctuation resulting from RDs, ITs, WKs, and ALL, respectively. For the case of ALL, the trend of σIOFF follows the σIOFF,RDs and the σION is governed by σION,ITs. Figs. 5(a)-5(d), 5(a’)-5(d’) and 5(a’’)-5(d’’) are the devices with

statistically generated patterns, the simulated surface current densities and potential profiles with respect to RDs, ITs, WKs, and ALL, respectively. Figs. 5(e) and 5(f) are random selected cases which exhibit low and high threshold voltages because of the random number and position effects on the variability of Vth and ION/IOFF. Fig. 6 is the fluctuated gate capacitances (CG-VG) with all random sources, and the inset is σCG vs. VG. Fig. 7 shows each component of σCG at VG = 0.8 V for RDs, ITs, WKs, ALL, and SUM, respectively. The σCG induced by ITs is larger than RDs and WKs due to strong impact from interface which can not be reduced by screening effect. Statistical sum is 18.5% ((0.32-0.27)/0.27x100%) larger than the total 3D simulation with all random sources. The static noise margin fluctuation (σSNM) of 6T CMOS SRAM induced by RDs, ITs, WKs and ALL are 23.5, 27.4, 19.1 and 34.7 mV, respectively, not shown here. The statistical sum of σSNM,RDs, σSNM,ITs and σSNM,WKs is 20% overestimation, compared with the result of total 3D coupled device-circuit SRAM simulation including all random sources. We also perform 3D simulation on bulk FinFET devices for the purpose of suppression comparison. First, compared with control planar device, as shown in Figs. 1 and 2(b), NMOS with low ITs’ density (say less that 1011 cm-2 at the HfO2/Si interface) and minimal 1x1 nm2 TiN grains can reduce σVth (about 19.2% reduction). Such suppression could be further improved by FinFET; 16-nm bulk FinFET with the same configuration of all random sources has 45.6% reduction on σVth (reduce from 55.5 to 30.2 mV). The findings of this study indicate structure innovation provides large suppression (σVth is reduced from 55.5 to 30.2 mV), compared with process innovation (reduce from 55.5 to 44.8 mV) on planar device. The suppression capability of FinFET with AR = 2 is enhanced as AR is increased and there is an optimal AR = 5, where the suppressions for AR = 3, 4, 5 and 6 are 5, 18.1, 21.7 and 23.1%, respectively.

Conclusions

In summary, we have extensively examined the difference of fluctuations induced by RDs, ITs and WKs between statistical sum of three random sources and total 3D simulation using 3D device simulation on HKMG devices. The results of this study suggest all fluctuations should be considered simultaneously owing to existence of interactions among sources resulting from random natures. Compared with 16-nm planar devices, vertical channel structure is an effective way to minimize fluctuation. Experimental measurement and comparison will be conducted in our future work.

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Acknowledgment This work was supported in part by National Science Council (NSC), Taiwan under Contract No. NSC-99-2221-E-009-175 and NSC-100-2221-E-009-018, and by TSMC, Hsinchu, Taiwan under a 2011-2012 grant.

Reference [1] H. -W. Cheng et al., IEDM, p. 379, 2010. [2] Y. Li et al., IEEE T. ED, vol. 57, p. 437, 2010.

[3] Y. Li et al., IEEE T. ED, vol. 55, p. 1449, 2008. [4] M. F. Bukhori et al., IEEE T. ED, vol. 57, p. 795, 2010. [5] H.-W. Cheng et al., DRC, p. 103, 2011. [6] M. Cassél et al., APL, vol. 96, p. 123506, 2010. [7] P. Andricciola et al., IEDM, p. 71, 2009. [8] H. Dadgour et al., IEDM, p. 705, 2008. [9] X. Zhang et al., IEDM , p. 57, 2009.

0.30.4 0.5

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0 2 4 6 8 1012141605101520253035

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Figure 1. (a) A 3D schematic plot of the studied device with considering three random sources: random dopants (RDs), random interface traps (ITs) and random work functions (WKs), simultaneously. The square patterns with green and blue colors are TiN <200> and <111> orientations; pink dots are interface traps at HfO2/Si interface and blue dots are discrete dopants inside the channel. (b) 3136 metal grains are randomly generated in a large area of (224 nm)2, where the size of metal grain are (4 nm)2 from empirical data. The work function of each sub-region is totally random according to the material property in the table. The numbers of <200> and <111> orientations in sub-region follow Gaussian distribution varying from 0 to 16, where the average are 9 and 7, respectively. (c) 1327 dopants are randomly generated in a large cube of (96 nm)3, in which the equivalent doping concentration is 1.5x1018 cm-3. The large cube is then partitioned into about 200 sub-cubes of (16 nm)3. The number of dopants in sub-cube may vary from 0 to 14, and the average number is 6. (d) 753 acceptor-like traps are randomly generated in a large plane of (224 nm)2, in which the trap’s concentration is around 1.5x1012 cm-2. The large plane is then partitioned into about 200 sub-planes of (16 nm)2. The number of traps in sub-plane may vary from 0 to 8, and the average number is 4. (e) The fluctuated devices are implemented for 16-nm SRAM (minimal cell ration; CR = 1 is examined) circuit using coupled device-circuit simulation to estimated circuit level fluctuation. (f) The flow of coupled device-circuit simulation.

Figure 2. (a) Cumulative probability of Vth of N-MOSFET fluctuated by RDs, ITs and WKs, respectively, and by all random sources (i.e., total 3D simulation with considering RDs, ITs and WKs simultaneously; denoted as ALL). The inset is the scatter plot of Vth,RDs, Vth,ITs and Vth,WKs. The ball-shape-liked distribution confirms the simulated Vth’s are independent statistically. (b) The σVth induced by RDs, ITs, WKs, ALL, and SUM, respectively. (c) The plot of the 3D simulated [(1), (2), (3)] and statistically calculated [(1’), (2’), (3’)] σVth with respect to different combinations of any two random sources (i.e., pairwise random sources). Statistical results always overestimate σVth; thus, total 3D simulation is necessary for estimating all fluctuations resulting from RDs, ITs and WKs.

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Figure 3. The ID-VG resulting from all fluctuations (i.e., 3D simulation with considering RDs, ITs and WKs at the same time). The red and black (with circle) lines are the nominal and averaged data. The inset is the normalized σID vs. VG among different fluctuations.

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Figure 5. (a)-(d), (a’)-(d’) and (a’’)-(d’’) are the devices (nominal Vth = 250 mV) with statistically generated patterns, the simulated surface current densities and potential profiles (from source (S) to drain (D)) with respect to RDs, ITs, WKs, and ALL, respectively. Surface potential’s interaction is observed for device suffers from ALL random sources. (e) and (f) are arbitrary two fluctuated cases among 200 samples which exhibit low and high Vth, compared with the nominal one.

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Figure 7. The σCG at VG = 0.8 V with respect to RDs, ITs, WKs, ALL, and SUM, respectively. The statistical sum (SUM) is 18.5% larger than the total 3D simulation with all random sources (ALL).

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