Cu Pillar and µµµµ-bump Electromigration Reliability

and Comparison with High Pb, SnPb, and SnAg bumps

Ahmer Syed, Karthikeyan Dhandapani, Robert Moody, Lou Nicholls, and Mike Kelly

Amkor Technology

1900 S Price Road

Chandler, AZ 85286

Ahmer.Syed@amkor.com

Abstract

Failures due to Electromigration (EM) in flip-chip bumps

have emerged as a major reliability concern due to potential

elimination of Pb from flip-chip bumps and a continuous drive

to increased IO density resulting in a reduction of bump pitch

and size. Additionally, the rapid development and

implementation of 3D IC structures introducing new

interconnects (µ-bumps, RDL, microvias, and TSVs) at much

finer geometries, raises concerns about electromigration and

current carrying capacity of these interconnects.

This paper presents the results of multiple EM studies on

Cu Pillar, High Pb, SnAg, eutectic SnPb Flip Chip bumps and

µ-bumps. A special test vehicle was designed to get a head-to-

head comparison of Cu Pillar EM with that of solder bumps.

Tests are being conducted using three current levels and three

temperatures to estimate Black’s Equation parameters. A

separate test vehicle is also being tested using 5 combinations

of current and temperature to estimate the current carrying

capacity of Cu-SnAg-Cu µ-bumps of 25um diameter.

More than 8000 hours of testing is completed on flip chip

solder bump and Cu Pillar, showing Cu Pillars as having the

best reliability amongst the four bump metallurgies. The worst

reliability was observed for High Pb bumps followed by

eutectic SnPb eut and SnAg bumps. The Cu-SnAg-Cu µ-bump

structure has been tested for 5500+ hours without any failures.

The paper provides the detailed test matrix, failure data,

failure analysis, and an estimation of Black’s Equation

parameters for some of the above configurations on test.

Introduction

The electromigration reliability of chip to package

interconnects has become a major concern [1 - 6] due to

potential elimination of Pb from flip chip bumps, increased IO

density resulting in smaller and finer pitch bumps, and the

introduction of 3D IC structures such as µ-bumps, TSVs, RDL,

and microvias. At the same time, the increase in power density

and higher power applications are requiring chip-to-package

interconnects to carry more current per interconnect. Since

electromigration reliability is a direct function of interconnect

sizes and metallurgies, all of these new interconnect

developments on the packaging side need to be characterized

for electromigration reliability.

Traditionally, flip-chip interconnects have incorporated a

high Pb bump soldered with a SnPb eutectic paste to the

substrate. However, because of RoHS directives, the industry

is responding with Pb free bump development, such as SnAg

bump with SAC solder or Cu Pillar with SAC/SnAg solder.

Although a number of recent publications deal with

electromigration reliability of High Pb, Pb free, and Cu Pillar

bumps [1 - 8], a gap exists in terms of their performance

comparison for the same UBM structure and substrate finish.

The available test data is based on different test vehicles and it

becomes difficult to determine the relative performance of

these metallurgies under accelerated test conditions. In

addition, not all published data provides the essential

parameters of Black’s equation to determine the performance

and reliability for actual use conditions.

This paper attempts to fill this gap by comparing

electromigration performance of High Pb, SnPb eutectic,

SnAg, and Cu Pillar flip chip (FC) bumps using the same test

vehicle. A special test vehicle was designed with daisy chain

structures for electromigration testing and the packages were

assembled on test cards. The testing is being done using five

(5) stress conditions (combination of current and temperature)

to estimate the current density exponent, n, and the activation

energy, Ea, parameters for Black’s equation. The reliability

data of up to 8000 hours of testing is presented in the paper.

In addition, tests are being conducted for EM reliability of

µ-bumps necessary for chip-to-chip (C2C) interconnection for

3D IC stacking. The details of the test vehicle used,

geometries, current stressing conditions, and the test results at

the end of 5500 hours of testing are also presented.

Test Vehicle

Flip Chip Bump Test Vehicle

The test vehicle used to compare the electromigration

(EM) performance of Cu Pillar with high Pb, SnPb, and SnAg

bump alloys employed a 14.7mm silicon die fabricated using

65ηm technology with low-k dielectric and 150 micron bump

pitch. The die was passivated using polyimide with a 47

micron polyimide opening. The bump alloy was varied in

order to give a direct comparison of electromigration

performance. The bump alloys evaluated were eutectic SnPb,

High Pb, and Pb-free SnAg bump. In each case, the bump was

fabricated directly over the polyimide via and adjacent

polyimide passivation. The under bump metallization (UBM)

diameter of 90 micron was used for this test vehicle with a

target bump height of 75 microns. For solder bumps,

TiW(1000A)/Cu(1500A)/Ni(2µm) UBM stack was used. For

Cu pillars, 55um of Cu was plated up on sputtered TiW/Cu

layers. The UBM for Cu Pillar was still 90um but the top

diameter at solder interface is around 100um due to the draft

angle resulting from the photoresist process. The Cu pillars

were then plated with 20 and 40um SnAg solder to form

solder caps.

The dice were attached to an organic laminate consisting

of a 4-2-4 build up structure with a 400µm thick core. Two

different substrate pad types were used; SMD and NSMD.

The solder resist opening for SMD pads was 85um and the

978-1-61284-498-5/11/$26.00 ©2011 IEEE 332 2011 Electronic Components and Technology Conference

metal pad diameter for NSMD pads was 115 microns. In the

case of SMD pads, the pads were covered with solder (SOP),

whereas the NSMD pads were only coated with an organic

surface protectant (OSP). Finally, SAC305 solder balls were

attached on the bottom side of the substrate. Figure 1 shows

the bump layout on the die and the top view of the substrate.

Table 1 shows the metallurgical details of each test vehicle.

Figure 1: Bump layout on die (14.7 x 14.7mm) and top

view of substrate (42.5 x 42.5mm)

Table 1: Metallurgical details of 5 flip chip bump

configurations used for EM testing

Test

VehicleHigh Pb

Eutectic

SnPbPb Free

Cu Pillar

SMD

Cu Pillar

NSMD

FC Bump95/5

Pb/Sn

63/37

Sn/PbSnAg2.3 Cu Pillar Cu Pillar

SnAg Cap NA NA NA 20um 40um

SOP Alloy63/37

Sn/Pb

63/37

Sn/PbSAC305 SAC305 SAC305

Substrate

Pad TypeSMD SMD SMD SMD NSMD

BGA Balls SAC305 SAC305 SAC305 SAC305 SAC305

Bump

x-section

µ-bump Test Vehicle

For µ-bump evaluation, an EM test vehicle was created

using Amkor internal silicon processes for patterning copper

traces, bump pads and micro bumps. The test vehicle

consisted of top and bottom die which were created by using a

single metal layer of 3um copper on 8 inch wafers.

Passivation openings were created on copper pads and µ-

bumps on the bottom and top die were created by

electroplating. The top die had a bump structure of 16um thick

Cu with 10um SnAg cap. For the bottom die, the bump

structure consisted of 10um Cu thickness with 5um SnAg cap.

The bottom die were joined to the top die using mass reflow

bonding. Figure 2 shows the general construction for each die

and a typical cross section of the final joints. After die to die

joining, this subassembly was wire bonded to a conventional

laminate substrate. Once wire-bonding was completed the

finished package was molded and standard SAC305 balls

were attached on the BGA side.

The final packages for both FC bump and µ-bump

evaluations were soldered to specially designed 1.6mm thick

EM test boards which were fabricated using high temperature

material to eliminate failures in the board due to high current

and temperature. The packages were pre-conditioned (125C

bake for 8 hours + 3X reflow, no moisture soak) before board

attachment. Since SAC305 solder balls were used for the

packages, the peak reflow temperature for board assembly was

around 240C.

Sn2.3Ag Solder

25um Diameter

Cu

Cu

Bottom Die: Silicon Interposer

Top Die: FPGA

Figure 2: Cross-sectional views of µµµµ-bump structures

and final joint

EM Test Structures

Although both test vehicles used for EM testing have

multiple EM structures, 2-bump daisy chain structures were

used in these evaluations. Figure 3 shows the EM structures

used for the two test vehicles with electron flow direction.

This 2-bump daisy chain structure has the advantage that both

sides of die to substrate (or die to die) interconnect are

stressed at the same current level and failure on one side

causes the failure of the whole structure. This is also useful

when the increase in resistance is used as the failure criteria as

this increase will be primarily caused by failure of one bump

as opposed to many bumps for multiple bump daisy chains.

Die

Substrate

e- e-

Cathode Anode

CathodeAnode

Die

Substrate

e-e- e-e-

Cathode Anode

CathodeAnode

Top Die

Bottom Die Figure 3: Electromigration test structures for FC bump

and µµµµ-bumps

Test Conditions and Joule Heating

The primary purpose of electromigration (EM) reliability

characterization of an interconnect type is to determine its

current carrying capacity under operating conditions for the

designed useful life and an acceptable failure rate. The

estimation of this current carrying capacity requires testing

these interconnects under accelerated test conditions with

higher levels of current and temperatures than these

interconnects will usually experience in actual operating

conditions. The results from these accelerated test conditions

are then used to estimate the parameters of Black’s equation,

shown by Equation (1) below. Typically, 15 or more samples

are tested for 3 or more current levels and temperatures to

have a better confidence in estimated current density exponent,

n, and activation energy, Ea. However, the number of samples

tested and the stress conditions (combination of current and

temperature) used are limited due to test equipment

availability.

333

=−

KTE

JAMTTF an exp (1)

For flip chip bump characterization, 4 to 5 different

conditions were employed here with a sample size of 8 DUTs

(Device under Test) for each condition. The test conditions

combination used are shown in Table 2. It should be noted

that the temperature values listed are the oven settings and the

actual device temperature is higher due to joule heating, which

is discussed later.

Table 2: Stress conditions and test matrix for FC Bump Current &

Oven Temperature0.4 Amps 0.55 Amps 0.7 Amps

Cu Pillar SMD

SnAg SnAg

High Pb High Pb High Pb

Eut SnPb Eut SnPb

Cu Pillar NSMD

Cu Pillar SMD Cu Pillar SMD Cu Pillar SMD

SnAg SnAg

High Pb High Pb

Eut SnPb Eut SnPb

160 deg C Eut SnPb

130 deg C

145 deg C

For µ-bump evaluation, 5 combinations were employed

with a sample size of 10 DUTs per condition, as listed in

Table 3. Since die-to-die µ-bumps are expected to carry much

lower current than a flip chip bump, the current values used in

this test are significantly lower than the ones used for flip chip

bump evaluation. However, in terms of current densities, the

lowest value used for µ-bump testing was at least 1.65X

higher than the highest value used for FC bumps, see Table 4.

Table 3: Stress conditions and test matrix for µµµµ-bump test

0.1 0.175 0.25

132 X

146 X X X

160 X

Oven Temperauture

(deg C)

Current Levels (Amps)

Table 4: Current densities used for testing

Current

(Amps)

Current

Density -

UBM

(A/cm2)

Current

Density -

SRO

(A/cm2)

Current

(Amps)

Current

Density

(A/cm2)

0.4 6288 7049 0.1 20372

0.55 8645 9692 0.175 35651

0.7 11003 12336 0.25 50930

u-bump Test

Vehicle

25um u-bump dia

FC Bump Test Vehicle

90um UBM, 85um SRO

dia

For both test vehicles, the resistance of EM structures was

measured using a 4-point Kelvin measurement technique.

Special test equipment is used, which is capable of measuring

the 4-point resistance measurement with high precision. The

initial room temperature resistance values were measured to

be around 50 milliohm and 33 milliohm for flip chip bump

and µ-bump structures, respectively.

The test equipment used here is capable of computing

"Joule Heating Effect" which refers to the increase in device

temperature due to current stressing. The testing system

automatically performs a Temperature Coefficient of

Resistance (TCR) calculation for each stress current and for

each DUT. For the Flip Chip bump test structures, the average

temperature increase due to Joule heating were measured as

3.4oC (Range: 2.4 – 4.4

oC) and 7.3

oC (Range: 6.0 – 7.8

oC) for

400 and 700mA current stressing, respectively. For the µ-

bump structure, the average temperature increases were

measured to be 3.6oC (Range: 2.8 – 4.2

oC) for 100mA and

4.9oC (Range: 4.3 – 5.6

oC) for 250mA current stressing.

The EM test device used here for Flip Chip bump test was

also designed with a temperature sensor located above the

bump under test and this was used to re-confirm the

temperature increase due to Joule heating. The temperature

increase due to current measured using this thermal sensor

was in the same range as listed above.

Results

A 4-point Kelvin measurement scheme was adopted to

measure the daisy chain resistance of the 2-bump structure

throughout the test and a 10 milliohm increase in resistance

was used as failure criteria for device failures. Figure 4 shows

a typical resistance increase vs. time curve and the failure

criteria used.

0

0.05

0.1

0.15

0.2

0.25

0 300 600 900 1200 1500

Res

ista

nce

(oh

ms)

Time (hours)

Resistance History

Failure Criteria

Figure 4: Typical resistance vs. time plot during EM

testing and the failure criteria

Table 5: Summary of test results for FC bump

Bump Configuration

Stress

Current

(mA)

Oven

Temperature

(deg C )

# Samples # FailedTest Hours

Completed

High Pb 400 130 8 8 5561

High Pb 400 145 8 8 2200

High Pb 550 130 8 8 2267

High Pb 700 130 7 7 714

High Pb 700 145 8 8 799

Eut SnPb 400 130 8 3 7130

Eut SnPb 400 145 8 8 2167

Eut SnPb 400 160 10 10 671

Eut SnPb 700 130 8 8 3274

Eut SnPb 700 145 8 8 742

SnAg 400 130 7 1 7130

SnAg 400 145 8 4 8140

SnAg 700 130 7 4 7130

SnAg 700 145 8 8 4180

Cu Pillar SMD 400 145 8 3 8140

Cu Pillar SMD 550 145 8 6 (4*) 8140

Cu Pillar SMD 700 130 10 2* 7130

Cu Pillar SMD 700 145 8 6 (4*) 8140

Cu Pillar NSMD - 1 700 130 8 3* 7130

Cu Pillar NSMD - 2 700 130 8 4 7130

334

Table 5 provides a summary of results at the current state

of testing. While testing has been complete on High Pb and 3

of the 4 legs for SnPb eutectic bumps, very few failures have

been observed for both SnAg and Cu Pillar bumps for most of

the test conditions. The last two legs (Cu Pillar NSMD -1 & 2)

are being tested using just one condition comparing the effect

of bump polarity. The NSMD-1 leg has 3 bumps feeding

current to one bump, resulting in 1/3rd

of the total current from

the substrate side but full current from the die side. The

NSMD-2 leg, on the other hand, uses the same 2-bump pair

EM structure as shown in Figure 3 and thus tests both sides of

the interconnect with the same current.

High Pb Bump: Figure 5 shows the lognormal

distribution plot of failures for all 5 conditions for High Pb

bumps. As expected the leg with the most severe condition

(145oC, 700mA) failed the earliest with mean life of 285 hours

and the leg with the most benign condition (130oC, 400mA)

failed the latest with mean life of 4,170 hours. For 130oC

condition, increasing the current from 400mA to 550mA and

700mA resulted in 4X and 7X lower mean lives, respectively.

However, for 145oC condition, increasing the current from

400mA to 700mA resulted in only 3.2X reduction in mean life.

Analyzing this data for Black Equation’s parameters, Eq.

1, resulted in estimated values of 1.08eV for activation energy,

Ea, and 1.86 for current density exponent, n. These values are

in line with the expected values for solder bumps.

Hours to Failure

Cu

mu

lati

ve %

Fa

iled

10.0 10000.0100.0 1000.01.0

5.0

10.0

50.0

99.0

130C

700mA

145C

400mA

145C

700mA

130C

400mA

130C

550mA

Figure 5: Lognormal distribution plot for High Pb bump

failures

SnPb eutectic bump: Figure 6 shows the failure

distribution for 4 of the 5 conditions for SnPb eutectic bump.

Not enough failures are observed so far for the most benign

condition of 130oC & 400mA. The mean life for these failures

ranged from 405 hours for 145oC, 700mA condition to 1790

hours for 130oC, 700mA condition. For 145

oC, increasing

current stressing to from 400 to 700mA resulted in 3.3X

reduction in mean life. Also, for 400mA condition, increasing

temperature from 145oC to 160

oC resulted in 2.6X reduction

in life.

Based on these four data sets, the estimated Ea and n

values are 1.06 eV and 1.62, respectively, which are again

within the expected range for these values for solder bumps.

Hours to Failure

Cu

mu

lati

ve %

Fa

iled

100.0 10000.01000.0

1.0

5.0

10.0

50.0

99.0

145C

700mA

160C

400mA

130C

700mA

145C

400mA

Figure 6: Lognormal distribution plot for eutectic SnPb

bump failures

SnAg bump: Table 5 shows that 100% failure rate was

achieved on only one condition (145oC, 700mA) by 8140

hours of testing. Although two other conditions (145oC,

400mA & 130oC, 700mA) have seen 50% failure rate but for

both conditions the first 2 failures were observed much earlier

than the last 2 failures and the data is not sufficient at this time

to plot failure distribution. The most benign condition (130oC,

400mA) has resulted in only one failure so far. For 145oC,

700mA condition where 100% failure rate has been achieved,

the mean life is estimated as 2320 hours.

Because of insufficient data at this time, estimates for Ea

and n values cannot be calculated.

Cu Pillar bump: Table 5 shows that a number of failures

were observed on multiple conditions for Cu Pillar bumps but

most of these failures (shown by *) were observed before

5000 hours. Failure analysis of these electrical failures -

discussed in the next section – show no evidence of

electromigration related damage on these bumps to cause

significant resistance increase. Additional failures observed

beyond 6000 hours of testing are being analyzed at this time

to determine if any of these are due to electromigration related

damage in Cu pillar bumps.

Comparing the above results, the EM performance can be

ranked as High Pb < SnPb eut < SnAg < Cu Pillar. This is also

clearly shown in Figure 7 where the performance of these FC

bump configurations is compared for 145oC & 700mA

condition. While the performance ranking of eutectic SnPb,

SnAg, and Cu Pillar is as per expectations, the performance of

High Pb bump is very surprising. High Pb FC bumps have

been used in the industry for over 40 years and are generally

considered very reliable for EM performance. In fact, other

alloys and bump structures are commonly compared with

High Pb to determine if these new alloys and structure are

reliable. It should be noted, however, that all of these bumps

335

were tested using Cu+SOP finish on the substrate in the

current study. This has a significant influence on EM

performance of High Pb and other bumps and is discussed in

detail in a later section.

The above data also shows that for the same condition Cu

Pillar can result in 3 to 4X better performance than SnAg

bump and confirms the findings from other published work [1,

4]. A more accurate estimate for Cu Pillar EM performance

and its improvement over other bump configurations can only

be established after complete data is collected. Therefore, the

tests are being continued until sufficient failures are observed.

Time to Failure (hours)

Cu

mu

lati

ve %

Fa

iled

10.0 8000.0100.0 1000.01.0

5.0

10.0

50.0

99.0Test Condition: 145C, 700mA

SnAgSnPb Eut

Unconfirmed

Failures for

Cu PillarHigh Pb

Figure 7: Comparison of FC bumps EM performance for

145oC & 700mA condition

33.6

33.8

34.0

34.2

34.4

34.6

34.8

35.0

35.2

35.4

0 500 1000 1500 2000 2500

Res

ista

nce

(m

illi

oh

ms)

Time (hours)

Figure 8: Typical Resistance vs. Time plot from µµµµ-bump

testing

Cu-SnAg-Cu µµµµ-bump: As of this writing, 5500 hours of

testing has been completed for Cu-SnAg-Cu µ-bump for all 5

conditions without any failure. This is a much better

performance than any of the FC bump configuration tested

above, especially since the current densities used for µ-bump

testing are much higher than the ones used for FC bump

testing, as shown in Table 4.

Figure 8 shows the resistance vs. time plot for one of the

µ-bump DUT. The resistance increase by about 4%

(1.4milliohms) during the first 1400 hours. However, there is

no further increase in resistance beyond that time. This initial

change in resistance is possibly due to conversion of solder

into intermetallics and not due to EM damage. Similar

observations are made elsewhere for Cu-solder-Cu µ-bump

interconnects [12].

Failure Analysis

High Pb bump: The above data shows surprisingly lower

EM performance for High Pb bumps compared to other bump

configurations. High Pb bumps are in use for a long time now

and are considered as very robust in terms of electromigration

performance. Published data [6] also shows high Pb bump to

be performing 12X better than eutectic SnPb bumps. Another

data [7] shows even better reliability for High Pb bump over

SnPb. In the current study, the failure analysis showed that the

failures primarily occurred on the substrate side with electron

flow out of substrate (cathode) with crack between the large

chunks of Cu-Sn intermetallics and substrate Cu pad, as

shown in Figure 9. This was also surprising as published data

[6] shows failures on the UBM side.

e-e- e-e-e-e-e- e-e-e-

Figure 9: Failure mode for High Pb bump showing failure

on substrate (cathode) side

However, there are two big differences in the present

study vs. published data on high Pb bumps [6]; the surface

finish on the substrate and the UBM stack. While this study

was conducted on Cu SOP substrate finish and TiW/Cu/Ni

UBM, the published data is based on ENIG finish on the

substrate and Ti/Ni(V)/Cu UBM. The surface finish turned out

to be the main reason for lower EM performance in this study,

as discussed later.

Figure 10 shows the element mapping of High Pb bump

before and after EM testing. As assembled High Pb bumps

with SnPb eutectic SOP show clear Pb rich (mainly bump)

and Sn rich (eutectic SOP) regions. However, after current and

temperature stressing, the whole bump converts into Pb rich

and Cu-Sn IMC and no Sn rich region was observed. This

reveals the possible reason for earlier than expected failures

for High Pb bump with Cu substrate finish. During

current/temperature stressing, Pb migrates to anode side and

Sn accumulates on the cathode side. This accumulated Sn

forms Cu3Sn intermetallic along with Cu consumption from

substrates pad. Further stressing results in the formation and

growth of Cu6Sn5 IMC with additional Cu consumption until

all Sn is used up in IMC formation. Finally, voids are formed

at the Cu6Sn5 and Cu3Sn interface and grow with further

current stressing.

This interaction of the amount of Cu available for High

Pb bump was also observed in previous studies [6, 9], albeit

on the UBM side, even with ENIG finish on the substrate. In

[6], where very thin Cu was used on the UBM side, the failure

occurred on the UBM side but at a much later time. However,

336

for 5um thick Cu UBM [9], catastrophic failures were

reported for High Pb bump soldered to TiW(0.2um)/Cu

(0.4um)/ Cu (5um) UBM. The failures primarily occurred on

the UBM side in that case due to formation of Cu6Sn5 and

Cu3Sn intermetallics. Since only a limited amount of Sn is

available for a High Pb bump and eutectic SOP combination,

exposure of this Sn to thick Cu results in rapid formation and

growth of these two intermetallics and complete depletion of

Sn from solder. For a thin Cu case [6], Sn still remains in the

system after Cu consumption and this additional Sn delays

crack initiation and growth, thus longer life.

Pb Rich Sn Rich

(a) Before EM test

e-e-e-Pb RichPb Rich

Cu-Sn IMC

(b) After EM test

Figure 10: Element mapping of High Pb bumps before and

after EM testing

SnPb bump: Figure 11 shows the X-sectional view and

element mapping of anode and cathode bumps for eutectic

SnPb bumps. The failure primary occurred on the substrate

side (cathode bump – electron flow out of substrate) between

the two Cu-Sn intermetallic phases along with Cu

consumption from the substrate pad. However, significant

amount of Sn still remains in the joint, which possibly is the

reason why eutectic SnPb bumps survived longer than the

High Pb bumps for the same test condition. Some EM damage

was also observed on the anode bump (electron flow out of

UBM side) due to current crowding. Also, a complete

migration of Pb to the substrate side can be observed for the

anode bump.

e-

CathodeAnode

e-

Cu3Sn

Cu6Sn5

(Cu,Ni)6Sn5

Figure 11: Cross-sectional analysis and Element mapping

of eutectic SnPb bumps after EM testing

SnAg bump: For SnAg bump, the failure was primarily

observed on the UBM side but significant damage was also

observed on the substrate side, as shown in Figure 12. For the

cathode bump (electron flow from substrate), Cu consumption

from substrate pad and Cu6Sn5 IMC migration to UBM side

can be observed along with cracking on the substrate side.

However, the primary pancake type crack was observed on the

UBM side of the anode bump (electron flow from UBM side).

This crack is just under the Ni3Sn4 IMC but chunks of IMCs

were also observed just under the crack. Both Ni3Sn4 (layer

under the UBM) and (Cu,Ni)6Sn5 (smaller chunks) were

identified on the UBM side. Since the UBM has 2 um thick Ni

barrier on thin Cu, the presence of (Cu,Ni)6Sn5 IMC on the

UBM side indicates SAC305 SOP as a source of this Cu on

the UBM side.

e-e-

Cu6Sn5

CathodeAnode

Figure 12: Cross-sectional analysis of SnAg bumps after

EM testing

Cu Pillar bump: As mentioned earlier, a number of electrical

failures were observed on Cu Pillar bumps before 5000 hours.

However, failure analyses of these bumps didn’t show any

EM related failures of these bump. One representative results

of failure analysis are shown in Figure 13. Although a minor

crack is observed on the cathode bump on the substrate side,

this is not enough to cause significant change in resistance.

The figure also shows significant part of SnAg bump +

SAC305 SOP joint converted into Cu6Sn5 IMC even within

1000 hours on current and temperature stressing. Asymmetric

Cu consumption can also be observed on the Cu pillar side on

anode bump, possibly due to current crowding.

e-e-

Sn Rich

Cu6Sn5

Cu6Sn5

Sn Rich

CathodeAnode

Figure 13: Cross-sectional analysis and Element mapping

of Cu Pillar bumps after EM testing

Figure 14 provides the magnified view of substrate side

of the cathode bump. Although significant Cu consumption

can be observed for the substrate pad, electrical continuity is

maintained. Thus the electrical failures observed don’t seem to

correlate with significant EM related damage.

A number of other early failures were also analyzed but

none of them showed EM related damage on Cu pillar bump.

One possible cause of these electrical failures is the substrate

trace design in the current path. Additional failure analyses of

substrates using parallel lapping are in progress to ascertain

the failure mode.

337

Figure 14: Magnified view of substrate side of Cu Pillar to

substrate interconnect

µµµµ-bump: Although no failures have been observed in µ-bump

structures even after 5500 hours of testing, one device was

removed after 2775 hours of 175mA and 132oC testing. Figure

15 shows that SnAg solder in both cathode and anode bumps

has been converted to Cu-Sn IMCs. Asymmetric Cu

consumption and possible kirkendall voids in Cu3Sn layer can

also be observed. The figure also shows an unstressed bump

(no current stressing but same amount of thermal aging) on

the same device. For this bump, the Cu consumption is more

uniform but solder still converted to IMC.

e-e-

CathodeAnode

Cu6Sn5

Cu3Sn

Cu6Sn5

Cu3Sn

Unstressed

Bump

Figure 15: Cross-section view of µµµµ-bumps after 2775 hours

of EM testing (not failed)

Discussion

The results from this study and other published [6, 7, 9]

and unpublished work seem to indicate a reverse trend on FC

bump EM performance depending on the solder alloy and

substrate pad finish. For High Pb bumps, this study and [6, 7]

indicate that compared to ENIG finish, the EM performance is

much worse for Cu finish on substrates. However, the trend

reverses for SnAg bump [1, 10], where Cu finish was found to

be much better than ENIG. For SnPb bump, while internal

unpublished work shows no significant impact of surface

finish, one study [11] did find 6X better performance for Cu

finish over ENIG.

This reverse behavior for Cu finish with different alloys

might be related to the amount of Sn available in the joint and

the thickness of Cu (either as final metal on UBM side or as

substrate finish). With thicker Cu, solder joints with low Sn

content (e.g., High Pb) result in complete depletion of Sn from

the joint during EM testing due to the formation and growth of

CuSn IMC, thus resulting in earlier failures. On the other hand,

joints with significant Sn content (e.g., SnPb eutectic and

Sn2.3Ag) will not experience complete Sn depletion due to

CuSn IMC formation and have much high EM performance.

For Cu Pillar or µ-bumps with SnAg solder, although all

Sn is also used up in the formation for IMC, the absence of Pb

in the system resulted in much better EM performance than

High Pb bump on Cu finish. The thickness of Cu does seem to

play a role for Cu pillar as thinner Cu may not be enough to

eliminate the current crowding effect completely at the solder

level, which will ultimately reduce the performance, as

observed by Yoo et al [13]. In their tests for the same test

conditions, 60um thick Cu pillar performed 39X and 8X better

than 5um and 10um Cu pillar, respectively.

To study the effect of Cu Pillar height on current

crowding, finite element simulations were performed on a

single bump with current flowing in from the UBM side. Cu

pillar height was varied from 5 to 50um and for each case,

current density distribution was determined in solder layer just

under the pillar. Figure 16 shows how the current crowding

ratio (maximum to average current density) varies with

increasing pillar height. The current crowding ratio is highest

with 5um thick pillar with maximum current density on the

left side of bump (the side current flows in from). As the pillar

height was increased, the current crowding ratio continued to

reduce until the pillar height of 35 um. A further increase in

pillar height, however, started to increase the current crowding

ratio slightly with maximum current density shifting to the

center of the bump. This shows that from current crowding

and current density perspective, 35 um pillar height might be

better than a 50um pillar. Since lower pillar height is also

preferred for reducing low-k stresses, a 35um pillar height

might be optimum for both EM and mechanical reliability. It

should be noted, however, that these simulations don’t capture

the effect of solder transforming to IMC during current

stressing and the complete damage process during EM test.

Thus, actual test data needs to be generated to confirm this

effect of Cu pillar height.

1

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

0 10 20 30 40 50 60

Cu

rren

t C

rod

ing R

ati

o

Cu Pillar Thickness

Current

Figure 16: Simulation results on the effect of Cu pillar

height on current crowding ratio

Summary and Conclusions

Electromigration reliability tests were performed on

various FC bump configurations with Cu finish on the

substrate. The results so far indicate that Cu pillar performs

the best followed by SnAg, eutectic SnPb, and High Pb. The

results for High Pb bump were surprising but further

investigation revealed that a complete depletion of Sn from

the joint due to formation of Cu-Sn IMCs is the primary

reason for this lower performance. The amount of Sn available

in the joint seems to have a direct influence on EM reliability

for Cu finish substrates and EM performance improves with

increasing Sn in the joint.

338

The test data on µ-bumps also show much better EM

reliability than FC bumps, even with significantly higher

current density.

For Cu pillar bumps, current crowding at solder level

decreases with increasing pillar height until a minimum is

reached. Further increase in pillar height may not be too

beneficial from EM perspective and may reduce mechanical

reliability.

Acknowledgements

The authors would like to thank various people within

Amkor who helped us complete this work. Thanks are due to

Jon Aday, Millete Carino, Steven Lee, Malvin Lara, Riki

Whiting, and DongHee Lee for the design and assembly of

flip chip bump and u-bump test vehicles. Thanks are also due

to CJ Berry for his insights in proper test vehicle design and

support during testing.

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