Metal Nanocrystal Memory with Sol-Gel Derived HfO2 High-κ Tunneling Oxide

Shih-Tang Chen1, Kun-Cheng Huang1, Hua-Chiang Chen1, Fu-Ken Liu2, and Ching-Chich Leu1,*

Abstract-A Metal–oxide–semiconductor (MOS) capacitor structure containing gold (Au) nanoparticles (NPs) within sol-gel derived HfO2 high-κ oxide is fabricated. Firstly, the Au NPs with particle size of about 3.3nm were synthesized by chemical reduction method. Then the 10 nm-thick HfO2 tunneling oxide, the Au NPs and the 15 nm-thick HfO2 control oxide were prepared by spin coating method to construct a Si/HfO2/Au NPs/HfO2 memory structure. The sol-gel derived ultra-thin HfO2

high-κ oxide layer showed good electrical properties and were critical to desirable memory property of the MOS structure. The high-frequency capacitance–voltage(C-V) measurements demonstrated the well defined counterclockwise hysteresis memory loops which was originated from the Au nanocrystals. By utilizing high-k HfO2 as tunneling oxide, the MOS structure showed memory effect even at a low voltage of ±2V. The flat-band voltage shift was about 0.8 V by a swapping voltage between ±5V. Although the memory window was not so large, the MOS showed better retention characteristics by replacing SiO2 with HfO2 as tunneling oxide. Therefore, we have successfully fabricated nanocrystal memory device with HfO2 high-k tunneling oxide which are attractive for low operation voltage non-volatile memory applications.

BACKGROUND

The nonvolatile flash memory devices utilizing floating gate as charge storage nodes had met the leakage and reliability challenges as the devices scaling down. In order to overcome these problems, the metal nanocrystal memory was proposed in recent years. However, there is a challenge between the program/erase (P/E) time and charge retention time of metal nanocrystal memory. In order to obtain faster P/E operation, a thinner tunneling oxide is needed. But at the same time, a thicker tunneling oxide is favorable to achieve longer retention time. In order to overcome this problem, several researches have focused on materials of tunneling and control oxide, utilizing high-dielectric constant (high-k) materials [1-3]. For most high-k dielectrics, hafnium oxide (HfO2) is a promising candidate as a tunneling oxide or a control oxide due to its high dielectric constant (~25-30) [4], heat of formation (271kcal/mol)[5], and band gap(5.68ev)[6]. Base on this fact, the MOS capacitor structure containing Au NPs within sol-gel derived HfO2 high-κ oxide is fabricated in present work. Firstly, the Au NPs were prepared by chemical reduction method and self-assembled onto 10nm HfO2/Si substrates by spin coating.

1Department of Chemical and Materials Engineering, National University of Kaohsiung, Kaohsiung,Taiwan, R.O.C.

2Department of Applied Chemistry, National University of Kaohsiung, Kaohsiung,Taiwan, R.O.C. *Contacting Author: Ching-Chich Leu is with the Department of Chemical and

Materials Engineering, National University of Kaohsiung, Kaohsiung,Taiwan, R.O.C. (phone: +886-7-5919456; email:ccleu@nuk.edu.tw).

Then, the sol-gel derived HfO2 layer was spin coated to fabricate a MOS structure. The C–V electrical properties and charge retention characteristics of the MOS structures are discussed.

CURRENT RESULTS

10nm HfO2 was deposited onto p-type (100) Si substrate as tunneling oxide. Fig.1 presents the procedure of the HfO2 layer which was prepared by sol-gel synthesis method. Fig. 2 shows the XRD patterns of the 10nm HfO2 films on Si substrate. As seenin this figure, the diffraction peak could be attributed to

the ( 111 ) monoclinic phase of HfO2. Based on this result, we can identify that HfO2 was succeeded to be deposited on Si substrate and exhibited polycrystalline structure. The 3nm Au solution was prepared by NaBH4 reduction of HAuCl4 in an ice bath condition [7] as illustrated in Fig. 3. For constructing the memory structure, the synthesized 3nm Au NPs was deposited on top of 10nm HfO2/Si substrate. The deposition steps of Au NPs on substrates are shown in Fig.4. Heat treatment were performed on the 3nm Au NPs at 200-500 . Fig.5 shows the scanning electron microscope (SEM) image of as-deposited 3nm Au NPs on substrates. The mainly size distribution and estimated density of the dispersed 3nm Au NPs are 4.50.5nm and 2.6x1011 cm-2, respectively. After deposition of the 3nm Au NPs, it was covered by sol-gel synthesized HfO2 as a control oxide to construct a Si/HfO2/NPs/HfO2 memory structure as shows in Fig.6. A reference sample without NPs was also fabricated. The high-frequency (100 kHz) C-V measurements were conducted using a HP 4294A capacimeter at room temperature to investigate the electrical properties of memory structure. In Fig. 7, we observed a clear counterclockwise C-V hysteresis curves, indicating the electron charging and discharging effects from Au NPs. The flat-band voltage shift was about 0.8 V at a swapping voltage between ±5V. The retention characteristics of the Au nanocrystal memory were showed in Fig.8. The MOS structure embedded with Au nanoparticles behaved a desirable retention characteristic up to 104s. The deterioration of memory window of MOS structure is only 33% after 104 s. Although the memory window was not really large, the MOS showed better retention characteristics by replacing SiO2 with HfO2 as tunneling oxide.

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Fig.1. The procedure of the HfO2 was prepared onto Si substrate by sol-gel synthesis method

Fig.2. The XRD pattern of 10nm HfO2 films deposited on Si substrate.

Fig.3. The schematic illustration of synthesis of 3nm Au NPs.

Fig.4. The procedure of the Au NPs prepared on 10nm HfO2/Si substrate.

Fig.5. SEM image of 3nm Au NPs on top of 10nm HfO2/Si substrates.

Fig.6. A schematic illustration of a fabricated MOS structure embedded with Au NPs.

Fig.7. The high frequency C-V curves of MOS structure with or without Au NPs.

Fig.8. The charge retention characteristics of the MOS structure embedded with Au NPs.