[IEEE 2008 IEEE International Reliability Physics Symposium (IRPS) - Phoenix, AZ, USA...

5
DEGRADATION MECHANISMS OF 0.1 m AlSb/InAs HEMTS FOR ULTRALOW- POWER APPLICATIONS Y.C. Chou, J. M. Yang, M. D. Lange, S. S. Tsui, D. L. Leung, C. H. Lin, M. Wojtowicz, and A. K. Oki Northrop Grumman Space Technology One Space Park, Redondo Beach, CA 90278 Tel: 310-812-3550; Fax: 310-813-0418; E-mail: [email protected] ABSTRACT The degradation mechanisms of 0.1 m AlSb/InAs HEMTs subjected to elevated-temperature lifetesting at three temperatures in N 2 atmosphere were investigated. Device degradation exhibits the increase of non-pinch-off drain current (I DS ), the decrease of transconductance (g m ) and the gate current (I G ) increase. The I G increase was found to correlate with material degradation on the gate-recess and Al 0.7 Ga 0.3 Sb-mesa-floor surfaces. Higher oxygen content was detected on these surfaces, indicating that they were modified by oxidation, which resulted in the I G increase. Despite the degradation observed in 0.1 m AlSb/InAs HEMTs, the three- temperature lifetesting shows that the activation energy (E a ) is approximately 1.5 eV and demonstrates a median time to failure (MTF) of 2 10 6 hours at T junction of 85 °C. This reliability result is essential for successful insertion of AlSb/InAs HEMTs into systems with ultralow-power requirements. Moreover, ohmic-metal lateral diffusion of Pd and Au elements was observed. To avoid potential ohmic-metal-lateral-diffusion induced device failure, lifetesting temperatures were kept below 190 °C in this investigation. INTRODUCTION AlSb/InAs HEMT technology has proven to be viable next- generation for low-noise, low-power, and high-speed applications due to the superior electronic properties of the InAs channel, such as electron mobility and peak velocity. The electron mobility and peak velocity are nearly two times larger than those of InAlAs/InGaAs/InP HEMTs with In x Ga 1-x As channels [1]. The combinations of high peak electron velocity (~ 4 10 7 cm/s) at low electric field, and high channel conductivity, enable operation of AlSb/InAs HEMTs at very low drain voltage. Accordingly, AlSb/InAs HEMTs have become critical elements for large-aperture phased-array applications with ultralow-power requirements [2]. The design of a large-aperture phased-array system is essentially power constrained. With the quantities of low-noise amplifier (LNA) elements ranging from 10 5 to 10 6 , reduction of total power dissipation in the system is a big challenge. A decrease of dc-power dissipation in LNAs from 10 mW to 1 mW would result in a dc- power reduction on the order of 1 to 10 kW. This is essential for a phased-array system with requirements of small size, light weight and low cost. As a result, AlSb/InAs HEMT technology has come into the mainstream of research and development recently, owing to its superior electronic properties for ultralow-power applications. To date, researchers have demonstrated superior microwave performance of LNAs at X-band [2-3] and W-band [4-5] frequencies using AlSb/InAs HEMTs. Furthermore, the manufacturability of AlSb/InAs HEMT LNA technology has been demonstrated [6]. However, the reliability evaluation of AlSb/InAs HEMT LNAs is still lacking. Recently, reliability evaluation of AlSb/InAs LNAs was reported, for the first time, by Chou et. al [7]. Nevertheless, comprehensive investigation of degradation mechanisms of 0.1 m AlSb/InAs HEMTs subjected to elevated-temperature lifetesting had still not been performed. In order to improve reliability performance of AlSb/InAs HEMTs to assure successful insertion for phased-array applications, it is important to understand the degradation mechanisms of AlSb/InAs HEMTs subjected to elevated-temperature lifetest. In this study, we performed three-temperature lifetesting to investigate degradation mechanisms of 0.1 m AlSb/InAs HEMTs. As mentioned above, device degradation exhibits the increase of non-pinch-off I DS , the decrease of g m and the I G increase. The I G increase was found to correlate with material degradation on the gate-recess and Al 0.7 Ga 0.3 Sb-meas-floor surfaces. Higher oxygen content was detected on these surfaces, indicating modification by oxidation, which resulted in the I G increase. In addition, while gate- sinking induced degradation was not observed on AlSb/InAs HEMTs, ohmic-metal lateral diffusion of Pd and Au elements was observed. Furthermore, Northrop Grumman (NG) has developed a wafer-level-packaging (WLP) technology to provide hermetic sealing of AlSb/InAs HEMT LNAs. This enables prevention of oxygen incorporation into the AlSb/InAs HEMT materials, thus reducing the potential for reaction with oxygen. Consequently, reliability performance could be improved. AlSb/InAs HEMT TECHNOLOGY The cross section of a 0.1 m AlSb/InAs HEMT is shown in Figure 1. The AlSb/InAs structures were grown by molecular beam epitaxy (MBE) on 3-inch semi-insulating GaAs substrates. The AlSb/InAs structures typically exhibit mobility of 25,000 to 30,000 cm 2 /V-s and electron sheet density of 1.2 0.3 10 12 cm -2 at 300 K. The lattice mismatch of the InAlAs barrier to the underlying AlSb barrier is as high as 5.5%; but because the channel is grown earlier, its quality is not affected by relaxation of the InAlAs. As a result, the thickness of the InAlAs barrier is kept below 40 Å in this device structure in order to preserve the material quality. Detailed information regarding the design of this structure can be found in previous publications [1, 8]. The fabrication processes of NG’s AlSb/InAs HEMTs were reported previously [6]. The device mesas were formed by a BCl 3 /Ar-based inductively-coupled-plasma (ICP) etching technique that etches the materials down to the Al 0.7 Ga 0.3 Sb buffer layer. The details of ICP etching were reported previously [9]. The ohmic contact resistance achieved using Pd/Pt/Au metal stacks is as low as 0.06 -mm. Electron-beam lithography (EBL) was utilized to pattern gates with a length of 0.1 m. The gate recess was done by a wet- etching technique. The gate metals were deposited on the InAlAs layer. After gate metal definition, devices were fully passivated by a nitride deposited by plasma-enhanced chemical vapor deposition (PECVD). The remaining processes for NG’s AlSb/InAs HEMT LNAs, such as thin-film resistors (TFRs), metal-insulator-metal capacitors (MIMCAPs), are identical to those of NG’s space- qualified 3-inch InP HEMT technology [10]. The design of NG’s 436 978-1-4244-2050-6/08/$25.00 ©2008 IEEE IEEE CFP08RPS-CDR 46 th Annual International Reliability Physics Symposium, Phoenix, 2008

Transcript of [IEEE 2008 IEEE International Reliability Physics Symposium (IRPS) - Phoenix, AZ, USA...

Page 1: [IEEE 2008 IEEE International Reliability Physics Symposium (IRPS) - Phoenix, AZ, USA (2008.04.27-2008.05.1)] 2008 IEEE International Reliability Physics Symposium - Degradation mechanisms

DEGRADATION MECHANISMS OF 0.1 m AlSb/InAs HEMTS FOR ULTRALOW-POWER APPLICATIONS

Y.C. Chou, J. M. Yang, M. D. Lange, S. S. Tsui, D. L. Leung, C. H. Lin, M. Wojtowicz, and A. K. Oki

Northrop Grumman Space Technology One Space Park, Redondo Beach, CA 90278

Tel: 310-812-3550; Fax: 310-813-0418; E-mail: [email protected]

ABSTRACT

The degradation mechanisms of 0.1 m AlSb/InAs HEMTs subjected to elevated-temperature lifetesting at three temperatures in N2 atmosphere were investigated. Device degradation exhibits the increase of non-pinch-off drain current (IDS), the decrease of transconductance (gm) and the gate current (IG) increase. The IGincrease was found to correlate with material degradation on the gate-recess and Al0.7Ga0.3Sb-mesa-floor surfaces. Higher oxygen content was detected on these surfaces, indicating that they were modified by oxidation, which resulted in the IG increase. Despite the degradation observed in 0.1 m AlSb/InAs HEMTs, the three-temperature lifetesting shows that the activation energy (Ea) is approximately 1.5 eV and demonstrates a median time to failure (MTF) of 2 106 hours at Tjunction of 85 °C. This reliability result is essential for successful insertion of AlSb/InAs HEMTs into systems with ultralow-power requirements. Moreover, ohmic-metal lateral diffusion of Pd and Au elements was observed. To avoid potential ohmic-metal-lateral-diffusion induced device failure, lifetesting temperatures were kept below 190 °C in this investigation.

INTRODUCTION

AlSb/InAs HEMT technology has proven to be viable next-generation for low-noise, low-power, and high-speed applications due to the superior electronic properties of the InAs channel, such as electron mobility and peak velocity. The electron mobility and peak velocity are nearly two times larger than those of InAlAs/InGaAs/InP HEMTs with InxGa1-xAs channels [1]. The combinations of high peak electron velocity (~ 4 107 cm/s) at low electric field, and high channel conductivity, enable operation of AlSb/InAs HEMTs at very low drain voltage. Accordingly, AlSb/InAs HEMTs have become critical elements for large-aperture phased-array applications with ultralow-power requirements [2].

The design of a large-aperture phased-array system is essentially power constrained. With the quantities of low-noise amplifier (LNA) elements ranging from 105 to 106, reduction of total power dissipation in the system is a big challenge. A decrease of dc-power dissipation in LNAs from 10 mW to 1 mW would result in a dc-power reduction on the order of 1 to 10 kW. This is essential for a phased-array system with requirements of small size, light weight and low cost. As a result, AlSb/InAs HEMT technology has come into the mainstream of research and development recently, owing to its superior electronic properties for ultralow-power applications.

To date, researchers have demonstrated superior microwave performance of LNAs at X-band [2-3] and W-band [4-5] frequencies using AlSb/InAs HEMTs. Furthermore, the manufacturability of AlSb/InAs HEMT LNA technology has been demonstrated [6]. However, the reliability evaluation of AlSb/InAs HEMT LNAs is still lacking. Recently, reliability evaluation of AlSb/InAs LNAs was reported, for the first time, by Chou et. al [7]. Nevertheless, comprehensive investigation of degradation mechanisms of 0.1 m

AlSb/InAs HEMTs subjected to elevated-temperature lifetesting had still not been performed. In order to improve reliability performance of AlSb/InAs HEMTs to assure successful insertion for phased-array applications, it is important to understand the degradation mechanisms of AlSb/InAs HEMTs subjected to elevated-temperature lifetest.

In this study, we performed three-temperature lifetesting to investigate degradation mechanisms of 0.1 m AlSb/InAs HEMTs. As mentioned above, device degradation exhibits the increase of non-pinch-off IDS, the decrease of gm and the IG increase. The IGincrease was found to correlate with material degradation on the gate-recess and Al0.7Ga0.3Sb-meas-floor surfaces. Higher oxygen content was detected on these surfaces, indicating modification by oxidation, which resulted in the IG increase. In addition, while gate-sinking induced degradation was not observed on AlSb/InAs HEMTs, ohmic-metal lateral diffusion of Pd and Au elements was observed. Furthermore, Northrop Grumman (NG) has developed a wafer-level-packaging (WLP) technology to provide hermetic sealing of AlSb/InAs HEMT LNAs. This enables prevention of oxygen incorporation into the AlSb/InAs HEMT materials, thus reducing the potential for reaction with oxygen. Consequently, reliability performance could be improved.

AlSb/InAs HEMT TECHNOLOGY

The cross section of a 0.1 m AlSb/InAs HEMT is shown in Figure 1. The AlSb/InAs structures were grown by molecular beam epitaxy (MBE) on 3-inch semi-insulating GaAs substrates. The AlSb/InAs structures typically exhibit mobility of 25,000 to 30,000 cm2/V-s and electron sheet density of 1.2 0.3 1012 cm-2 at 300 K. The lattice mismatch of the InAlAs barrier to the underlying AlSb barrier is as high as 5.5%; but because the channel is grown earlier, its quality is not affected by relaxation of the InAlAs. As a result, the thickness of the InAlAs barrier is kept below 40 Å in this device structure in order to preserve the material quality. Detailed information regarding the design of this structure can be found in previous publications [1, 8].

The fabrication processes of NG’s AlSb/InAs HEMTs were reported previously [6]. The device mesas were formed by a BCl3/Ar-based inductively-coupled-plasma (ICP) etching technique that etches the materials down to the Al0.7Ga0.3Sb buffer layer. The details of ICP etching were reported previously [9]. The ohmic contact resistance achieved using Pd/Pt/Au metal stacks is as low as 0.06 -mm. Electron-beam lithography (EBL) was utilized to pattern gates with a length of 0.1 m. The gate recess was done by a wet-etching technique. The gate metals were deposited on the InAlAs layer. After gate metal definition, devices were fully passivated by a nitride deposited by plasma-enhanced chemical vapor deposition (PECVD). The remaining processes for NG’s AlSb/InAs HEMT LNAs, such as thin-film resistors (TFRs), metal-insulator-metal capacitors (MIMCAPs), are identical to those of NG’s space-qualified 3-inch InP HEMT technology [10]. The design of NG’s

436978-1-4244-2050-6/08/$25.00 ©2008 IEEE IEEE CFP08RPS-CDR 46th Annual International Reliability

Physics Symposium, Phoenix, 2008

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AlSb/InAs HEMT LNAs is coplanar. Therefore, no backside process is required.

DC ELEVATED TEMPERATURE LIFETEST

The AlSb/InAs HEMTs were mounted on 16 PIN dual-in-line (DIP) packages for d.c. elevated-temperature lifetesting to investigate degradation mechanisms. Temperature step stress lifetest results suggest that oven ambient temperature be kept below 190 °C to avoid failures of AlSb/InAs HEMTs. As a result, three-temperature lifetesting at Tambient of 150, 160, and 170 °C, with 11 samples for each temperature, was performed in N2 atmosphere. The devices were stressed at VDS=0.2 V and IDS=150 mA/mm with total power dissipation of 2.4 mW. Comprehensive dc characterization, including gate-source/gate-drain diode characteristics, characteristics of IDS and gm versus gate voltage (VGS), and d.c. current-voltage (I-V)characteristics, was performed at room temperature on the samples after each interval of lifetesting. A representative evolution of IDS,gm, and IG is shown in Figure 2. It was found that the magnitude of non-pinch-off IDS is approximately equal to the IG on an AlSb/InAs HEMs after stress. Therefore, the increase of non-pinch-off IDS, and the degradation of gm shown in Figure 2 were observed. These signatures of electrical degradation of AlSb/InAs HEMTs differ from those of GaAs pHEMTs and InP HEMTs reported in previous publications [11, 12].

RESULTS AND DISCUSSIONS

Scanning-transmission electron microscopy (STEM) was used to examine the physical evidence of a degraded AlSb/InAs HEMT. Figure 3 shows a STEM image on the gate-semiconductor interface (region A) and gate-recess surfaces (regions B). As shown in Figure 3, no gate sinking into the semiconductor material was observed. This is attributed to the lower channel temperature generated during lifetesting of AlSb/InAs HEMTs, owing to their ultralow-power operation.

To explore potential degradation of the material on the gate- recess surfaces (regions B), a high resolution energy-dispersive analysis with X-ray (EDAX) was performed on locations 1 (control) and 2 (affected region). The oxygen signal from location 2 shown in Figure 4 was higher than that detected from location 1. This indicates that the gate-recess surfaces of AlSb/InAs HEMTs subjected to elevated-temperature lifetesting could be affected due to reaction with oxygen. The oxygen is probably incorporated into the AlSb/InAs HEMTs from the atmosphere.

contact capSource Drain

InAs channelAlSb barriern-type InAs: Si dopedAlSb barrierInAlAs barrier: mismatch ~ 5.5%

gate

AlSb barrier

GaAs buffer

GaAs substrate

InAs

SiNxpassivation

Al0.7Ga0.3Sb buffermesa floor

contact capSource Drain

InAs channelAlSb barriern-type InAs: Si dopedAlSb barrierInAlAs barrier: mismatch ~ 5.5%

gate

AlSb barrier

GaAs buffer

GaAs substrate

InAs

SiNxpassivation

Al0.7Ga0.3Sb buffermesa floor

FIGURE 1. Cross section of a 0.1 m AlSb/InAs HEMT fabricated on a 3-inch GaAs substrate. The Al0.7Ga0.3Sbsurface of the mesa-floor is shown.

0.06 m

Nitride

Gate

Nitride

InAs channel

AB B

1 2

0.06 m

Nitride

Gate

Nitride

InAs channel

AABB BB

1 2

FIGURE 3. The gate and gate-recess STEM micrograph of a degraded 0.1 m AlSb/InAs HEMT, showing no evidence of gate-sinking-induced degradation. However, the gate-recess surfaces were affected by oxidation.

Oxygen

Al

Sbaffected region

Oxygen

Al

Sbaffected region

FIGURE 4. EDAX spectrum of a degraded 0.1 m AlSb/InAs HEMT on location 2 of Figure 2, showing the oxygen presence in the upper AlSb layer.

at VDS= 0.2 V: before: after

IDS

gm

0

200

400

600

800

1000

1200

-0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0VGS (Volts)

I DS

(mA

/mm

). g m

(mS/

mm

)

-75

-62.5

-50

-375

-25

-12.5

0Ig (before stress)

Ig(after stress)

I G(m

A/m

m)

-87.5

at VDS= 0.2 V: before: after

at VDS= 0.2 V: before: after

IDS

gm

0

200

400

600

800

1000

1200

-0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0VGS (Volts)

I DS

(mA

/mm

). g m

(mS/

mm

)

-75

-62.5

-50

-375

-25

-12.5

0Ig (before stress)

Ig(after stress)

I G(m

A/m

m)

-87.5

FIGURE 2. Evolutions of IDS, gm, and IG characteristics in a 0.1 m AlSb/InAs HEMT subjected to 170 °C lifetesting.

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Analysis by STEM was also performed on the mesa-floor region in Figure 1 to explore whether the Al0.7Ga0.3Sb buffer after elevated-temperature lifetesting could be affected. Figure 5 shows a STEM image of the Al0.7Ga0.3Sb buffer layer on the mesa-floor (as shown schematically in Fig. 1). Note that the STEM images of the upper and lower portions of the Al0.7Ga0.3Sb buffer are quite different. Measurements by EDAX were performed on location 3 of the upper Al0.7Ga0.3Sb portion, and location 4 of the lower Al0.7Ga0.3Sb buffer layer to reveal what could cause the difference in the STEM image. The oxygen signal from location 3, shown in Figure 6, is higher than that from location 4. According to the data in Figures 4 and 6, the oxygen incorporating into the AlSb/InAs materials during elevated-temperature lifetesting may modify the gate-recess and/or Al0.7Ga0.3Sb-mesa-floor surfaces, therefore increasing the gate leakage along these surfaces.

To understand the IG evolution of AlSb/InAs HEMTs subjected to elevated-temperature lifetesting, IG was also monitored with a hot chuck d.c. stress system. As shown in Figure 7, gradual IG increase was observed on an AlSb/InAs HEMT device subjected to a hot chuck d.c. stress at Tambient of 180 °C. Because the increase of IG will become part of IDS, VGS, as shown in Figure 8, needs to be set at gradually more negative values to maintain constant IDS stress. The electrical results observed in Figures 7 and 8 are consistent with the physical degradations on gate-recess and/or Al0.7Ga0.3Sb mesa-floor surfaces of a degraded AlSb/InAs HEMT. Despite the surface degradation observed in 0.1 m AlSb/InAs HEMTs, the three-temperature lifetesting still exhibits Ea of approximately 1.5 eV and demonstrates MTF of 2 106 hours at Tjunction of 85 °C, which is important for successful insertion of AlSb/InAs HEMT LNAs with ultralow-power requirements [7].

Nitride

Al0.7Ga0.3Sb cap layer

Al0.7Ga0.3Sb buffer layer

0.06 m

4

3

NitrideNitride

Al0.7Ga0.3Sb cap layer

Al0.7Ga0.3Sb buffer layer

0.06 m

4

3

Nitride

FIGURE 5. A STEM image of a degraded AlSb/InAs HEMT on the Al0.7Ga0.3Sb-mesa-floor surface (shown schematically in Fig. 1)

Al

Sb

GaOxygen

EDX onlocation 3

Al

Sb

GaOxygen

EDX onlocation 3

FIGURE 6. An EDAX spectrum of a degraded 0.1 mAlSb/InAs HEMT from location 3 in Fig. 5, showing the oxygen presence in the upper portion of the Al0.7Ga0.3Sb buffer layer.

-6

-5

-4

-3

-2

-1

0

0 40 80 120 160 200

Elapsed Stress Time (hours)

I G(m

A) a

t 180

°C

Tambient= 180 °C

Stress conditions:VDS= 0.2 VIDS= 150 mA/mm

-6

-5

-4

-3

-2

-1

0

0 40 80 120 160 200

Elapsed Stress Time (hours)

I G(m

A) a

t 180

°C

Tambient= 180 °C

Stress conditions:VDS= 0.2 VIDS= 150 mA/mm

FIGURE 7. IG evolution of a 0.1 m AlSb/InAs HEMT subjected to 180 °C lifetesting.

-0.2

-0.8

-0.7-0.6

-0.5

-0.4-0.3

0 40 80 120 160 200Elapsed Stress Time (hours)

V GS

(V) a

t at1

80 °C

Tambient= 180 °C

Stress conditions:VDS= 0.2 VIDS= 150 mA/mm

-0.2

-0.8

-0.7-0.6

-0.5

-0.4-0.3

0 40 80 120 160 200Elapsed Stress Time (hours)

V GS

(V) a

t at1

80 °C

Tambient= 180 °C

Stress conditions:VDS= 0.2 VIDS= 150 mA/mm

FIGURE 8. VGS evolution of a 0.1 m AlSb/InAs HEMT subjected to 180 °C lifetesting.

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The forward- and reverse-diode I-V characteristics shown in Figure 9 are from the gate Schottky junction of an AlSb/InAs HEMT after the stress shown in Figures 7 and 8. Note that both forward and reverse IG exhibit significant increase after stress. From the data in Figure 3, no detectable Schottky junction degradation was observed. Therefore, we believe that the increase of IG does not originate from the gate. It is likely to be from the gate-recess and/or Al0.7Ga0.3Sb-mesa-floor surfaces of a degraded AlSb/InAs HEMT due to their reaction with oxygen as substantiated in Figures 4 and 6.

Furthermore, STEM was performed on the ohmic-metal region to look for any physical evidence of ohmic-metal degradation. As shown in Figure 10, ohmic-metal lateral diffusion was observed on both the source and drain sides of an AlSb/InAs HEMT subjected to elevated-temperature lifestesting. The STEM image of ohmic-metal on a virgin sample does not exhibit the same amount of ohmic-metal lateral diffusion as does a sample after lifetesting. However, a small degree of ohmic-metal lateral diffusion was observed on a virgin sample, which was induced after an ohmic-metal anneal. The EDAX was performed on locations 5 and 6 shown in Figure 10. No ohmic-metal lateral diffusion was detected on location 6. Figure 11 identifies that the Pd and Au elements contribute to the ohmic-metal lateral diffusion there. Further ohmic-metal lateral diffusion towards the gate could lead to device failure. As a result, lifetesting temperatures were kept below 190 °C to avoid potential ohmic-metal-lateral-diffusion induced device failure. (Note that the Cu signal shown in Figure 11 is induced by a STEM sample grid.)

CONCLUSIONS

For the first time, degradation mechanisms of 0.1 m AlSb/InAs HEMTs were investigated. Device degradation exhibits the increase of IDS, the decrease of gm and the IG increase. The IG increase was found to correlate with material degradation on the gate-recess and Al0.7Ga0.3Sb-mesa-floor surfaces owing to the reaction with oxygen. Additionally, ohmic-metal lateral diffusion of Pd and Au was observed. Furthermore, a wafer-level packaging technology was developed that provides hermetic sealing to prevent oxygen from incorporating into the AlSb/InAs HEMT materials, therefore improving reliability performance.

ACKNOWLEDGEMENT

This work was supported by DARPA under contract number FA8750-06-C-0051. The authors would like to thank Dr. Mark Rosker (DARPA) and all the engineers and technicians at Northrop Grumman who contributed to this work

REFERENCES

[1] J. B. Boos, W. Kruppa, B. R. Bennett, D. Park, S. W. Kirchoefer, R. Bass, and H. B. Dietrich, “AlSb/InAs HEMTs for Low-Voltage, High-Speed Applications”, Vol. 45, 1998, pp. 1869-1875.

[2] W. R. Deal, R. Tsai, M. D. Lange, J. B. Boos, B. R. Bennett, and A. Gutierrez, “A Low Power/Low Noise MMIC Amplifiers for Phased-Array Applications Using InAs/AlSb HEMT”, the Technical Digest of IEEE IMS Symposium, 2006, pp. 2051-2054.

[3] B. Y. Ma, J. B. Hacker, J. Bergman, P. Chen, G. Sullivan, G. Nagy, and B. Brar, “Ultra-Low-Power Wideband High Gain InAs/AlSb HEMT Low Noise Amplifiers”, the Technical Digest of IEEE IMS Symposium, 2006, pp. 73-76.

65

0.15 m

Ohmicmetal

Nitride65

0.15 m

Ohmicmetal

Nitride

FIGURE 10. Au ohmic STEM micrograph of a degraded AlSb/InAs HEMT, showing physical evidence of ohmic-metal lateral diffusion.

Pd

Au

Al Sb

EDX on location 5

Au

Cu

Pd

Au

Al Sb

EDX on location 5

Au

Cu

FIGURE 11. The EDAX spectrum from a degraded 0.1 mAlSb/InAs HEMT at location 5 in Figure 10, exhibiting evidence of Pd and Au ohmic-lateral diffusion along the upper AlSb material.

10-9

10-8

10-7

10-6

10-5

10-4

10-3

10-2

-0.5 -0.3 -0.1 0.1 0.3 0.5VGS Volts)

I G(A

mps

) before

after

10-9

10-8

10-7

10-6

10-5

10-4

10-3

10-2

-0.5 -0.3 -0.1 0.1 0.3 0.5VGS Volts)

I G(A

mps

) before

after

FIGURE 9. Evolution of forward and reverse IG characteristics of a 0.1 m AlSb/InAs HEMT subjected to 180 °C lifetesting.

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[4] W. R. Deal, R. Tsai, M. D. Lange, J. B. Boos, B. R. Bennett, and A. Gutierrez, “A W-band InAs/AlSb Low-Noise/Low-Power Amplifier,” IEEE Microwave and Wireless Components Lett., Vol. 15, 2005, pp. 208-210.

[5] W. R. Deal. R. Tsai, M. Lange, J. B. Boos, B. R. Bennett, R. Grundbacher, L. J. Lee, K. Padmanabhan, P. H. Liu, C. Namba, P. Nam, and A. Gutierrez, “A 110 GHz AlSb/InAs MMIC Amplifier”, the Technical Digest of GaAs IC Symposium, 2004, pp. 301-304.

[6] Y. C. Chou, J. M. Yang, C. H. Lin, J. Lee, M. Lange, R. Tsai, P. Nam, M. Nishimoto, A. Gutierrez, H. Quach, R. Lai, D. Farkas, M. Wojtowicz, P. Chin, M. Barsky, and A. Oki, “Manufacturable and Reliable 0.1 m AlSb/InAs HEMT MMIC Technology for Ultra-Low Power Applications”, the Technical Digest of IEEE IMS Symposium, 2007.

[7] Y. C. Chou, D. L. Leung, W-B Luo, J. M. Yang, C. H. Lin, M. Lange, Q. Kan, D. S. Farkas, J. B. Boos, B. R. Bennett, A. L. Gutierrez, D. C. Eng, M. Wojtowicz, A. Oki, and T. Block, “Reliability Evaluation 0.1 m AlSb/InAs HEMT Low Noise Amplifiers for Ultralow-Power Applications”, the Technical Digest of IEEE ROCS Workshop, 2007.

[8] B. R. Bennett, R. Magno, J. B. Boos, W. Kruppa, and M. G. Ancona , “Antimonide-based Compound Semiconductors for Electronic Devices: A Review”, Solid-State Electronics, Vol. 49, 2005, pp. 1875-1895.

[9] P. Nam, R. Tsai, M. Lange, W. Deal, J. Lee, C. Namba, P. Liu, R. Grundbacher, J. Wang, M. Barsky, A. Gutierrez-Aitken, and S. Olson, “Shallow Mesa Isolation of AlSb/InAs HEMT with AlGaSb Buffer Layer Using Inductively Coupled Plasma Etching”, the Technical Digest of GaAs Mantech Symposium, 2003.

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