Anomalous Positive-Bias Temperature Instability of High-κ/Metal Gate nMOSFET Devices with Dy2O3 Capping

Robert O’Connor , Vincent S. Chang +, Luigi Pantisano, Lars-Åke Ragnarsson, Marc Aoulaiche, Barry O’Sullivan, Christoph Adelmann, Sven Van Elshocht, Peer Lehnen x. HongYu Yu, Guido Groeseneken*.

IMEC, Leuven, Belgium, (*) also K.U. Leuven, Leuven, Belgium, (+) TSMC, Hsinchu, Taiwan, (x) Aixtron assignee at IMEC.

INTRODUCTION

Recently, thin rare-earth oxide dielectric capping layers between the high-κ and metal gate have been used to modulate the threshold voltage (Vt) of MOSFETs [1].

In Dy2O3-capped high-k based devices, we observe an anomalous PBTI behavior where the Vt decreases during stress. Results suggest that there are two competing mechanisms –diffusion of preexisting positively-charged species and electron trapping. The charged species is likely located in the mixed high-κ dielectric and associated with the interaction between the host dielectric, cap, and metal gate.

DEVICES

HfSiON (2.5 nm) was formed on ~1-nm chemical oxide by ALD. A closed, 1-nm Dy2O3 film was deposited by AVD on HfSiON followed by 10nm TaN and100-nm poly Si deposition. The PBTI was measured on 10 × 10-μm2 transistors at 125°C unless specified otherwise. A novel pulse-like stressing technique with a sense time of 100 ms was used to minimize the recovery effect and to ensure that both the permanent and relaxing components of the PBTI were probed effectively. Transmission-electron microscopy (TEM) images (not shown) of Dy2O3-capped HfSiON stacks show no interface between the cap and HfSiON, suggesting that the two layers intermix. The mixed high-κ (2.9 nm) is thinner than the as-deposited stack (~3.5 nm) possibly due to the interaction between the high-κ and the metal. The interfacial layer (IL) thickness remains unchanged as compared to the as-deposited case (~1 nm), suggesting that Dy diffusion into the IL is unlikely.

ANOMALOUS BTI

The effect of Dy2O3 capping on the PBTI characteristics is shown in Fig. 1. Id-Vg curves (inset) show that after stress, the Vt

of Dy2O3-capped HfSiON decreases by ~120 mV. This is opposite to the common observations from HfSiON where the Vt

increases due to electron trapping [2]; the Vt of the HfSiON reference increases only negligibly (~2 mV) after the stress.

Fig. 1 also shows that ΔVt of Dy2O3-capped layers saturates after 10000s. The saturation also occurs at high oxide electric fields (Eox), suggesting that the defects causing the negative ΔVt are pre-existing. The unaffected mobility and sub-threshold slopes (Fig.1, inset) suggest that most defects are located away from the channel, likely in the mixed high-κ.

To examine the possible origins of the defects responsible for these observations, the ΔVt was measured under positive andnegative stress biases at various temperatures. In the case of hole trapping or electron de-trapping, a weak temperature dependence of ΔVt is expected [2]. However, Fig. 2(a) shows a strong temperature dependence and high activation energy (EA), thusneither mechanism alone can explain the observations. The positive ΔVt under negative stress bias suggests that hole trapping is unlikely. In contrast, the symmetric ΔVt at the opposite polarities and the strong temperature dependence indicate that the diffusion of positively-charged species is a likely mechanism.

At lower temperatures, shown in Fig. 2(b) (-23°C and below), the Vt increases with time and gate overdrive at both stress polarities. It indicates that during the stress, the Vt is determined

by two competing mechanisms as shown in Fig. 3(a). At low temperature (T1) where the diffusion of the positively-charged species is suppressed, electron trapping dominates, leading to a regular Vt increase. At higher temperatures (T2 and T3), the diffusion of the positively-charged species is enhanced and becomes dominant, resulting in Vt decreasing.

To confirm the existence of the positively-charged species, the device was stressed twice and relaxed between the two stresses by removing the gate bias. Fig. 3(b) shows that the Vt during the second stress behaves identically to that during the first stress. The ID-VG characteristics (not shown) indicate full Vt recovery. This reversible Vt behavior also suggests the diffusion of charged species.

SENSITIVITY TO HOT CARRIERS

Substrate hot electron injection (SHEI) was used to further investigate the behavior. The technique allows two injection modes, where at low Vwell, primarily interface traps are created and at high Vwell bulk trap creation is dominant [3].

Under SHEI at room temperature (figure 4), Vt is seen to rise with increasing stress. However, for a given Qinj, the largest magnitude is seen for the lowest field condition. When the SHEI is turned on, the Si/SiO2 interface is exposed to conditions which preferentially degrade the interface and cause significant negative trapping, increasing the positive Vt shift as seen for the Vg-Vt=1.5V case. If the gate voltage is now increased, there is only an incremental contribution (in comparison with the dominance of SHEI) to the positive Vt shift. However, increasing the oxide field assists in the diffusion of the positively charge species in the stack. As seen for Vg-Vt=2V and 2.5V, the net effect of the addition of the two components is that we see seemingly ‘less’ shift for increasing field or, more correctly, we observe the dominance of the diffusion at higher fields.

In figure 5, the SHEI data is extrapolated back to the low Qinj

regime corresponding to very short stress times. There is a clear crossover point. At very low values of Qinj (stress time <1s) the situation is reversed and normal behaviour is observed. The Vt

shift is positive and increases with increasing voltage. However, the change in diffusion rate of the positively charged species at different fields means that the effective defect generation rates are different for changing Vg. In this case, above Qinj=1x10-7C positive trapping becomes dominant over the conventional BTI effect.

CONCLUSION

Dy2O3 capping effectively reduces Vt, but results in anomalous PBTI behavior where the Vt decreases during stress. Systematic measurements at various electric fields, stress bias polarities, and temperatures, and SHEI studies suggest that the Vt is determined by two competing mechanisms – diffusion of positively-charged species and electron trapping – which dominate at high and low temperatures, respectively.

Data shows the anomalous behaviour is not seen in AVD Dy2O3 with Ni-based fully-silicided (FUSI) gate [4] nor elsewhere. Therefore we speculate that the origin of thepositively charged species is likely associated with the interactions between the host dielectric, cap, and metal gate, rather than the properties of the cap material itself.

671978-1-4244-2050-6/08/$25.00 ©2008 IEEE IEEE CFP08RPS-CDR 46th Annual International Reliability

Physics Symposium, Phoenix, 2008

Figure 1: Vt shift (Vt) and effective charge density (Neff) of Dy2O3-capped HfSiON as a function of stress time with various Eox. The inset shows the ID-VG characteristics of uncapped and Dy2O3-capped HfSiON before (dash line) and after (solid line) a stress at 9 MV/cm for 2047 s.

Figure 2: Vt as a function of stress time of Dy2O3-capped HfSiON stressed under positive or negative gate biases at various temperatures: (a) 25 to 175°C with a gate overdrive (VG–Vt or VG–Vfb) of 1 V. The activation energy (EA) is determined from the Vt after a 511-s stress. (b) -73 to 27°C with gate overdrive of 2 or 2.2 V.

Figure 3: (a) Schematic diagram of the two mechanisms responsible for the Vt instability of Dy2O3-capped HfSiON stressed at positive gate bias and various temperatures (T1 < T2 < T3). (b) Vt of a Dy2O3-capped HfSiON device stressed twice at 125°C and 9 MV/cm. Between the two stresses, the gate bias was removed for 1200 s to relax the device.

0

100

200

300

400

500

1.00E-08 1.00E-07 1.00E-06 1.00E-05 1.00E-04

Qinj (C)

DVt

(mV

)

1.5V

2V

2.5V

Vg-Vt=

Closed: CVS

Open: Vw ell=-1V

Figure 4: Substrate hot electron injection measurements which preferentially degrade the interface yield conventional positive Vt

shift results, however when the Vg is increased, the diffusion of the positive species leads to an effective lowering of the Vt shift, due to the competition between the two processes.

10

100

1000

1.E-09 1.E-07 1.E-05 1.E-03

Qinj (C)

DVt (

mV

)

2.5V

2V

1.5V

Vg-Vt=

Vwell=-1V

1.5nm cap

Figure 5: Extrapolation of the PBTI behaviour to low stress time shows that normal PBTI behaviour is observed in the timeframe before the diffusion of the positively charged species begins to dominate the behaviour.

References:[1]Kirsch et al, “Band edge n-MOSFETs with high-k/metal gate stacks scaled to EOT=0.9nm with excellent carrier mobility and high temperature stability,” in IEDM Tech. Dig., 2006.[2]M. Aoulaiche et al, “Polarity dependence of bias temperature instabilities in Hf(x)Si(1-x)ON/TaN gate stacks,” in Proceeding of ESSDERC, Grenoble, France, 2005, pp. 197-200.[3] R O’Connor et al, “Electron energy dependence of defect

generation in high-k gate stacks”, Accepted to SISC 2007.[4] H. Y. Yu et al, “Low Vt Ni-FUSI CMOS Technology using a DyO cap layer with either single or dual Ni-phases,” in VLSI Symp. Tech. Dig., 2007.

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