50µm Pitch Pb-Free Micro-bumps by C4NP Technology

Bing Dang, Da-Yuan Shih, Stephen Buchwalter, Cornelia Tsang, Chirag Patel, John Knickerbocker, Peter Gruber, Sarah Knickerbocker*, John Garant*, and Krystyna Semkow*, Klaus Ruhmer**, Emmett Hughlett**

IBM T. J. Watson Research Center,

1101 Kitchawan Road, Yorktown Heights, New York 10598 * IBM Systems and Technology Group

** SUSS MicroTec, Inc., Waterbury Center, VT, United States Email:dangbing@us.ibm.com

Abstract

Controlled collapse chip connection new process (C4NP) is currently used in IBM manufacturing for all 300 mm Pb-free wafer bumping for flip chip packages. In this study, the extendibility of C4NP technology to ultra fine pitch applications has been explored. Reusable C4NP glass molds were fabricated and characterized for 50µm pitch application. Mold fill and wafer transfer with Pb-free solders have been demonstrated using both 200mm and 300mm wafers in a manufacturing environment. Significant improvement in bump yield was achieved for these early demonstations of fine pitch interconnections through process optimization and contamination control. Challenge in wafer inspection metrology is discussed for the 50µm pitch micro-bumps. Mechanical strength of the C4NP micro-bumps has been characterized using test dies with a full area array of micro-bumps.

Introduction As feature size scales down, the number of transistors and

interconnects on a chip has increased continuously. As a result, the number of chip to package input/output (I/O) interconnects have also increased significantly in the past decades [1]. On the one hand, flip-chip I/O pitch is being reduced continuously to meet the requirement of I/O counts in high-performance and high-bandwidth applications. On the other hand, fine-pitch wire bond interconnection in low-cost and memory applications needs to be replaced by fine-pitch area interconnection due to the performance limitation of wire-bond technology in high-frequency regime. Furthermore, fine pitch interconnection is highly demanded for 3D integration of semiconductor chips because of the benefits in power distribution, signal latency as well as chip to chip communication bandwidth, etc. Therefore, manufacturing of fine pitch controlled-collapse-chip-connection (C4) (50µm pitch or below) interconnects needs to be explored.

C4 bumps can be produced by a number of methods, such as paste screening [2], masked evaporation [3], photolithographic electroplating [4], etc. However, not all of the C4 bumping technologies are extendable to fine-pitch applications for volume production at low cost. Recently, C4 – New Process (C4NP) technology has been developed and adopted by IBM in manufacturing production of 300 mm Pb-free solder bumped wafers [5]. Compared to the other bumping technologies, C4NP has demonstrated several advantages that include solder choice flexibility (easy change to desired solder materials and compositions), high-volume

manufacturability, environmentally friendly operation, ( “dry” process, no plating chemicals involved or waste to be disposed), and low cost.

In this study, the extendibility of C4NP technology to ultra fine-pitch application has been demonstrated from the perspectives of mold manufacturing, patterning and fabrication of UBM (Under Bump Metallurgy) capture pad, mold fill with Pb-free solders and bump transfer from glass mold to wafers, as well as high-volume inspection using a test vehicle containing a full area array of micro-bumps at 50µm pitch. The 12” x 13” glass plates were successfully filled with SnAg solder in various atmospheres. The fill quality and yield were shown to improve significantly with a controlled atmosphere, optimized scan speed and contamination control. For the first time, micro C4 solder transfer is successfully demonstrated for both 200mm wafers and 300mm wafers using a manufacturing tool. The initial experiment achieved very high yield of good chips, each containing ~11,000 bumps at 50µm pitch. Initial micro C4 volume variation of ~ 8% was measured. Defect types and root causes were characterized. The challenge and methodology in high-speed inspection for the large number of micro C4 bumps (~ 9 millions) will be discussed.

Characterization of glass molds for ultra fine-pitch micro-bumps

C4NP glass molds are fabricated using borofloat glass plates, which have a coefficient of thermal expansion (CTE) closely matching that of the silicon wafer. Photolithographic patterning and wet chemical etching processes are used to create cavities into the 12” x 13” glass plate that mirror-images the UBM (under-bump-metallurgy) pads and pitch on the 300 mm silicon wafers. To achieve good volume uniformity on all the cavities with acceptable manufacturing yield, the surface of the glass plate is first thoroughly cleaned. After glass cleaning, bi-layer blanket Cr/Cu films are subsequently sputtered onto the glass surface, followed by spray-coating a relatively thick photoresist layer on the Cu surface. The patterned Cu/Cr film serves as an etch mask to isotropically etch the cavities.

Figure 1 shows the SEM image of typical etched cavities in the C4NP glass mold. As illustrated in Figure 2, there are three major types of non-flatness. The type 1 is related to localized waviness. The type 2 is the global waviness, which can largely compensated for during the solder transfer process. The type 3 is from the non-uniformity in the glass mold thickness (wedge shape), which again can be overcome during transfer in the solder transfer tool.

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Figure 1. C4NP glass mold with etched cavities

Figure 2. Challenge in non-flatness for the glass molds For the first time, the C4NP molds with nearly 9 millions

of cavities at 50 µm pitch have been fabricated by a qualified vendor through their standard and proprietary manufacturing process. The molds were characterized for their defect level, thickness, planarity, and cavity dimensions. The results for a group of 4 molds are summarized in Table 1. Defects such as missing cavities or bad cavities were not detected for mold #1 and mold #2 through automated inspection. Mold #3 and #4 have a cavity defect rate less than 1 ppm. This early data demonstrates that there may be a path to high yield manufacturing for glass molds for micro-bumps.

However, cavity dimension, which controls volume uniformity can be sensitive to the etching process, and needs to be carefully controlled. For instance, the cavity volume of the mold #4 are significantly out of volume target (10,500~ 12,500 µm3) because the etching time is insufficient.

Meanwhile, the measured volume uniformity of the cavities in mold #2, #3 and #4 is excellent and less than 5%. Table 1. Micro bump mold cavity dimension as measured

MoldID

Depth(µm)

Mean Top Diameter (µm)

Mean Volume (x103 µm3)

Estimated 3σ volume uniformity

Visual inspection

1 13.6 39.9 11.9 8.0% 0 defect 2 14.0 40.1 12.3 4.6% 0 defect 3 13.9 40.0 12.1 4.8% <1ppm 4 8.8 32.6 5.4 3.7% <1ppm A key challenge for C4NP at 50µm can be illustrated in

Figure 3. In order to achieve solder transfer from mold to UBM pads on wafer, the reflowed solder stand-off height (∆h) above the mold surface should be higher than any potential non-flatness of a mold during transfer. As discussed above, the local non-flatness (type 1) can not be compensated by compression force during transfer. Fortunately, the estimated C4 stand-off height is larger than 13µm, which is well above the measured local non-flatness (<1.35µm) for all 4 molds, as summarized in Table 2.

Figure 3. Illustration of the challenge in cavity dimension control for micro bumps

The global non-flatness (type 2 and type 3) of the 4 molds

is also less than 8.9µm across 12” x 13” area, which can be accommodated by the solder transfer tool. Therefore, the stand-off height (∆h) of the reflowed micro C4 bumps can ensure a good contact between the C4 bumps in the mold cavities and the receiving pads on the wafer.

D2

D1

h

D

∆h

h

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Table 2. Estimated C4 stand-off height above mold surface and the measured non-flatness

Mold ID

Depth (µm)

C4 stand-off ∆h (µm)

Local non-flatness (µm)

Global non-flatness (µm)

1 13.6 14.7 < 0.9 < 7.3

2 14.0 14.6 < 1.35 < 7.7

3 13.9 14.6 < 0.95 < 6.4

4 8.8 13.0 < 1.12 < 8.9

Mold filling and wafers transfer in manufacturing environment

After the molds were manufactured and characterized, they were scanned beneath a solder injection head and the cavities were filled with molten solder to the top surface of the glass plates. The solder volume transferred to a wafer is determined by the cavity volume of the glass mold. All the molds were filled through the SUSS C4NP MFT (Mold Fill Tool) installed at IBM’s manufacturing facility. Solder bridging for standard C4s (pitch ≥150µm) does not require special care because the spacing between adjacent cavities is longer. However, bridging can be more sensitive for micro-bumps because of shorter spacing between cavities.

(a) O2/N2

(b) N2

Figure 4. Comparison of filled cavities under O2/N2 and N2 atmosphere

The solder for this experiment was a lead-free SnAg alloy and the mold filling was conducted under a controlled ambient. Through process optimization, ambient control and new mold design, we have demonstrated that bridging may be completely eliminated for the 50 µm pitch micro-bumps. Figure 4 compares the typical filling effect under N2/O2 ambient to that under pure N2 atmosphere. More solder bridging between adjacent cavities is observed under the N2/O2 mixture environment, while bridging was mostly eliminated under the pure N2 ambient.

Figure 5. Optical image of the transferred micro-bumps With the successfully filled molds, micro-bumps have

been transferred for both 200mm and 300mm wafers. As shown in Figure 5, the UBM is the sputtered TiW/Ni/Cu structure. With the aid of formic acid, excellent wetting is achieved for the Pb-free SnAg micro-bumps. The UBM pads are ~ 28 µm in diameter. An additional reflow was performed to reshape the micro-bumps and uniform bump heights were obtained, as shown in Figure 6. The reflowed micro-bump has a diameter of ~ 31 µm and the minimum space between adjacent bumps is around 19 µm. Figure 7 shows the high magnification SEM for the surface of a micro-bump. Typical wrinkle appearance can be observed for the high-Sn solder. With In lens detector, minimum oxide is observed, which confirms a clean solder surface.

Pre-transfer: Sputtered UBM

Post-transfer: micro-bumps

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Figure 6. SEM image of the C4NP micro-bumps

Figure 7. High-magnitude SEM image revealing little oxide

Wafer inspection metrology for 50µm pitch micro bumps Inspection after mold fill is a critical element for C4NP

technology because final C4 transfer yield is dependent on the mold filling yield. For bump pitch ≥150µm any defect in the filled mold will be caught by MIT (Mold-Inspection Tool). The mold will be recycled and refilled with solder, inspected again before transfer to achieve excellent bumping yield.

(a). 2D diameter inspection

(b) 3D height inspection

(c) Distribution of estimated volume of the micro-bumps Figure 8. Measured diameter and height distribution of the micro-bumps with high-resolution wafer inspection tool.

However, the tight pitch and the large total number of

bumps raise significant challenge for the inspection of micro-

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bumps at 50µm pitch. With the full area arrays, each test chip (6.5mm x 5.4mm) contains approximately 11,000 micro bumps and an 8” wafer contains ~9 million micro bumps in total. Thus, a high resolution is required for the inspection tool and a large memory is needed for data processing. Experiments indicated that resolution of the existing manufacturing mold inspection tool as well as the wafer inspection tool can not meet the new requirement for the micro-bumps at 50 µm pitch. As a result, the test C4NP bumped wafers are being evaluated using a higher-resolution for 2D and 3D metrology system with state-of-the-art technology. Figure 8 shows an example of the measured diameter and height distribution for the transferred micro bumps across a wafer. Table 2 summarizes the inspection results for the bump diameter and height and excellent uniformity is verified. The measured standard deviation is around 0.5µm and 1.5µm for the bump diameter and bump height respectively. The mean bump diameter and height variation from wafer to wafer is also very small. In addition, the bump volume was estimated based on the diameter and height measurement and was well correlated to the previously estimated mold cavity volume. The difference between the two estimated solder volumes is within 10%. Table 3. Summary of micro-bump transfer yield and dimensions C4 Diameter (µm)

Min Mean Max STD STD(%)

Wafer #1 32.7 34.2 35.4 0.5 1.5% Wafer #2 34.5 35.3 36.1 0.3 0.8% C4 height (µm)

Min Mean Max STD STD(%)

Wafer #1 16.8 19.8 22.6 1.4 7% Wafer #2 15.4 18.3 21.9 1.3 7%

Figure 9. A C4NP transferred wafer with ~9million micro-bumps at 50µm pitch. Due to the limitation of the memory size of the existing metrology tool, only 25% of chips on a wafer were scanned for data processing within each single pass. As shown in

Figure 9, each chip contains approximately 11,000 micro-bumps at 50µm pitch. For a wafer populated with full area array of micro bumps (~9millions), multiple scans were needed to process all the inspection data, which can largely increase the total inspection time. Therefore, this challenge still remains to be solved through further collaboration with a metrology tool vendor.

Chip assembly and mechanical characteristics of micro-bumps

With a precision flip chip bonder, the test chips with Pb-free SnAg C4NP micro bumps (~ 11,000) were joined on Si based substrates. Figure 10 shows the SEM of cross-section of a joined bump. A significant level of intermetallic compound (IMC) was observed, which suggests that the UBM composition needs to be optimized considering that the solder volume of a micro-bump is much smaller than a standard C4. Chip pull test was performed to verify the wettiblity, joint strength and failure mechanisms. During post pull test inspection, no bridging was observed for all the 11,000 micro-bumps, which indicates the success of the joining. The pull strength data is sensitive to the accuracy of the pull tester alignment. Therefore, the measured pull strength is only approximate. The average pull strength measured for the micro-bumps is around 3 gram-force, which is close to what is expected. In theory, when the diameter of a C4 scales by a factor of 1/3, its cross-section area of scales by a factor of 1/9 approximately. Thus, its strength should scales by a factor 1/9 approximately.

Figure 10. SEM of cross-section of the joined C4NP micro-bumps

Conclusions The extendibility of C4NP technology to ultra fine-pitch

application has been successfully demonstrated using a test vehicle with a full area array of micro-bumps at 50µm pitch for both 200mm and 300mm wafers. For the first time, high-yield C4NP glass mold fabrication has been demonstrated through manufacturing environment. Excellent yield and uniformity have been demonstrated for Pb-free C4NP transfer through manufacturing environment. The effect of various atmospheres on the mold fill quality and yield has been investigated. The fill quality and yield were shown to improve

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significantly with controlled atmosphere, scan speed, mold design and contamination control. Co-planarity less than ~1.5µm and volume variation less than ~8% was measured for the transferred micro-bumps across wafers. The challenge and methodology in high-speed inspection for the large number of micro C4 bumps (~ 9 millions) has been discussed.

Acknowledgments We would like to thank P. Andry, P. Laura, R. Horton, R.

Sirdeshmukh, at IBM research division and G. Advocate, L. Quellet, L. Belanger, L. Guerin, R. Kumar at IBM S&T G for their technical support. We would also like to acknowledge the management support of T. Chainer, D. Seeger, and T.C. Chen.

References 1. International Technology Roadmap for Semiconductors,

Assembly and Packaging, 2006. 2. V. Kripesh, et al., “Ultra-Fine Pitch Pb-free & Eutectic

Solder Bumping with Fine Particle Size Solder Paste for Nano Packaging,” ECTC, 2003.

3. Miller, L. F., “Controlled Collapse Reflow Chip Joining,” IBM J. Res. Dev., 13, 1969,

4. H. Gan, et al., “Pb-free Micro-joints (50 µm pitch) for the Next Generation Micro-systems: the Fabrication, Assembly and Characterization,” ECTC, San Diego, may/June 2006.

5. E.Laine, et al., “C4NP Technology for Lead Free Solder Bumping,” ECTC 2007, Reno, NV, May/June 2007.

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