A 57dB SFDR Digitally Calibrated 500MS/s Folding ADC in 0.18µm digital CMOS

Ivan Bogue and Michael P. Flynn University of Michigan

1301 Beal Avenue EECS Ann Arbor, MI 48109, USA

Abstract- A digitally calibrated 8-bit folding ADC incorporating redundancy and reassignment is described. Small, redundant folder and comparator circuits generate 1024 available zero-crossings. An entirely self-contained calibration engine selects 255 zero-crossings from the available set. Unselected circuits are powered down. The calibration breaks the link between ADC performance and analog accuracy, allowing small transistors to be used in the signal path. Fabricated in 0.18µm digital CMOS, the DNL of the uncalibrated ADC is 6.7LSB and 0.8LSB, before and after calibration, respectively. SFDR remains above 55dB up to a sampling rate of 550MS/s. The total die area is 1.2mm2.

I. INTRODUCTION

Random offsets in comparators and distortion and offsets in folders limit the performance of folding ADCs. Approaches to achieve accuracy include the use of large devices that match well, and analog or digitally-controlled trimming. This paper introduces a digital technique, based on redundancy and reassignment that calibrates and corrects offsets and distortion in an 8-bit folding ADC. Unlike other folding ADC calibration techniques [1] this approach also compensates for unintended non-linearities and distortion in the folders. Much as the technique in [2] overcomes amplifier non-linearity in a pipeline ADC through digital processing, this approach overcomes analog inaccuracy and distortion with a simple digital calibration technique. Digital calibration decouples analog accuracy from overall ADC accuracy allowing minimum length, small devices to be used in the signal path. A 500MS/s 8-bit fully-integrated, self-calibrating, prototype, complete with digital calibration engine, is fabricated in digital 0.18µm CMOS.

II. DIGITAL CALIBRATION SCHEME

The new architecture works by generating redundant folding zero-crossings. A calibration engine controls a DAC that searches the set of available folder zero-crossings and selects and enables circuitry that generates the 2N-1 most appropriate crossings. A redundancy of 4 ensures a high yield even with low accuracy analog components, decoupling speed and accuracy [3]. Calibration information is stored in SRAM. During conversion the calibration engine and unselected redundant circuitry is powered down. A conventional N-bit folding ADC generates a folder zero-crossing for each of the 2N-1 codes. In this scheme, a calibration routine selects the 2N-1 most appropriate crossings from the set of available redundant crossings. Reassignment allows any zero-crossing to be assigned to any code [3].

To illustrate the technique, Fig. 1 shows a simple example of redundancy and reassignment in a 2-bit flash ADC. Three comparators are redundantly assigned to each code transition. Comparators, 1A, 1B and 1C, are nominally assigned to code transition 1 (Fig. 1(a)). Offsets in the comparators cause the trip-points of the comparators to deviate from the nominal values (Fig. 1(b)). In this example comparator 1A has a trip-point close to the ideal value and is assigned to code 1. Comparator 2B is selected for code 2. In an example of reassignment comparator 2A, nominally assigned to code 2, is selected to represent code 3.

Fig.1. (a) Nominal comparator trip-points with a redundancy of 3 comparators

for each code (b) Offsets move trip-points. Example of reassignment, 2A is assigned to code 3.

Fig. 2 describes how redundancy and reassignment are applied in a folding ADC. The figure shows two ideal folding waveforms A, B, as well as examples of low accuracy folding waveforms from redundant folder pairs (A1 and A2, B1 and B2). By digitally selecting the most appropriate individual zero-crossings, the correct folder characteristic is constructed. Similar to a conventional folding ADC, the calibrated ADC also incorporates a coarse ADC or cycle pointer, but in this case the coarse ADC functions in a somewhat different manner. In this example, the coarse ADC divides the ADC input range into four quadrants; labeled 0-3. If a zero-crossing is selected then a folder output is enabled for an entire quadrant. In an example of reassignment, a zero-crossing from B2 is selected for folding waveform A. Since no zero-crossings are selected from folder A2, it is powered down. The calibration ensures that a folder with two zero-crossovers in a quadrant is not selected, and also corrects crossover polarity. In quadrant 3, B1 has an ideal zero-crossing (X1) for A. However if the output of folder B1 is enabled in quadrant 3, two zero-crossings (X1 and X2) not one would be selected, therefore A1 is selected instead. The

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IEEE 2007 Custom Intergrated Circuits Conference (CICC)

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calibration also corrects zero-crossings close to an ideal voltage but with the wrong polarity - the zero-crossing of B1 in quadrant 2 is inverted by the calibration logic. Since offsets in the comparators can also lead to errors, comparator redundancy is also used in the digital calibration scheme.

Fig.2. Redundancy and reassignment of folder zero-crossings.

III. ARCHITECTURE

A conventional 8-bit folding ADC, with fold-by-4 folders, consists of 64 folders connected to 64 comparators. The prototype incorporates 128 folders, feeding 256 comparators, generating 1024 potential zero-crossings as shown in Fig. 3.

Fig. 3. Folding ADC block diagram.

On power-up, the ADC undergoes a calibration routine and the resistor ladder is configured as a 10-bit search DAC. The calibration engine controls the DAC to search the available 1024 zero-crossings for the best 255 zero-crossings. The zero-crossing selection and polarity correction information is stored in SRAM. The prototype uses a 3-bit coarse flash ADC to divide the ADC conversion range into ‘octants’. The use of a 3-bit rather

than 2-bit coarse ADC decreases the possibility of having more than one zero-crossing in a given octant. The coarse ADC itself is calibrated from a set of 21 available redundant comparators. The locations of the coarse ADC trip-points are also stored in SRAM. Synchronization between the coarse ADC and folders is achieved through overlap and digital correction. In conversion mode, the DAC and calibration engine are disabled. The Power Control block powers down unselected redundant circuitry. Comparator outputs are decoded on-chip using information from the coarse ADC and the information in the polarity and zero-crossing memories. An adder sums the decoded comparator outputs and combines this sum with the output of the coarse ADC trip-point register to give the 8-bit ADC output.

IV. CIRCUIT IMPLEMENTATION

A. Folders and Comparators This folding ADC contains 128 folders connected to 256

comparators. The extra folders are introduced by connecting 2 folders to each set of reference voltages and two comparators to each folder. Similarly the coarse ADC has 3 times as many comparators as are needed. Minimization of comparator size is possible since there is virtually no matching requirement. The reduction in the area of individual comparators and folders compensates for the increase in their number.

Each folder consists of four cross-coupled differential pairs and a single extra transistor that acts as a DC level shift so that the folder outputs cross (Fig. 4). The folder outputs are mirrored into two comparators. If a comparator is unselected then it is powered down. If both comparators are unselected the folder is also powered down. Clocks to the unselected comparators are also disabled to reduce switching noise and power consumption.

Fig. 4. Each folder is connected to two comparators. Unselected circuitry is powered down.

The two comparators connected to the folder outputs are connected with reverse polarity to protect against systematic offset. The comparators used are small, each one having a total area of only 300µm2. The low accuracy helps ensure that the comparators generate 8 distinct zero-crossings. Transistor sizes are shown in Fig. 4. For speed and energy efficiency, the differential pair transistors are minimum length and have a width of 2.5µm. This small size leads to very poor matching, the input referred standard deviation offset of the folders due to the differential pair mismatch alone is more

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than 3 LSB, but these offsets are overcome by the calibration routine. To reduce the capacitance at the tails of the folder differential pairs, the current source transistors are small with a width of 2µm and a length of 0.7µm. The low output resistance of the current sources causes significant distortion in the folder outputs. A conventional 8-bit folding ADC using 64 of these folders, simulated with Spectre and with no mismatch, is limited to a DNL of 3.8LSB, Fig. 5.

Fig. 5. Calibration corrects distortion in the folder crossovers – this distortion is shown in DNL plots derived from Spectre simulation of an 8-bit ADC using

these folders. The distorted output of a single folder as the input voltage is swept from low to high is shown in the inset.

B. Resistor ladder DAC A resistor string provides the ADC reference voltages (Fig. 6). Each folder requires four reference voltages equally spaced over the entire reference range. Bending the resistor ladder simplifies the connection of the reference taps to the folders but this adds extra parasitic resistance at the corners (Fig. 6(a)). These corner errors are eliminated by building a ladder comprised of ‘L’ shaped metal resistors so that the ladder can take almost any shape (Fig. 6(b)). Switches for the DAC and substrate connections fit into the ‘cavities’ of the resistor string (Fig. 6(c)). Fig. 6, (a) Resistor ladder suffers from parasitic corner resistance; (b) resistor

ladder with ‘L’ shaped resistors and (c) DAC switches and substrate connections are embedded in ladder cavities.

C. Sample and Hold A folding ADC, with an input frequency FIN and folding by 4, applies an input to the comparators at a frequency of approximately 4 times FIN. A 3.3V sample and hold is used at the input to the chip. Instead of using a dedicated hold

capacitor, CL consists of the input capacitance of folders and input wiring. Although the input capacitance of the folders varies non-linearly with applied voltage, thanks to the small folder devices the folding input capacitance is only 1.3pF of the total 2.1pF. M2 is a dummy transistor and cancels charge injection when M1 turns off.

Fig. 7. The parasitic load capacitance of the routing and folder inputs forms the sample-and-hold hold capacitance.

D. Coarse ADC calibration The coarse ADC is calibrated first. The comparators in the

coarse ADC are similar to those connected to the folders and because of the small transistor sizes these have large random offsets. From the available bank of 21 comparators, 7 are selected and enabled and the remainder are powered down. An example comparator search is shown in Fig. 8. Generating an input to the bank of redundant comparators with the DAC, the search range expands beyond the ideal value until a comparator is found. The location of the comparator trip-point is stored in the coarse ADC trip-point register.

Fig. 8. Coarse ADC comparator search. In this example, a comparator is

found on the 4th search.

E. Folding ADC Search The folding ADC calibration algorithm is similar to the

coarse ADC calibration. For each code, the search begins by looking for a folder zero-crossing between -1 DAC LSB and +1 DAC LSB of the ideal value. If no zero-crossing is found then the search is extended to -2 DAC LSB to +2 DAC LSB and so on. A boundary check ensures that enabling the selected comparator output for a given octant only enables a single zero-crossing. The boundary edges are defined by the coarse ADC transition points, stored in the trip-point register during the coarse ADC calibration. If the boundary test fails

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then the search range is extended. The overall ADC calibration process is summarized in Fig. 9.

Fig. 9. (a) Calibration of coarse ADC (b) Calibration of folders.

V. PROTOTYPE MEASUREMENTS

The prototype 8-bit ADC, fabricated in 0.18µm digital CMOS (Fig. 10), has an active area of 1.22mm2. The total analog active area (i.e. folders, comparators and sample-and-hold), is only 0.2mm2. The prototype is entirely self-contained, incorporating all calibration and decoding logic. All digital circuitry is synthesized from verilog, and automatically placed and routed.

Fig. 10. Folding ADC die micrograph.

The SFDR versus sampling rate (FS), measured with a 1MHz input (FIN), is show in Fig. 11. At FS=39MS/s, SFDR is 63dB and remains above 55dB up to FS=550MS/s. Thermal noise in the folders limits the SNDR to 44dB. Simulations show that thermal noise can be reduced significantly with a small increase in total analog power. The SFDR, measured at FS=500MS/s, is above 52dB for FIN up to 120MHz, Fig. 12. The DNL of the calibrated ADC, measured at FS=500MS/s, is

between -0.81 and 0.77LSB and the INL is between -0.57 and 0.73LSB. The measured DNL of the uncalibrated ADC is 6.7LSB. Using the method described in [4], no metastability error was detected in 1012 samples indicating a BER less than 10-12. At 500MS/s analog circuitry (clocking, S/H, folders, comparators) consumes 132mW while the digital backend consumes 216mW.

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ACKNOWLEDGMENTS

This work was supported by the WIMS-ERC, Engineering Research Centers program of the NSF under Award EEC-9986866 and by NSF Award CCF0346874. The authors acknowledge the assistance of Stacy Ho of Analog Devices.

REFERENCES

[1] R.C. Taft, C.A.. Menkus, M.R. Tursi, O. Hidri and V. Pons, “A 1.8-V 1.6-GSample/s 8-b self-calibrating folding ADC with 7.26 ENOB at Nyquist frequency”, IEEE J. Solid-State Circuits, Vol. 39, Issue 12, Dec. 2004 Page(s):2107 - 2115

[2] B. Murmann and B.E. Boser, “A 12-bit 75-MS/s pipelined ADC using open-loop residue

amplification”, IEEE J. Solid-State Circuits, Vol. 38, Issue 12, Dec 2003 Page(s):2040 - 2050

[3] C. Donovan and M.P. Flynn, “A ‘digital’ 6-bit ADC in 0.25µm CMOS”, IEEE J. Solid-State Circuits, Vol. 37, Issue 3, March 2002 Page(s): 432-437

[4] A.G.W. Venes and R.J. van-de-Plassche, “An 80-MHz, 80-mW, 8-b CMOS folding A/D converter with distributed track-and-hold preprocessing”, IEEE J. Solid-State Circuits, Vol. 31, Issue 12, Dec. 1996 Page(s):1846 - 1853

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