Reliability Evaluation and Comparison of Class-E and Class-A Power Amplifiers with 0.18 ,u m CMOS Technology

Wei-Cheng Lin, Long-Jei Du and Ya-Chin King

Microelectronics Laboratory, Semiconductor Technology Application Research (STAR) Group, Institote of Electronics Engineering, National Tsing-Hua University, Hsin-Chu 300, Taiwan

PhoneiFax: +886-3-5715 13 1-41 07/+886-3-5721804, E-mail: d895028@oz.nthu.edu.tw

1. Abstract Circuit Reliability of Class-E and Class-A power amplifiers

are investigated based on a degradation subcircuit model. In this study, we’ve found that Class-E amplifier degrades faster than Class-A amplifier, due to the relatively large switch stress voltage between gate to drain. The decrease of power added efficiency lead to the functional failure of a power amplifier. 2. Introduction

IC technology advancement in the past few years has allowed RF f r o n t a d CMOS IC becomes competitive [I]. Therefore, papers discussing RFlC reliability evaluation start to emerge recently [2.3.4].

While moving toward to monolithic CMOS transceivers, the integration of the power amplifier (PA) remains a difficult challenge reported. In order to achieve high efficiency at high power level, a Class-E amplifier employs a switch-mode operation, sweeping the drain peak voltage to 3.6Vr[5.6]. Its high voltage stress on the active device is always a reliability issue in the design of the Class-E amplifier. Class-A amplifier has a high linearity characteristic, but its efficiency less than 50%.

Using a degradation sub-circuit model, the reliability evaluations of Class-E and Class-A amplifiers have been investigated. By predicting device degradation behavior at its unique operation condition, the circuit-level depdat ion of the power amplifier can be analyzed.

3. Degradation Model Fig. 1 shows the degradation sub-circuit model proposed,

which describes device characteristics degradation after high-voltage stress [2].

Device characteristics is modeled by two Rss resistors and two Rco resistors, to represent degradation at “on state” and “off state”, respectively. Rss models the degradation of drain current due to mobility reduction afler stress, whereas Rco models the stress induced oxide leakage current between gate and drain. This model could predict device degradation as a fimction of stress voltage and stress time. The device models and circuit design are based on 0.18 m CMOS technology,

Fig. 2 compares the fresh and stressed measurement results with the simulated results from this degradation model. A fairly good agreement between the measured I-V curves and simulated values by the sub-circuit model is demonstrated.

4. Circuit Evaluations and Discussion Fig. 3(a) shows the configuration of Class-E amplifier. The

transistor functions as a switch, which is mmed on and off with 50% duty cycle at the frequency 2.4GHz. LI-CI is designed to resonate at 2.4GHz, the operating frequency for Bluetooth. The output matching network L2-0 transforms the 50ohm standard load to provide optimal efficiency.

Fig. 3(b) shows the circuit schematic of a Class-A amplifier. Mi is operated in the saturation region. The input signal given is a sine wave operated at 2.4GHz. CA-LI-C+ transformed the impedance to match the standard load of 5Oohm to provide optimal eficiency.

The simulated poww added efficiency of Class-E and Class-A amplifier at 2.4GHz against output power are shown in

Fig. 5. In a Class-E amplifier, the PAE increases with raising output power. Class-A amplifier designed has a maximum PAE of 46% with the output power of 24dbm. At output power of 22dbm. the two amplifiers’ PAE have the same power added efficiency 43%. The following reliability evaluations of the two power amplifier are based on the same PAE at 43% and output power of 22dhm.

Fig. 4(a) shows the simulated gate voltage and drain voltage waveforms of Class-E amplifier, respectively. The drain voltage at the drain of the class E amplifier is swept up to 6 volts, almost 3.3 times the supply voltage. Fig. 4(b) shows the gate voltage and drain voltage waveforms of Class-A amplifier during operation, respectively. From Fig. 4, it is obvious the transistor in a Class-E amplifier suffers much higher stress voltage than that in a Class-A amplifier operating at the same power level.

Fig. 6 shows the degradation of drain current of the two MOSFETs which are in a Class-E and a Class-A amplifier, respectively. The MOSFET in Class-A amplifier show little to no degradation at Vv =1.8V after IO8 seconds of operation. Whereas, the MOSFET in a Class-E amplifier degrades severely.

Fig. 7 (a)(h) show the degradation of power added efficiency and output power of the two amplifier with time. At the one year halts, the power added efficiency decrease from 43% to 37% and output power decrease from 155mW to 146mW for a Class-E amplifier. The decreased of PAE can cause function failure for the transceiver circuit. Notice that Class-A amplifier shows no degradation in its critical performance parameter even after ten years. Fig. 8(a)(b) show the change in PAE and output power of the two amplifiers, a s a results of decreasing drain current. A Class-E amplifier is more susceptible to active-device drain current degradation than a Class-A amplifier. The PAE of a Class-E amplifier with reduced l~ decreases severely, on the other hand, the PAE of a Class-A amplifier increases. The increase of PAE in Class-A amplifier is due to a faster decreasing power dissipation than the output power as I&, decrease.

5. Conclusion In this analysis, we found that not only does the Class-E

configuration puts the active device under a high voltage stress level, the performance of a Class-E amplifier can be critically degraded when device characteristics changes with operation time. Simulation results show that a switch-mode Class-E amplifier experiences severe degradation much more than a Class-A amplifier in PAE and output power.

Referenee [IICheon So0 Kim et el, IEEE M T M , pp.945-948,1997. [2]Wei-Cheng Lin et SI, accepted by IEEE WIC Symposium, 2003. [3]Qiang Li et al. IEEE RFlC Symposium. pp.399-402,2002, [41Qiang Li et al. IEEE M l T , vol. 49, N0.9, pp.1546-1551, September

[5]Paul R. Gray et al. IEEE I. Solid-State Circuit, ~01.34, N0.7,

[6]Koen L. R. Menens et al, EEE I. Solid-Stale Circuit, ~01.37, N0.2,

2001.

pp.962-970, July 1999.

pp.137-141,Feb. 2002.

IEEE 04CH37533 42d Annual International Reliability 0-7803-8315x104/$20.00 QW IEEE 415 Physics Symposium, Phoenix, 2004

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Fig. 1. The sub-circuit model with external resistances for degradation modeling 121.

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v s 4 a ; 1 u % ......................... :

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Fig. 3@) The schematic at Class-A amplifier.

m x m

Fig. 5. The simulated power added efficiency of Class-E and Class-A amplifier at 2.4GHz against output power.

D . . . . . . . . . . . .

Fig. 7@). The degradation of output ~ W R

with operating time.

T m f h R c r o n n d m W d .................... .............. ‘

........... ..: - - - - - - - -

Fig. 2. Comparison between measured I-V and simulated I-V at the stress condition of Vg=5.4V aller 45000sec.

Fig. 3(a) The schematic of Class-E amplifier.

Fig. 4. Waveforms of simulated (a) Class-E and @) Class-A amplifier,

8 W . . . . _1

Drain Voltage (V)

Fig. 6. The degradation of drain current of the two MOSFETs which operated in Class-E and Class-A amplifier respectively after 108 seconds.

Fig. S(9 The change of output power against the drain current degradation. With &e same c m n t degradation, Class-E amplifier degrades more than the Class-A amplifier.

Fig. 7(a). The degradation of power added efficiency with operating time.

Fig. 8(b). The change of PAE against the percentage of drain current degradation.

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