[IEEE 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers - San...
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• 2001 IEEE International Solid-State Circuits Conference 0-7803-6608-5 ©2001 IEEE ISSCC 2001 / SESSION 8 / NYQUIST ADCs / 8.1 8.1 A 6b 1.3GSample/s A/D Converter in 0.35μm CMOS Michael Choi, Asad A. Abidi Electrical Engineering Department, University of California, Los Angeles, CA Digital receivers for high bit-rate communications are spurring on the required conversion rate of A/D converters. State-of-the- art disk drive read channels and high-speed Ethernet signals use partial response signaling, requiring 6b resolution at conversion rates of 1GHz and beyond, and an effective resolution bandwidth of half the Nyquist frequency. Furthermore, continuous DVD playback and certain Ethernet uses permit no idle times when the linearity of the A/D converter may be self-calibrated by auto- zeroing. This work reports on a 6b ADC without autozero or self- calibration, which digitizes a 630MHz input with a linearity of 5.5 effective bits at 1GSample/s, and a 650MHz input with 5 effective bits at 1.3GSample/s. At conversion rates of 1GSample/s and beyond, the only practical architecture to date is the flash ADC. As MOSFETs in the pream- plifiers are sized up to lower random mismatch to resolve a typi- cal full-scale of 1.6V to 6b, the power consumption and input capacitance also grow to a point that the ADC may no longer be readily embedded in a receiver chip. This ADC uses resistor aver- aging in two places to filter out random mismatch between arrays of differential pairs, substantially improving the accuracy of small MOSFETs which bias at a small current and present low input capacitance. Previous work [1] presents a systematic method to design averaging networks based on spatial filtering. With the proper number of dummy preamplifiers at each end of the array, the optimum averaging network lowers INL by 3.3x. To obtain the same linearity without averaging, FET W/L, and therefore power dissipation, must be scaled by 10x. This flash ADC consists of an array of 63 differential preampli- fiers, with 9 dummy preamplifiers at each end of the array. Although averaging lowers the effect of FET mismatch in the preamplifiers, the low voltage gain of 3 in the single-stage pre- amplifier required for wideband operation is insufficient to sup- press random offsets due to the regenerative comparators. Therefore, the outputs of the sense amplifier array driving latch- es in the comparators are averaged as well (Figure 8.1.1). Monte Carlo transient simulations show that both stages of averaging lower input-referred RMS offset from 11mV to 3.7mV. The dif- ferential averaging network consists of diode-connected FET resistors connected across the differential output of each ampli- fier, and fixed polysilicon resistors connected between neighbors in an array. While the unclocked preamplifier tracks the input signal, a switch lowers the first comparator gain to less than one to erase memory of the previous decision, and to develop a voltage in response to the current input (Figure 8.1.2). Then, while the input sample is being held during clkbar high, the switch is released and the merged latch regenerates. The output of the first comparator drives a second comparator (Figure 8.1.3). As this second comparator samples the output of the first compara- tor, its output is reset through two parallel discharge paths for fast overdrive recovery. In the next half clock cycle, differential pair nMOSFETs comprising cross-coupled CMOS inverters rapidly steer the tail current from one side to the other, speeding up regeneration. This drives an SR latch. The cascaded regener- ation times of the two ranks of comparators and SR latch guar- antee a metastable error rate of less than 10 –10 at 1GSample/s. A high-speed encoder (Figure 8.1.4) converts thermometer code at the output of the latch array to quasi-Gray code, and then to binary code [2]. This arrangement requires only two-input NAND gates, but gives the same bubble-error suppression as conventional Gray encoding which needs slower three input NAND gates. To operate at 1GHz, the D-flip flops are true sin- gle-phase clocked (TSPC) circuits, and encoders are ROM-based. The encoded output is decimated-by-16 on-chip to enable easy acquisition by a logic analyzer. The output buffers are differen- tial circuits driving 100Ω loads. An on-chip track-and-hold (T/H) circuit precedes the flash quan- tizer. This track-mode bandwidth of this circuit must exceed 1GHz, and at half-Nyquist input frequency its dynamic distor- tion must be below –40dBc. A passive FET switch connected to a sampling capacitor through a dummy switch fulfills these requirements [3]. The main sources of distortion are signal- dependent charge injection on switch closure, nonlinearity of the input buffer, and dynamic current into the signal-dependent input capacitance of the comparator array. The differential input voltage is applied to the sampling switches of the T/H (Figure 8.1.5) at a low common-mode of 0.5V, which ensures that the nMOS switch maintains a large gate overdrive over the 1.6V dif- ferential full-scale and does not introduce significant distortion due to its nonlinear channel resistance. A pMOS source follower, with source tied to well to eliminate nonlinear body effect, buffers and level shifts the voltage sampled on the 1pF hold capacitor and drives the signal-dependent input capacitance of the quantizer array. Simulations show that when acquiring sam- ples of a 249MHz full-scale sinewave at 1GSample/s, the T/H introduces 3 rd -harmonic distortion of about –60dBc at the quan- tizer input. The ADC occupies 0.8mm 2 active area fabricated in a 0.35μm CMOS four-metal process (Figure 8.1.7). The entire chip is extracted and simulated using mixed-signal techniques. The reported performance is from first silicon. To measure dynamic performance accurately, the ADC is clocked with a low phase noise sinewave synthesizer. On-chip circuits generate and dis- tribute true and complement clocks. About 1.6nF of decoupling capacitance is placed on empty areas of the die. The ADC is mounted in a 64-pin TQFP for all tests. Excluding output buffers, it consumes about 500mW from 3.3V at 1 GHz conver- sion rate, and 545mW at 1.3GHz. The logic circuits and clock buffers consume half the power, and this portion of the total power will scale down with technology. At 1GSample/s, INL and DNL are below ±0.3 LSB. The ADC dynamic performance (Figure 8.1.6) shows an effective resolution bandwidth exceeding Nyquist input frequency, and flat reconstructed SNDR and SFDR up to 1.3GHz conversion rate. References: [1] H. Pan, et al., “A 12b 65MSample/s CMOS ADC with 82dB SFDR at 120MHz,” ISSCC Digest of Technical Papers, pp. 38-39, Feb 2000. [2] T. Wakimoto, et al., “Si Bipolar 2GSample/s 6b Flash A/D Conversion LSI,” ISSCC Digest of Technical Papers, pp. 232-233, Feb 1988. [3] P. Pai, A. Brewster, A. Abidi, “A 160-MHz analog front-end IC for EPR- IV PRML magnetic storage read channels,” IEEE J. of Solid-State Circuits, vol.31, no.11, p.1803-16, Nov. 1996.
Transcript of [IEEE 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers - San...
![Page 1: [IEEE 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers - San Francisco, CA, USA (5-7 Feb. 2001)] 2001 IEEE International Solid-State Circuits Conference.](https://reader035.fdocument.org/reader035/viewer/2022080506/5750ac421a28abcf0ce5a576/html5/thumbnails/1.jpg)
• 2001 IEEE International Solid-State Circuits Conference 0-7803-6608-5 ©2001 IEEE
ISSCC 2001 / SESSION 8 / NYQUIST ADCs / 8.1
8.1 A 6b 1.3GSample/s A/D Converter in 0.35µm CMOS
Michael Choi, Asad A. Abidi
Electrical Engineering Department, University of California, Los Angeles, CA
Digital receivers for high bit-rate communications are spurringon the required conversion rate of A/D converters. State-of-the-art disk drive read channels and high-speed Ethernet signals usepartial response signaling, requiring 6b resolution at conversionrates of 1GHz and beyond, and an effective resolution bandwidthof half the Nyquist frequency. Furthermore, continuous DVDplayback and certain Ethernet uses permit no idle times whenthe linearity of the A/D converter may be self-calibrated by auto-zeroing. This work reports on a 6b ADC without autozero or self-calibration, which digitizes a 630MHz input with a linearity of5.5 effective bits at 1GSample/s, and a 650MHz input with 5effective bits at 1.3GSample/s.
At conversion rates of 1GSample/s and beyond, the only practicalarchitecture to date is the flash ADC. As MOSFETs in the pream-plifiers are sized up to lower random mismatch to resolve a typi-cal full-scale of 1.6V to 6b, the power consumption and inputcapacitance also grow to a point that the ADC may no longer bereadily embedded in a receiver chip. This ADC uses resistor aver-aging in two places to filter out random mismatch between arraysof differential pairs, substantially improving the accuracy of smallMOSFETs which bias at a small current and present low inputcapacitance. Previous work [1] presents a systematic method todesign averaging networks based on spatial filtering. With theproper number of dummy preamplifiers at each end of the array,the optimum averaging network lowers INL by 3.3x. To obtain thesame linearity without averaging, FET W/L, and therefore powerdissipation, must be scaled by 10x.
This flash ADC consists of an array of 63 differential preampli-fiers, with 9 dummy preamplifiers at each end of the array.Although averaging lowers the effect of FET mismatch in thepreamplifiers, the low voltage gain of 3 in the single-stage pre-amplifier required for wideband operation is insufficient to sup-press random offsets due to the regenerative comparators.Therefore, the outputs of the sense amplifier array driving latch-es in the comparators are averaged as well (Figure 8.1.1). MonteCarlo transient simulations show that both stages of averaginglower input-referred RMS offset from 11mV to 3.7mV. The dif-ferential averaging network consists of diode-connected FETresistors connected across the differential output of each ampli-fier, and fixed polysilicon resistors connected between neighborsin an array.
While the unclocked preamplifier tracks the input signal, aswitch lowers the first comparator gain to less than one to erasememory of the previous decision, and to develop a voltage inresponse to the current input (Figure 8.1.2). Then, while theinput sample is being held during clkbar high, the switch isreleased and the merged latch regenerates. The output of thefirst comparator drives a second comparator (Figure 8.1.3). Asthis second comparator samples the output of the first compara-tor, its output is reset through two parallel discharge paths forfast overdrive recovery. In the next half clock cycle, differentialpair nMOSFETs comprising cross-coupled CMOS invertersrapidly steer the tail current from one side to the other, speedingup regeneration. This drives an SR latch. The cascaded regener-ation times of the two ranks of comparators and SR latch guar-antee a metastable error rate of less than 10–10 at 1GSample/s.
A high-speed encoder (Figure 8.1.4) converts thermometer codeat the output of the latch array to quasi-Gray code, and then to
binary code [2]. This arrangement requires only two-inputNAND gates, but gives the same bubble-error suppression asconventional Gray encoding which needs slower three inputNAND gates. To operate at 1GHz, the D-flip flops are true sin-gle-phase clocked (TSPC) circuits, and encoders are ROM-based.The encoded output is decimated-by-16 on-chip to enable easyacquisition by a logic analyzer. The output buffers are differen-tial circuits driving 100Ω loads.
An on-chip track-and-hold (T/H) circuit precedes the flash quan-tizer. This track-mode bandwidth of this circuit must exceed1GHz, and at half-Nyquist input frequency its dynamic distor-tion must be below –40dBc. A passive FET switch connected to asampling capacitor through a dummy switch fulfills theserequirements [3]. The main sources of distortion are signal-dependent charge injection on switch closure, nonlinearity of theinput buffer, and dynamic current into the signal-dependentinput capacitance of the comparator array. The differential inputvoltage is applied to the sampling switches of the T/H (Figure8.1.5) at a low common-mode of 0.5V, which ensures that thenMOS switch maintains a large gate overdrive over the 1.6V dif-ferential full-scale and does not introduce significant distortiondue to its nonlinear channel resistance. A pMOS source follower,with source tied to well to eliminate nonlinear body effect,buffers and level shifts the voltage sampled on the 1pF holdcapacitor and drives the signal-dependent input capacitance ofthe quantizer array. Simulations show that when acquiring sam-ples of a 249MHz full-scale sinewave at 1GSample/s, the T/Hintroduces 3rd-harmonic distortion of about –60dBc at the quan-tizer input.
The ADC occupies 0.8mm2 active area fabricated in a 0.35µmCMOS four-metal process (Figure 8.1.7). The entire chip isextracted and simulated using mixed-signal techniques. Thereported performance is from first silicon. To measure dynamicperformance accurately, the ADC is clocked with a low phasenoise sinewave synthesizer. On-chip circuits generate and dis-tribute true and complement clocks. About 1.6nF of decouplingcapacitance is placed on empty areas of the die. The ADC ismounted in a 64-pin TQFP for all tests. Excluding outputbuffers, it consumes about 500mW from 3.3V at 1 GHz conver-sion rate, and 545mW at 1.3GHz. The logic circuits and clockbuffers consume half the power, and this portion of the totalpower will scale down with technology. At 1GSample/s, INL andDNL are below ±0.3 LSB. The ADC dynamic performance(Figure 8.1.6) shows an effective resolution bandwidth exceedingNyquist input frequency, and flat reconstructed SNDR andSFDR up to 1.3GHz conversion rate.
References:[1] H. Pan, et al., “A 12b 65MSample/s CMOS ADC with 82dB SFDR at120MHz,” ISSCC Digest of Technical Papers, pp. 38-39, Feb 2000.[2] T. Wakimoto, et al., “Si Bipolar 2GSample/s 6b Flash A/D ConversionLSI,” ISSCC Digest of Technical Papers, pp. 232-233, Feb 1988.[3] P. Pai, A. Brewster, A. Abidi, “A 160-MHz analog front-end IC for EPR-IV PRML magnetic storage read channels,” IEEE J. of Solid-State Circuits,vol.31, no.11, p.1803-16, Nov. 1996.
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• 2001 IEEE International Solid-State Circuits Conference 0-7803-6608-5 ©2001 IEEE
ISSCC 2001 / February 6, 2001 / Salon 7 / 8:30 AM
Figure 8.1.1: Flash ADC architecture with two stages of averaging resistor networks, 9dummy channels on each side of main array suppress systematic INL at boundaries. Figure 8.1.2: First stage comparator.
Figure 8.1.3: Second stage comparator designed for fast overdrive recoveryand fast regeneration.
Figure 8.1.4: Encoder block diagram. Individual circuit blocks are chosen to clock at1.3GHz.
Figure 8.1.5: One half of quasi-differential T/H circuit at ADC input.
Figure 8.1.6: (a) Measured SNDR vs. analog input frequency, at conversion rate of1GHz and 1.3GHz. (b) Measured SNDR and SFDR vs. conversion rate for input fre-quency of 100MHz.
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Figure 8.1.7: Chip micrograph.
• 2001 IEEE International Solid-State Circuits Conference 0-7803-6608-5 ©2001 IEEE
