[IEEE 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers - San...
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. - - ISSCC97I SESSION 6 / LOW-POWER AND MIXED-SIGNAL PROCESSING / PAPER TP 6.3 TP 6.3: A 16b 100kSampleIs 2.7V 25mW ADCIDSPIDAC- Based Analog Signal Processor in 0.8vm CMOS Ian J. Dedic, Neil C. Amos, Malcolm J. King, William G. Schofield, Andrew K. Kemp Fujitsu Microelectronics Ltd., European Mixed-Signal ASIC Design Centre, Berkshire, United Kingdom As supply voltage and process geometry decrease, digital signal processinguses less power and area than does analog, with analog currents rising quadratically to maintain SNR [11. For DSP-based signal processing in high-speed, high-resolution, low-power ap- plications, critical factors compared to a purely analog solution are ADC power consumption, and ADCIDSP cost. The 0.8pm CMOS signal processor shown in Figure 1 combines a low-noise analogfront-end and reference, 16bADC/DAC, and 16b DSP optimized for filter applications. With 25mW typical power consumption at 100kSample/s (3mW for ADCIDAC) it can be programmed for high-order analog filtering and other signal processing functions with 80dB typical SNR. The ADC/DAC that makes this feasible uses a differential 16b charge-balancing DAC and a single high-speed low-power com- parator, shown in Figure 2. Error-correcting successive approxi- mation (ECSA) uses two comparisons per bit to remove the need for accurate settling and comparison each clock cycle, requiring twice as many cycles but decreasing overall conversion time and latency by more than 4x. A conventional SA-ADC compares the input to the DAC output, and increments or decrements the DAC code by a bit weight that halves each cycle: Vin > DAC , DAC = DAC +weight : Vin < DAC , DAC = DAC - weight The ECSA-ADCchanges the DAC code only if the result is larger than half the weight. Two clock cycles are needed to make comparisons with upper and lower thresholds: Vin>DAC+weighti2,DAC=DAC+weight:Vin<~AC-~eighffZ,DAC=DAC-~eight The no-change state means that comparison errors, unless large, are corrected later in the conversion. A segmented 64-unit capaci- tor DAC is used for the GMSBs, and a modified R-2R DAC with 3 segmented MSBs for the 10LSBs. By duplicating the capacitors, DAC conversions can be performed simultaneously with one circuit using the decode and switch logic while the other one samples. With Ips sampling and 2ps conversion (32 cycles at 16MHz)itperforms simultaneousADandDIAconversions in 3ps using only 3mW at 100kSample/s, with 92dB measured SNR. Typical small-signal resolution at 500kSample/s is shown in Figure 3. The 16b fixed-point DSP core, Figure 4, and instruction set are optimized for cascaded biquad IIR filters, needing half as many clock cycles per biquad as a general-purpose DSP [a]. A multiple- bus triple-RAM architecture executes single-cycle compound in- structions, including I/O, multiply/accumulate, roundinghatura- tiodabsolute value, memory R/W, auto address control, iterative callfreturn, and fast sleep/wake up. The RAMS have dynamically- enabled read and write circuits for zero static power and mini- mum dynamic power. The DSP uses conditional clocking with reduced gate sizes and small fan-out to reduce power consump- tion and digital noise coupling. Asleep operation allows the clocks to be stopped during critical sample and convert operations. A dual-mode 4-wire serial interface loads the program and coef- ficient RAMS and control registers. Master mode allows stand- alone operation with an external EEPROM. Slave mode is used for development or when the system uses a controller. The interface also provides ADCIDAC data access for U0 to an external processor. All analog signal paths are differential to maximize noise rejec- tion. The error input has a fully-differential variable gain current- mode feedback amplifier with 1pV noise. Large (high Gm) sub- threshold input transistors with source feedback minimize the number of active devices that contribute significant noise. This is followed by a single-amplifier second-order switched-capacitor anti-aliasing filter (SC AAF). The signal input uses a single differential amplifier for second-order RC filtering (switched capacitors coarse chargedfrom low impedance first-order output, fine charged from higher impedance second-order output), second order SC filtering (half of biquad on each clock phase) with programmable gain. Each channel has 3dB gain steps from -12dB to +6dB. The S/H drives a push-pull 300Q driver. An untrimmed bandgap reference uses lateral bipolar npn transistors to give 8pV noise with a l/f noise corner of 100Hz. The 0.8pm p-well CMOS process has implanted resistors and poly-poly capacitors. A TSOP24 package with 20-pin lead frame minimizes size and thickness, and together with analog/digital pin spacing, die shape and layout reduces noise coupling. The chip is 5.9 x 3.5mm2,the analog is about 4mm2 (ADCDAC 1.5mm2). The analog power and area is minimized using MATLAB and HSPICE to analyze SNR trade-offs between and inside each circuit block. With 90dB typical SNR for each circuit block, 80dB total SNR is achieved using 4.5mA for the analog (1.1mA ADC/ DAC). Adding 4.5mA for the DSP (2mW/MHz, lOMHz, 60% activity) total power is typically 25mW at 2.7V for 100kSamplel s operation. Measured SINAD vs. input level for the entire device is shown in Figure 5. With the DSP running continuously at 16MHz, the ADC samples each input every 6ps with a DAC output every 3ps. This gives a 333kSample/s ADCIDAC and 16MIPS DSP with 50mW power consumption; SNR is degraded by less than 0.3dB compared to 1OOkSampleis operation with sleep instructions during conversions. 16 register-controlled analog test modes give access to all parts of the signal path. Digital test uses a partial-scan approach with signature analysis. Due to the low 110 count, analog pins are reconfigured as digital pins for these tests. SaberNerilog mixed- signal simulations of the entire device verify all modes and programmable options. In a handset noise-cancellation application, latency of the proces- sor must be small to keep the loop stable. Oversampled converters are unsuitable for this application as their digital filters introduce too much delay. The wanted signal (voice)and the signal from an additional microphone at the entrance to the ear (noise) are filtered separately, with the summed and filtered result driving the earpiece. The filter responses (a maximum of 23 state- variable biquads can be realized) depend on the acoustics of the transducers and handset but are fixed for a particular applica- tion. The result is an acoustic“virtua1 ground” for noise at the ear, reducing perceived ambient noise by 15-20dB. References: [ll Vittoz, E. “Low-Power Design:Ways to Approach the Limits,” ISSCC Digest of Technical Papers, pp.14-18, Feb.,1994. 121 Fujitsu MB871204 Generic Control Processor (GCP)data sheet. 96 1997 IEEE InternationalSolid-state Circuits Conference 0-7803-3721-2 I97 l$5.00 IO IEEE
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ISSCC97I SESSION 6 / LOW-POWER AND MIXED-SIGNAL PROCESSING / PAPER TP 6.3
TP 6.3: A 16b 100kSampleIs 2.7V 25mW ADCIDSPIDAC- Based Analog Signal Processor in 0.8vm CMOS
Ian J. Dedic, Neil C. Amos, Malcolm J. King, William G. Schofield, Andrew K. Kemp
Fujitsu Microelectronics Ltd., European Mixed-Signal ASIC Design Centre, Berkshire, United Kingdom
As supply voltage and process geometry decrease, digital signal processinguses less power and area than does analog, with analog currents rising quadratically to maintain SNR [11. For DSP-based signal processing in high-speed, high-resolution, low-power ap- plications, critical factors compared to a purely analog solution are ADC power consumption, and ADCIDSP cost.
The 0.8pm CMOS signal processor shown in Figure 1 combines a low-noise analogfront-end and reference, 16bADC/DAC, and 16b DSP optimized for filter applications. With 25mW typical power consumption a t 100kSample/s (3mW for ADCIDAC) it can be programmed for high-order analog filtering and other signal processing functions with 80dB typical SNR.
The ADC/DAC that makes this feasible uses a differential 16b charge-balancing DAC and a single high-speed low-power com- parator, shown in Figure 2. Error-correcting successive approxi- mation (ECSA) uses two comparisons per bit to remove the need for accurate settling and comparison each clock cycle, requiring twice as many cycles but decreasing overall conversion time and latency by more than 4x. A conventional SA-ADC compares the input to the DAC output, and increments or decrements the DAC code by a bit weight that halves each cycle:
Vin > DAC , DAC = DAC +weight : Vin < DAC , DAC = DAC - weight
The ECSA-ADC changes the DAC code only if the result is larger than half the weight. Two clock cycles are needed to make comparisons with upper and lower thresholds:
Vin>DAC+weighti2,DAC=DAC+weight:Vin<~AC-~eighffZ,DAC=DAC-~eight
The no-change state means that comparison errors, unless large, are corrected later in the conversion. A segmented 64-unit capaci- tor DAC is used for the GMSBs, and a modified R-2R DAC with 3 segmented MSBs for the 10LSBs. By duplicating the capacitors, DAC conversions can be performed simultaneously with one circuit using the decode and switch logic while the other one samples. With Ips sampling and 2ps conversion (32 cycles a t 16MHz)it performs simultaneous ADandDIAconversions in 3ps using only 3mW a t 100kSample/s, with 92dB measured SNR. Typical small-signal resolution at 500kSample/s is shown in Figure 3.
The 16b fixed-point DSP core, Figure 4, and instruction set are optimized for cascaded biquad IIR filters, needing half as many clock cycles per biquad as a general-purpose DSP [a]. A multiple- bus triple-RAM architecture executes single-cycle compound in- structions, including I/O, multiply/accumulate, roundinghatura- tiodabsolute value, memory R/W, auto address control, iterative callfreturn, and fast sleep/wake up. The RAMS have dynamically- enabled read and write circuits for zero static power and mini- mum dynamic power. The DSP uses conditional clocking with reduced gate sizes and small fan-out to reduce power consump- tion and digital noise coupling. Asleep operation allows the clocks to be stopped during critical sample and convert operations.
A dual-mode 4-wire serial interface loads the program and coef-
ficient RAMS and control registers. Master mode allows stand- alone operation with an external EEPROM. Slave mode is used for development or when the system uses a controller. The interface also provides ADCIDAC data access for U 0 to an external processor.
All analog signal paths are differential to maximize noise rejec- tion. The error input has a fully-differential variable gain current- mode feedback amplifier with 1pV noise. Large (high Gm) sub- threshold input transistors with source feedback minimize the number of active devices that contribute significant noise. This is followed by a single-amplifier second-order switched-capacitor anti-aliasing filter (SC AAF). The signal input uses a single differential amplifier for second-order RC filtering (switched capacitors coarse chargedfrom low impedance first-order output, fine charged from higher impedance second-order output), second order SC filtering (half of biquad on each clock phase) with programmable gain. Each channel has 3dB gain steps from -12dB to +6dB. The S/H drives a push-pull 300Q driver. An untrimmed bandgap reference uses lateral bipolar npn transistors to give 8pV noise with a l/f noise corner of 100Hz.
The 0.8pm p-well CMOS process has implanted resistors and poly-poly capacitors. A TSOP24 package with 20-pin lead frame minimizes size and thickness, and together with analog/digital pin spacing, die shape and layout reduces noise coupling. The chip is 5.9 x 3.5mm2, the analog is about 4mm2 (ADCDAC 1.5mm2).
The analog power and area is minimized using MATLAB and HSPICE to analyze SNR trade-offs between and inside each circuit block. With 90dB typical SNR for each circuit block, 80dB total SNR is achieved using 4.5mA for the analog (1.1mA ADC/ DAC). Adding 4.5mA for the DSP (2mW/MHz, lOMHz, 60% activity) total power is typically 25mW at 2.7V for 100kSamplel s operation. Measured SINAD vs. input level for the entire device is shown in Figure 5. With the DSP running continuously at 16MHz, the ADC samples each input every 6ps with a DAC output every 3ps. This gives a 333kSample/s ADCIDAC and 16MIPS DSP with 50mW power consumption; SNR is degraded by less than 0.3dB compared to 1OOkSampleis operation with sleep instructions during conversions.
16 register-controlled analog test modes give access to all parts of the signal path. Digital test uses a partial-scan approach with signature analysis. Due to the low 110 count, analog pins are reconfigured as digital pins for these tests. SaberNerilog mixed- signal simulations of the entire device verify all modes and programmable options.
In a handset noise-cancellation application, latency of the proces- sor must be small to keep the loop stable. Oversampled converters are unsuitable for this application as their digital filters introduce too much delay. The wanted signal (voice) and the signal from an additional microphone at the entrance to the ear (noise) are filtered separately, with the summed and filtered result driving the earpiece. The filter responses (a maximum of 23 state- variable biquads can be realized) depend on the acoustics of the transducers and handset but are fixed for a particular applica- tion. The result is an acoustic“virtua1 ground” for noise a t the ear, reducing perceived ambient noise by 15-20dB.
References:
[ l l Vittoz, E. “Low-Power Design:Ways to Approach the Limits,” ISSCC Digest of Technical Papers, pp.14-18, Feb.,1994.
121 Fujitsu MB871204 Generic Control Processor (GCP) data sheet.
96 1997 IEEE International Solid-state Circuits Conference 0-7803-3721-2 I 9 7 l$5.00 IO IEEE
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ISSCC97 I February 6,1997 I Salon 10-15 I2:30 PM
Filter Optimiscd Instruction Set Single Amplilier Filter
300 ohm drive
Figure 1: Signal processor block diagram.
2 2 \ ; + 5 %
(6 MSB) Vrdac (10 LSB) 64 Uurs x2 3MSB Seg id" 7 LSB R-2R DAC Out F;:p$ (ADCiDAC)
ADC In
Comparator
&-Q7 Conversion Complete
ADC Our DAC In Data Ready
Figure 2: 16b ADC/DAC block diagram.
* ( A ) * (X) * ( B ) 82.00 LSBs 0.0025 s
LSBSWAVEFORM CH1, vs TIME / s
0 :Om 20m 5 Om 7 Om 0.:
Figure 3: 500kSample/s small-signal ADC performance.
Coeff Ram Data Ram
b PCU
ADC
SDI
Figure 4: 16b DSP block diagram.
0 (X) 0 ( B ) 0 ( A )
- 79.19 d B r - 62.00 d B r - 77.68 dBr F I L E VS GEN VOLT d B r d B r FILE
- 4 0 -40 noise vs. voice LF i n p u t
- 5 0 -50 / I
- 55
- 60
- 65
-70
-75
- 80 50 - 3 0 -10 0 -100 -80
Figure 5: Measured SINAD performance. Figure 6 See page 438.
DSP 16b f=ed-point, 2mWMHz at 2.7V, 16MHz max. ADC/DAC 16b ECSA with S/H, 5mW
Noise Microphone amp lpV, overall device 80dB SNR Power 25mW at 2.7V, 100ks/s ADC/DAC + 6MIPS DSP
50mW at 2.7V, 333ks/s ADC/DAC + 16MIPS DSP Chip 5.9 x 3.5mm2 in 0 . 8 ~ CMOS, 20 pin TSOP
Table 1: Performance summary.
at 333kSample/s, 92dB SNR
-55
-60
'-65
-70
-75
-80 dB r
97 DIGEST OF TECHNICAL PAPERS
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TP 6.3: A 16b 100kSampleIs 2.7V 25mW ADCIDSPIDAC-Based Analog Signal Processor in 0.8pm CMOS (Continued from page 97)
Figure 6: Chip micrograph.
TP 6.4: A Single Battery, O.9V-Operated Digital Sound Processing IC Including ADIDA and IR Receiver with 2mW Power Consumption
Continued from Daae 991
Figure 7: Micrograph of the hearing aid IC.
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438 1997 IEEE International Solid-state Circuits Conference
