EE457L, Prof. Parker Spring 2007

HW6 Solution

Solutions to problems 1, 2, 6-9 by Roger Su 3-5 by Doochul Shin

10-13 by Ko-Chung Tseng 14-18 by Kun Young

3. L = 2λ (both PMOS and NMOS) W = 6λ (for NMOS)

2/)/(*4.219 VALWn

µ! = 2/)/(*51 VALWp µ! =

Since we make W of PMOS such that

p! =

n!

W (for PMOS) = 26 λ !

p! = 663 2

/VAµ

n

! = 658.2 2/VAµ

4. /)/(*int != WLRR

S

)5.0/200(*40 µµ=diffR = 16000 Ω

)75.0/4755(*1.0 µµ=

metalR = 634 Ω 3 * contact resistance = 30 Ω Note that 3 contacts/vias is the worst case path. On the NMOS side, there is only one contact. Last year’s solution averaged the two cases to come up with 2 contacts in the path. I prefer the worst case solution, so we used 3 contacts this year. !

totR = 16000 + 634 +30 = 16664 Ω

5. |)||(|

1

thpgsP

effVV

R!

="

Let thpV = - 0.7 V

!="

= 94.837)7.05.2(*/663

12VA

Reffµ

connectR is about 20 times larger than effR

1.0)100/100(*1.0 == !!padR ! So we can neglect pad resistance.

10. The high noise margin = 2.1-1.9=0.2(Volt) < 0.4(Volt) The low noise margin = 0.9-0.6=0.3(Volt) < 0.4(Volt) Therefore, the output might generate a wrong result due to noise. 11. a) A 5-input NAND gate has 5 pmos transistors in parallel. To solve βpeff (beta), we consider the case in which only one of them is on.

102)2

4(51)( =!=!=

L

WPpeff "" (µ A/V2)

b) RC model Assume NO diffusion sharing is being used.

(Falling RC model) (Rising RC model)

Delay(falling) )26(52423222 gdchndchndchndchndchn CCRCRCRCRCR +!+!!+!!+!!+!=

gchndchn CRCR !!+!!= 1050 ff) 100(ohms) 500(10 ff) 40(ohms) 500(50 !!+!!= 5.1= (ns)

Delay(rising)= 44.0)100240(6ohms)1000()26( =!+!!=!+!! gdchp CCR (ns) 12. 3200ff 502

6=!=

LC (ff)

13.

1) Ernie’s design

The lumped RC time constants of the above model =

)25.02()5.0()25.02()5.0( intintintint gdchngdchp CCCRRCCCRR !++!!++!++!!+

)100260402)](125.03

5(2.0500[

)100260402)](125.03

5(2.01000[

!++!!

+

+!++!!

+=

micron

mm

micron

mm

32.234031673403667 =!+!= (ns) 2) His boss’ design i) First rise, second fall

The lumped RC time constants of the above model =

)25.06()5.03

()65.02()5.0( intintintint gdchn

gdchp CCCRR

CCCRR !++!!++!++!!+

)100260406)](125.03

5(2.0

3

500[

)100660402)](125.03

5(2.01000[

!++!!

+

+!++!!

+=

micron

mm

micron

mm

130.450028337403667 =!+!= (ns) ii) First fall, second rise

The lumped RC time constants of the above model =

)25.06()5.03

()65.02()5.0( intintintint gd

chp

gdchn CCCRR

CCCRR !++!!++!++!!+

)100260406)](125.03

5(2.0

3

1000[

)100660402)](125.03

5(2.0500[

!++!!

+

+!++!!

+=

micron

mm

micron

mm

843.350030007403167 =!+!= (ns) From (i) and (ii), the average delay = 3.98 (ns) We conclude that Ernie’s boss’ design is worse than Ernie’s design. 14. Since six NMOS transistors are connected in series in pull-down, βneff

= βneff /6 where Wn = 4λ (unit size). From βpeff = βneff, 51(Wp/L) = 219.4(Wn/L)/6 Hence, Wp = 2.87 λ ≈3 λ

15. Suppose the inverter is driving load CL. We assume that the Vin changes from 0 to VDD instantaneously

at t = 0+. Since PMOS is off and NMOS is on at t = 0+, IDSn = – IC, where NMOS is operating in saturation (Vin = VDD, Vout = VDD Hence, VDSn = VGSn = VDD).

As Vout decreases, NMOS enters linear region when Vout = VDSn = VGSn – Vtn = 2.5V – 0.7V = 1.8V.

Hence, 2)(2

tnGSn

nout

LCVV

dt

dVCI !!==

" when 1.8 <Vout < 2.5, and

[ ]2)2(2

DSnDSntnGSn

nout

LVVVV

dt

dVC !!!=

" when Vout < 1.8V.

Fall time is computed when 0.125V <Vout < 2.375V.

Fall time = ( ) out

DSnDSntnGSnn

L

out

tnGSnn

LdV

VVVV

CdV

VV

C!!

""+

"

8.1

125.0 2

375.2

8.1 2 )2(

2

)(

2

##,

Where VGSn = 2.5V, Vtn = 0.7V, and VDSn = Vout. PMOS continues to operate in cutoff region after t = 0+ because VGS = Vin – VDD = 0 > Vtp.

a b c d e f

a

b

c

d

e

f

Without the assumption of instantaneous input change, the analysis becomes more complicated by considering the current flowing via PMOS as well as NMOS.

16. Unit length is 10microns. So, the distributed model consists of 10 resistors and 10 capacitors. 2(ohm)

3fF

2(ohm)

3fF

2(ohm)

3fF

2(ohm)

3fF

2(ohm)

3fF

2(ohm)

3fF

2(ohm)

3fF

2(ohm)

3fF

2(ohm)

3fF

2(ohm)

3fF

17. Answer: R1C1 + (R1+R2)C2 + (R1+R2)C3 + (R1+R2+R4)C4 + (R1+R2+R4)C5 + R1C6 + R1C7 + R1C8 18. clkoutloadoutclkloadDout !+!+!!=

GA

GB

Dload

out

load

out

clk

GC

out

clk

clk

load

D

out (1st latch)

5 15 25 27

Erroneous value D=0 is

propagated to out

(Intended to keep D=1)

2nd latch captures D=1

GA is on G

C is onG

C is on G

B is on

GA is on

Time problem: Although Ernie wants to keep the value of out (1st latch’s output) instead of capturing D by

lowering load, the first latch will capture an erroneous value of D because load is still active even AFTER clock becomes transparent for the first latch of Flip-Flop.

As illustrated in the figure above, load is still active (high) between time 25 to 27 when clk is high, which activates GA instead of GB for 2 units of time. This prevents the 1st latch from keeping the previous out value of logic-1, and instead an erroneous value D=0 propagates to the 2nd latch.