High Performance Digital Controller for High-Frequency Low...

Année 2009

THÈSE

Présentée

devant L’INSTITUT NATIONAL DES SCIENCES ALLPLIQUÉES DE LYON

Pour obtenir

LE GRADE DE DOCTEUR

École Doctorale: ELECTRONIQUE, ELECTROTECHNIQUE, AUTOMATIQUE

(E.E.A.)

Spécialité: GÉNIE ELECTRIQUE

par

Shuibao GUO

————————————————————————————————————— High Performance Digital Controller for High-Frequency Low-Power

Integrated DC/DC SMPS

高频低功率集成 DC / DC 开关电源中的高性能数字控制器的设计 —————————————————————————————————————

Soutenue: 27 Avril 2009 devant la Commission d’examen Jury: M. Marcian Cirstea Professeur - Anglia Ruskin University Rapporteur M. Eric Monmasson Professeur - Université de Cergy-Pontoise Rapporteur M. Emmanuel Godoy Professeur - SUPÉLEC Examinateur M. Bruno Allard Professeur - INSA Lyon Directeur de thèse Mme. Xuefang Lin-Shi MCF HDR- INSA Lyon Co-Directeur de thèse M. Séverin Trochut Ingénieur - ST-Ericsson Examinateur

LABORATOIRE AMPERE

To my parents,

and

To my wife

v

Acknowledgement

First and foremost, I would like to thank my advisor, Prof. Bruno Allard, for his guidance,

support and encouragement during my research. His extensive academic knowledge, advice,

creative thinking and broad practical experience in the power electronics field have been an

invaluable aid in focusing my study. Besides, his amicable disposition and accessibility have

provided for a constructive, stress-free collaboration. Working with Prof. Bruno Allard has

been one of the most memorable experiences and the best fortunes in my life.

Along with Prof. Bruno Allard, I would like to thank Dr. Xuefang Lin-Shi, for her patience,

discussions, suggestion and invaluable help. It has been a great pleasure to work with Dr.

Xuefang Lin-Shi at Lab AMPERE. The most precious thing I learned from her is the attitude

toward research, which can be applied to every aspects of life too. I have been benefited not

only from her wisdom and knowledge, but also her unique way of handling things and

structuring ideas, which will become invaluable treasures for me.

I am particularly grateful to my co-advisor from department IECE at Shanghai University,

Prof. Yi Ruan, for his particular support, profitable suggestion and excellent advice. Under his

direction, I have been given the opportunity to pursue my own scientific interests while

learning to explore complexity in power electronics.

Associate Prof. Yanxia Gao, I express my sincere regards for you recognizing my potential

and encouraging me to pursue the PhD degree under the cooperation between IECE and

AMPERE. Thank you for believing in me and giving me chance to attend graduate school and

join your group. Without you nothing would be possible. I have learned a lot from you in

class and also outside the class. It has been a real honor and great pleasure working with you.

The environment at AMPERE is full of brilliant and enthusiastic colleagues who have

provided me valuable help and discussions, the past and present members of Prof. Allard and

Dr. Lin-Shi group: Hocine Ziana, Florent Morel, Ludovic Menager, Mohanmed Trabelsi,

Lingbo Zhu, Nan Li, Bo Li and Yanyan Zhuang. I would like to thank AMPERE secretary

Sandrine Vallet, electrical engineers Pascal Bevilacqua and Abderrahime Zaoui. In addition, I

will never forget the assistance of my dear fellows during the research at IECE, Yanping Xu,

Minyan Zhang, Yi Zhang and Shaofeng Zhang. They made my life at IECE so pleasant.

Last but most important, my heartfelt appreciation goes toward my mother Gennv Huang,

father Zhenli Guo, who have always encouraged and supported me to pursue higher education.

With deepest love, I would like to thank my wife, Kaihua Wan, who has always been there

with her love, support, understanding and encouragement for all my endeavors.

i

Abstract

Being widely used in the new generation portable systems, the regulation requirement for

low-power high-frequency integrated DC-DC switching mode power supply (SMPS)

converter systems becomes more and more demanding in industry. The power level of this

kind of portable electronics is low from milli-watts for chip power management to several

watts for a monolithic power system, whereas it switches at very high frequency beyond

10MHz range. The challenges for these dedicated SMPS are emerging in terms of higher

dynamic response performances, less output ripple, smaller size and weight.

Although the analog control systems have proven successful in SMPS applications, there

are several reasons that make digital control attractive. The digital controllers are less

sensitive to external influences, re-programmable, more flexible and allow implementation of

more sophisticated control laws. They benefit from scalability and cost advantages of

standard digital CMOS process. The advantages of digital control have been recognized and

fast development of micro-processors (MCU, DSP, etc.) has been followed by the wider use

of digital systems in medium to high power applications with low switching frequency (kHz

range).

Despite being a popular research topic, digital control is still seldom applied in practical

low-power high-frequency integrated SMPS converters. Phones, PDAs and music/video

players are still mainly designed with analog PWM control inside the voltage regulator blocks.

This is mainly due to the apparent complexity of implementation, cost constraint and absence

of digital controller architectures that can support operation at switching frequencies

significantly higher than 1MHz with low-power consumption features. Broader acceptance of

digital techniques in low-power high-frequency SMPS is still hampered by practical problems

of the combination of cost issues, trade-off performances and power consumption.

However, with the rapid development of Very Large-Scale Integration (VLSI) technologies

and CMOS manufacturing technique, and associated with their design tools in the last decade,

it is now very possible to realize the high performance digital control in power electronics

system by high-speed low-power digital devices (FPGA, ASIC, etc). With these advantages,

the implementation of digital controller has become more feasible for low-power high-

frequency SMPS design in portable electronics applications.

The research interest of the thesis is to explore practical ways of incorporating advantages

of digital control in practical implementation, investigates issues of digital controller

implementation at lower power levels, gives detailed guidelines for digital controller design

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and hardware selection, and proposes new hardware solutions for the main functional digital

controller blocks. Two main objectives of this work focus the implementation of high-

resolution high-frequency digital PWM (DPWM) and high-performance digital control

algorithms for SMPS in FPGA-based realization.

To improve the output voltage precision and avoid limit cycling in digitally-controlled DC-

DC converters, the efficient DPWM is urgently expected to feature high-speed high-

resolution, low-power and small-area. In this thesis, two efficient architectures Hybrid dither

DPWM and Hybrid Delta-Sigma DPWM are proposed, which are addressed to increase

resolution and reduce power consumption simultaneously.

In order to improve the dynamic performance of digital controller and reduce the energy

consumption of algorithm computation simultaneously, a Tri-mode controller consisting of a

PID and robust RST controllers is proposed. The Tri-mode digital controller addresses

transient, steady-state and stand-by modes. To accommodate fast dynamic response, the RST

robust control-law is adopted in transient mode. In steady-state mode, the PID control law is

applied to minimize power consumption. While in stand-by mode if the converter is light-

loaded, then the controller is clocked at a frequency lower than the converter switching

frequency for consideration of energy consumption.

Due to the nonlinear characteristic in nature of SMPS system, a nonlinear Sliding-Mode

Controller (SMC) is developed to achieve the best possible transient performance under load

current change. A PID-type sliding mode, which is redefined as a DPWM-based controller to

meet practical limitations of variable and infinite frequency, is employed to regulate the

output voltage of a buck converter. Experimental results prove that this algorithm has

improved significantly the dynamic performance under load change.

The new digital blocks are implemented in a FPGA-based digital controller for a buck

converter. The experimental circuit includes a DC-DC Buck converter, the A/D converter, and

a Xilinx FPGA board. It has been proven that not only the efficient digital control at low

power levels is very possible, but also the digital control can achieve significant

improvements of dynamic performance. An ASIC implementation of the digital controller on

0.35µm CMOS technology is under process.

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Table of Contents

CHAPTER 1 INTRODUCTION ............................................................................................ 1

1.1 RESEARCH INTEREST: SIZE MINIATURIZATION FOR SMPS IN PORTABLE DEVICES .... 1 1.2 MOTIVATION: WHY DIGITAL CONTROL IN DC-DC SMPS? .......................................... 2

1.2.1 Analog Control in DC-DC SMPS .......................................................................................................... 2 1.2.2 Digital Control in DC-DC SMPS........................................................................................................... 4 1.2.3 Research Objective ................................................................................................................................ 6 1.3 Dissertation Outline.................................................................................................................................. 7

CHAPTER 2 LITERATURE ABOUT DIGITAL CONTROL APPLICATION IN LOW POWER HIGH FREQUENCY SMPS................................................................................. 10

2.1 ISSUES RELATED TO DIGITALLY-CONTROLLED SMPS................................................. 10 2.1.1 Resolution Requirement of the A/D Converter......................................................................................11 2.1.2 Resolution Requirements of DPWM .................................................................................................... 12

2.2 REVIEW OF ADC DESIGN IN LOW-POWER SMPS ........................................................ 14 2.2.1 Flash ADC ........................................................................................................................................... 16 2.2.2 Delay-Line ADC .................................................................................................................................. 17 2.2.3 Ring-Oscillator ADC ........................................................................................................................... 19

2.3 REVIEW OF DPWM DESIGN IN LOW-POWER SMPS.................................................... 21 2.3.1 Fast Counter-Comparator DPWM ...................................................................................................... 22 2.3.2 Delay-Line DPWM .............................................................................................................................. 23 2.3.3 Hybrid Delay-Line DPWM .................................................................................................................. 24 2.3.4 Segment Delay-Line DPWM................................................................................................................ 25 2.3.5 Ring-Oscillator DPWM ....................................................................................................................... 26 2.3.6 Segment Ring-Oscillator DPWM......................................................................................................... 26 2.3.7 Comparison of DPWM......................................................................................................................... 27

2.4 REVIEW OF DIGITAL CONTROL-LAW APPLICATIONS IN HIGH-FREQUENCY LOW-POWER SMPS ...................................................................................................................... 29

2.4.1 Classical PID Control.......................................................................................................................... 30 2.4.2 Multi-PID Control ............................................................................................................................... 31

2.5 SUMMARY ....................................................................................................................... 32

CHAPTER 3 HIGH-RESOLUTION DPWM DESIGN..................................................... 34

3.1 DESIGN OF A 11-BIT HYBRID DITHER DPWM............................................................... 35 3.1.1 Design of a 3-bit digital dither block................................................................................................... 35

A. Principle of Digital Dither Approach..................................................................................................................... 35 B. Determine the Bit Number of Dither ..................................................................................................................... 38 C. 3-bit Digital Dither Block ...................................................................................................................................... 40

3.1.2 Design of a 4-bit Segmented DCM Phase-Shift Block ......................................................................... 41 3.1.3 Design of a 4-bit Fast Counter-Comparator Block ............................................................................. 43

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3.1.4 Operation of the Hybrid Dither DPWM .............................................................................................. 44 3.2 DESIGN OF A 11-BIT HYBRID MASH ∆-Σ DPWM ........................................................ 47

3.2.1 MASH ∆-Σ Modulator Design ............................................................................................................. 47 A. Principle of ∆-Σ modulator .................................................................................................................................... 47 B. ∆-Σ Modulator Application in DPWM................................................................................................................... 49 C. Proposed MASH Second-Order DPWM ............................................................................................................... 51

3.2.2 Operation of the Hybrid ∆-Σ DPWM Scheme...................................................................................... 53 3.3 SUMMARY ....................................................................................................................... 55

CHAPTER 4 DESIGN OF A DIGITAL TRI-MODE CONTROLLER.......................... 57

4.1 SENSITIVITY FUNCTIONS FOR ROBUST CONTROL ........................................................ 58 4.1.1 Sensitivity Functions for SMPS............................................................................................................ 58 4.1.2 Robust Modulus and Delay Margins.................................................................................................... 60

4.2 DESIGN OF PID AND ROBUST RST CONTROLLERS ...................................................... 60 4.2.1 PID Control Design ............................................................................................................................. 61 4.2.2 Robust RST Control Design ................................................................................................................. 63 4.2.3 Simulation Comparison ....................................................................................................................... 69

4.3 TRI-MODE CONTROLLER BASED ON RST AND PID...................................................... 73 4.3.1 Design of a Tri-mode Controller.......................................................................................................... 73 4.3.2 Operation of the Tri-mode Controller.................................................................................................. 74

4.4 SUMMARY ....................................................................................................................... 76

CHAPTER 5 DESIGN OF A DIGITAL SLIDING MODE CONTROLLER ................. 77

5.1 REVIEW OF SLIDING MODE CONTROL .......................................................................... 78 5.1.1 Sliding Mode Controller: An Ideal Controller in Theory..................................................................... 78 5.1.2 Theory of Sliding Mode Controller ...................................................................................................... 78

5.2 SLIDING MODE CONTROL FOR DC-DC SMPS ............................................................. 80 5.2.1 Quasi-Sliding-Mode (QSM) Controller ............................................................................................... 80 5.2.2 Conventional HM-based SMC ............................................................................................................. 81 5.2.3 The Requirement of Fixed-Frequency SMC......................................................................................... 81 5.2.4 PWM-Based SMC ................................................................................................................................ 82

A. Equivalent Control................................................................................................................................................. 83 B. Averaged Duty Control .......................................................................................................................................... 84 C. PWM-Based SMC Replace HM-Based SMC........................................................................................................ 85

5.3 DESIGN OF A DPWM-BASED SMC................................................................................ 85 5.3.1 System Modelling for Sliding-Mode Controller ................................................................................... 86 5.3.2 Derivation of DPWM-Based SMC....................................................................................................... 88 5.3.3 Determination of SMC Parameters ..................................................................................................... 89 5.3.4 Derivation of Existence Conditions ..................................................................................................... 90 5.3.5 Stability for SMC ................................................................................................................................. 92 5.3.6 Matlab Simulation of SMC for a Buck Converter................................................................................ 92

5.4 SUMMARY ....................................................................................................................... 99

CHAPTER 6 EXPERIMENTAL VERIFICATION IN FPGA ....................................... 100

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6.1 BRIEF INTRODUCTION TO FPGA................................................................................. 100 6.1.1 VHDL And Design Flow .................................................................................................................... 101 6.1.2 Xilinx Virtex-II Pro FPGA Family ..................................................................................................... 103

6.2 TEST PLATFORM DESCRIPTION ................................................................................... 103 6.2.1 FPGA Board ...................................................................................................................................... 104 6.2.2 Buck Converter And Dynamic Load Board........................................................................................ 107 6.2.3 A/D Converter Board......................................................................................................................... 108

6.3 EXPERIMENTAL RESULTS............................................................................................. 108 6.3.1 Open-Loop Test for DPWM ................................................................................................................110 6.3.2 Closed-loop Operation .......................................................................................................................112

A. PID and RST Controller Operation.......................................................................................................................113 B. Tri-Mode Controller Operation.............................................................................................................................116 C. SMC Operation.....................................................................................................................................................118

6.4 SUMMARY ..................................................................................................................... 119

CHAPTER 7 CONCLUSION AND PERSPECTIVE....................................................... 121

7.1 CONTRIBUTIONS........................................................................................................... 121 7.1.1 Two Efficient DPWM Architectures Design ....................................................................................... 123 7.1.2 Tri-Mode Controller Implementation................................................................................................. 123 7.1.3 Sliding-Mode Controller Implementation .......................................................................................... 124

7.2 FUTURE WORK............................................................................................................. 125 7.2.1 Stability Analysis of MASH ∆-Σ DPWM ............................................................................................ 125 7.2.2 Observer for Output Voltage Derivation............................................................................................ 125 7.2.3 Application in DCM and Other Type SMPS....................................................................................... 125 7.2.4 ASIC Implementation and A/D Converter Design ............................................................................. 126

REFERENCE ....................................................................................................................... 127

CURRICULUM VITA......................................................................................................... 135

APPENDIX ................................................................................................................................I

APPENDIX A: MODULUS MARGIN ∆M AND DELAY MARGIN ∆Τ ...........................................I APPENDIX B: SMALL SIGNAL AND STATE-SPACE AVERAGING............................................III APPENDIX C: STATE-SPACE AVERAGING FOR BUCK CONVERTER ...................................... V APPENDIX D: SCHEMATIC CIRCUIT OF BUCK CONVERTER ............................................VIII APPENDIX E: SCHEMATIC CIRCUIT OF A/D CONVERTER................................................VIII APPENDIX F: TOP-LEVEL VHDL CODE FOR DIGITAL CONTROLLER................................IX APPENDIX G: TEST OF PID AND RST AT SWITCHING FREQUENCY 1MHZ...................... XV APPENDIX H: TEST OF PID AND RST AT SWITCHING FREQUENCY 2MHZ................... XVII APPENDIX I: TEST OF TRI-MODE AT 1MHZ AND SWITCHING FREQUENCY 2MHZ ........XIX APPENDIX J: TEST OF SLIDING-MODE AT SWITCHING FREQUENCY 1MHZ AND 2MHZ. XX APPENDIX K: INFORMATION ABOUT IC DESIGN OF THE DIGITAL CONTROLLER...........XXI

vii

Chapter 1 Introduction

1.1 Research Interest: Size Miniaturization for SMPS in Portable Devices

Compared with linear power supplies, Switching Mode Power Supplies (SMPS) provide

high efficiency, easy integration, small dimensions and weight. Due to these advantages,

SMPS have been widely used in numerous portable personal communication systems such as

cell telephones, MP3 player and other PDA products, which have grown explosively in recent

years. The power level of this kind of portable electronics is low, which starts from milli-watts

for on chip power management to several watts for a unitary power system. For example,

most portable devices use a battery of voltage between 5.5V when in charge, 3.3V during

discharge lifetime and down to 2.7V when empty, as well as the separate SMPS for

microprocessors and specific ICs, which require low voltage but high current output. They are

also used in a variety of applications including computer systems, wireless communication

systems, medical devices, motor drives, avionic systems, lighting, and consumer electronics.

With the application of DC-DC SMPS in the new generation portable systems and

embedded applications, new challenges are emerging in terms of high dynamic performances,

static output ripple, size and weight. Especially the miniaturization is always a critical

consideration for the portable devices. Even now in some portable application, the size of

DC-DC power converters is becoming the primary focus in the overall design. Therefore the

technology for high switching frequency operation to reduce size of passive components

(inductors and capacitors) to obtain miniaturization is urgently needed.

Because of the inverse proportion to the switching frequency, the size of passive elements

like transformers, inductors and capacitors can be reduced significantly at higher switching

frequencies. Advanced semiconductor integrated technology over the last decade has resulted

in a noticeable reduction in the size and weight of electronic components. It has been made

possible to allow for the realization of very compact and complex electronic functions. At the

same time, since power supply modules have usually to insure several output voltage levels, it

is essential to continuously increase the power densities of the SMPS by improving assembly

techniques and increasing their operating frequency.

1

Generally SMPS can be designed in single-phase or multi-phase architectures as shown in

Fig. 1-1. However the multi-phase converters are not suitable for the low-power SMPS in

portable system where the size is critical for the IC integration. Although multi-phase

architecture converters have the advantages for high current capability, low output voltage

ripple, and even can reduce the switching frequency to 1/N for an N-phase SMPS, the larger

size is their shortcoming in integration. Therefore the single-phase SMPS with high switching

frequency is receiving lots of research effort.

•••••• R

outi

Vin+-

1L

NL

C

2L

ADC XControl lawPWM

o u tVrefV

+

-eddutyN phase−

( )1PWM A

( )1PWM B

( )2PWM A

( )2PWM B

•••( )PWMn A

( )PWMn B

:1phase

: 2phase

:phase N

Fig. 1-1 A multi-phase interleaved DC-DC buck converter with N single-phase architectures

In high switching frequency operation, the efficiency of power conversion will suffer from

the high switching losses. High efficiency can be achieved only by zero voltage switching

(ZVS) operation with very low switching losses. This requires the separation of the switch

current and voltage transitions, and that can be accomplished only by a complex reactive

topology. It increases the size of power stage and results in poor controllability. It becomes

difficult to implement such a topology (e.g., the one used in a Class-E converter) on an IC

chip. Thus the case of ZVS, or resonant converters like Class-E SMPS is not discussed in this

work.

1.2 Motivation: Why Digital Control in DC-DC SMPS?

1.2.1 Analog Control in DC-DC SMPS

Historically because of its simplicity and low cost, most SMPS are operated with analog

2

controllers especially in low-power applications. The closed-loop operation offers large

performance in keeping the output voltage constant and restraining the overshoot during the

input voltage or external load changes. Presently most of the SMPS products are still

predominantly controlled by analog circuit control. A block diagram of analog controlled

buck converter is shown in Fig. 1-2.

The analog controlled SMPS operates as follows:

The output voltage and the desired voltage are compared, and then is obtained

the signal error . The error signal constitutes the input of the controller. The

controller can be realized by using an operational amplifier and a network of passive

components such as capacitors and resistors. The output of the controller is the control signal

. The Pulse Width Modulator (PWM) is used to transform the control signal into duty

ratio with the switching frequency

outV refV

ref oute V V= −

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sf .

Internal power stage

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C

R12

R21

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controller

Ramp Generator

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External Filter

CurrentLimiter

Soft start

u

R11 C11

PWMVout

Iout

Fig. 1-2 block diagram of the analog controlled buck converter

Fig. 1-2 is just a schematic diagram of an analog SMPS architecture. In fact for a practical

application, a number of passive components are needed to construct the compensator, or to

adjust the switching frequency, filter the switching noise, etc. It can be seen that the analog

controlled SMPS requires a lot of external passive components, and this architecture increases

the overall size of portable system. The analog components are sensitive to the environmental

influence, such as temperature, aging, noise, tolerance of fabrication, which results in lack of

flexibility, low reliability, not to mention the parameter auto-tuning and system diagnosis.

3

Besides it is difficult to apply sophisticated control algorithms with an analog approach

implementation. In addition, to meet the size miniaturization demand, the high switching

frequency sf is indispensable. However in higher switching frequency operation, the analog

controller signal transmission through the process will suffer from the limitation of

band-width and large gain variation. The variability of the integration technology is more

critical with higher switching frequency. Although analog control is still dominating in SMPS

applications, it is becoming less adequate to meet the complex requirements of higher

switching frequency for the reduction of passive components and improvement of dynamic

response in today’s portable devices.

1.2.2 Digital Control in DC-DC SMPS

Digital control is not new in the field of Power Electronics. Based on Digital Signal

Processor (DSP) or other processor, it has been applied for several years in motion control,

and in medium to high power line-frequency based application such as rectifier, inverters and

uninterruptable power supply (UPS). Generally these digital control systems present sufficient

resources to accommodate the modest switching frequency of the converter in the range of

kHz, where the PWM signals of interest is generated by DSP PWM core at low and medium

power application. In these medium to high power applications system, the size is not the

primary focus, neither the power consumption.

However for the battery-powered portable applications like cell phones and PDA products,

higher switching frequencies in the MHz and plus tens of MHz range are needed in order to

reduce the size of passive components. Such high switching frequency can not be achieved by

the traditional digital control mentioned above. Furthermore, the power consumption of

traditional DSP digital controllers are not critical in medium to high-power levels; while in

battery-powered system where it definitely results in low efficiency when this power

consumption is compared to output power. Moreover low-power portable applications are

driven by cost, which means the digital controller cost and complexity are very important.

Because the requirements of high speed, high frequency, small size, low power and low cost

are difficult to achieve simultaneously, most DSP and other microprocessor controllers are

either too expensive and complex, or too high power consumer, or too slow to be able to

perform the required high-performance and real-time control task.

4

In order to reduce size and improve the system performance, recently the digital controllers

in dedicated ASIC or monolithic IC rather than the traditional DSP has become an attractive

research topic in SMPS for high performance applications in portable electronics. Fig. 1-3

illustrates the block diagram of a digitally controlled buck converter. The digital controller

consists of three blocks: analog-to-digital converter (ADC), digital control law and digital

PWM (DPWM), and all these blocks should be integrated in one chip.

The digital controller SMPS operates similarly as the analog controller as follows:

The output voltage subtracted from the reference voltage results in the voltage error

. The ADC transfers the analog error to discrete in digital signals e[n:0]. During each

switching period, the error value is sent to the control law block, where the controller makes

algorithm calculation to regulate the output by new digital control duty d[m:0] of PWM ratio.

Through the DPWM block, the digital duty value is converted into time analog signal

outV refV

e

( )c t to

drive MOSFET switches.

Vin

DigitalPWM

Control Law

A/D Converter

Digital Controller

Vref

ed[m:0]

c(t)

+e[n:0]

-

NMOS

LC RPMOS

Vout

Fig. 1-3 block diagram of a digitally controlled buck converter

As shown in Fig. 1-3, the complete digital controller that contains three blocks (ADC,

Control-law and DPWM) can be realized totally on an IC chip, which significantly reduces

the size of the overall SMPS. The ADC can be designed using analog-to-digital CMOS

technologies at low cost. The algorithm calculation of control law can be implemented with

internal structure of logic circuit, without any external analog component. Thus the digital

controller should be less sensitive to environment than analog counterpart. Also digital control

law offers possibility to implement more sophisticated control strategies and other intelligent

interface functions that are impractical in analog. Another noticeable merit is that digital

controller signal transmission through the process can be used to address the limitation of

bandwidth and large gain variation that is associated with traditional analog approaches. In

addition by using the available automated design soft tools and Very-high-speed Hardware

5

Description Languages (VHDL), digital controller system design cycle can be accelerated,

and it offers a degree of programming flexibility to modify and update the product that is

impossible in analog counterpart.

From the comparisons between analog control and digital control mentioned above, it can

be seen that digital control in SMPS application has the advantages:

- Advanced control algorithms implementation

- Flexibility and programmability

- Size miniaturization and high frequency

- Less susceptible to component and variations

- Alleviation for the limitation of bandwidth and large gain variation in control law

1.2.3 Research Objective

With the rapid development of VLSI technology and digital CMOS technique, and

associated with their design tools in the last decades, it is now possible to realize the high

performance dedicated digital controller (ASIC or monolithic IC) for power electronics

system. With these advancements, the implementation of digital controller has become more

feasible for low-power high-frequency SMPS design in portable electronics applications.

Under the strict restraint of performance/cost, there are some issues to be considered about

the dedicated digital controller in practical implementation, such as the resolution, speed and

power consumption for ADC and DPWM blocks, the algorithm complexity, computation

speed and dynamic performance for Control-Law block, which are focused by many power

supply engineers. Therefore, large research attention has been paid to improve the

performance of ADC, DPWM and digital Control-Law for digital controller practical

implementation in high-frequency low-power SMPS in recent years. Thanks to the window-

ADC technique, the issue of high-speed low-power dedicated ADC for digital controller

design becomes less important. Thus the recent research on digital control has mainly focused

two areas. One is the methods to generate high-frequency high-resolution PWM signals to

meet the output voltage accuracy requirement and reduce the clock frequency requirement

simultaneously. The other is to develop high performance digital control algorithm that can

utilize the advantages of the digital controller so as to improve the dynamic performance of

the switching power converters.

6

In the research reported in this thesis, our goal focuses the issues of practical

implementation of high-performance digital controller for high-frequency low-power DC-DC

PWM switching converter. Key issues of digital controller such as ADC, Control-Law and

DPWM are introduced respectively. Thus the different candidates of ADC, Control-Law and

DPWM are summarized in the state-of-art. After the issues description, the research work

focuses on the design of high-frequency and high-resolution DPWM with low frequency

hardware clock, and implementation of the high-performance digital control-law at low-power

consumption. It should be noted that ADC is an important contributor to energy consumption.

Only a careful and dedicated design can solve the energy/accuracy trade-off for an integrated

ADC. This issue is not discussed in the dissertation and practical validations are performed

with FPGA and discrete ADCs.

The objectives of the thesis:

— Investigate existing implementation methods of digital control in DC-DC SMPS

application at low-power level and high switching frequency.

— Explore new architectures to increase DPWM resolution at higher switching frequency to

reduce size of passive component.

— Enhance the dynamic response performance by new digital controllers at high switching

frequency.

The monolithic integration of the digital controller is not addressed in the dissertation. Only

a fully-integrated digitally controlled SMPS would have rendered possible to perform tests

with more significant values (i.e. area and power consumption) and give a pertinent insight in

energy consumption. Due to the lake of time, it was not possible to layout an ASIC and obtain

the dies for test in the duration of the thesis. Experimental validation has been carried out on

FPAG board and a discrete high-frequency low-power DC/DC converter.

1.3 Dissertation Outline

The thesis is organized as follows:

Chapter 2 presents the state-of-art in digital control for high-frequency low-power

integrated DC-DC converter. It briefly introduces the basic structure of digitally controlled

switching converters and its main functional blocks. For the practical implementation of

digital controller, challenges and issues such as processing delay, quantization effects, limit

7

cycling and resolution of ADC and DPWM are detailed. Also the power consumption of the

digital controller issues such as DPWM architecture and digital computation requirements

(fixed-point, world length and calculation speed). Along with these issues descriptions, a

bibliography investigation of ADC, DPWM and control-laws applied in low-power SMPS in

recent years is detailed.

Taking the advantage of Digital Clock Manager (DCM) phase-shift characteristics available

on FPGA resource, Chapter 3 proposes two kinds of 11-bit high-frequency hybrid DPWM

architectures. One is the Hybrid dithering DPWM which can operate up to 2MHz (in the

selected FPGA), only requires system clock at 64MHz. Other is the Hybrid Sigma-Delta (Σ-∆)

DPWM which can operate up to 4MHz (in the selected FPGA), only requires system clock at

16MHz. The proposed hybrid DPWMs dramatically alleviate the clock requirement and can

allow higher switching operation for digitally controlled SMPS.

In order to obtain fast dynamic performance under load current change, in Chapter 4 a

so-called robust RST control law is adopted for low-power high-frequency digitally controlled

SMPS. For the sake of comparison a classical PID control is also designed. Considering the

computational power consumption of digital controller, a Tri-mode digital controller that

consists of RST and PID control laws is proposed to minimize power consumption in the

implementation. The idea of the Tri-mode controller is proposed for the consideration of

energy saving when SMPS is in steady-state and stand-by mode, and highest dynamic

performance when the external load features a transient change.

Chapter 5 introduces a DPWM-based digital Sliding-Mode-Control (SMC) for the high

frequency SMPS. As SMPS represents a particular class of Variable Structure Systems (VSS),

the sliding-mode controller can offer high dynamic performance and robustness. However

because of the SMC principles, the operation requires infinite switching frequency that

challenges the feasibility for SMPS. For the sake of completeness, we present the

conventional Hysteresis Modulator (HM) based SMC and reveal its shortage in practical

design. Also the requirement of fixed-frequency and the relationship between the equivalent

control and duty ratio control are derived. Thus a fixed-frequency DPWM-based digital SMC

is proposed to fix the very high and variable switching frequency in practical implementation.

The existence conditions for the sliding surface and the stability of SMC are also discussed.

Chapter 6 presents the practical FPGA-implementation of the proposed digital controllers

8

in low-power high-switching frequency SMPS based on a synchronous discrete buck

converter. FPGA board, test bench and design procedure are described. The proposed

DPWMs along with the proposed linear classical PID, RST, Tri-mode controllers and

nonlinear sliding-mode controller are implemented in a Xilinx FPGA. Experimental results

with constant switching frequency up to 4MHz (due to discrete component architecture

limitation) validate the functionality of the proposed digital controller.

Finally, Chapter 7 draws conclusions of the thesis and discusses some possible future work.

9

Chapter 2 Literature about Digital Control Application in Low Power High Frequency SMPS

2.1 Issues Related to Digitally-Controlled SMPS

Even though the advantages of digital control are very attractive and all of these

characteristics are suitable for digitally-controlled high-frequency low-power SMPS, there are

some issues that should be carefully considered in practical implementation.

A typical digitally-controlled synchronous buck converter which is widely used as voltage

regulator is shown in Fig. 2-1. The digital controller typically consists of analog/digital

converter (ADC), digital control law and digital PWM (DPWM) generator. Compared to

analog control, all tasks of digital controller are performed digitally with discrete signals. Power

Vbat

Switching Power Converter

L

CR

Vout (t)

PWM1

Nmos

C 2 (t)

Load

PWM2

Pmos

Gain

C 1 (t)

Dead time ADC

Control lawduty [m: 0] e [ n:0]

Vout [ n:0]

Vref [ n:0]C (t)DPWM

Digital Controller integrated in one chip

C 2 (t)

Fig. 2-1 A typical digitally-controlled synchronous buck converter

10

A lot of research has been performed in the domain of digital control for switching power

supplies and significant progress has been achieved. Initially due to the limit of digital CMOS

technologies, research attention was given mainly to the theoretical investigations of different

control methods [T1, Y1] that could utilize advantages of digital controller, but not enough

attention addressed practical implementation issues. Although these DSP digitally controlled

switching converter showed new features such as estimation and prediction techniques [T1,

Y1], implementation of nonlinear and fuzzy control law [P1], they operated at switching

frequency in range of tens of kHz [T1, Y1, P1, D1, C1] which made them inferior in

comparison to commercially available analog controlled system that usually operate at much

higher switching frequencies (>1MHz). Therefore broader acceptance of digital techniques in

low-power high-frequency SMPS applications is still hampered by a combination of issues of

cost, performance and power consumption.

Recently, thanks to the rapid development of VLSI technologies and digital CMOS

technique, more and more research focus on the practical implementation of high performance

digital control in low power portable electronics system. As it can been seen in Fig. 2-1, the

main issues are processing/sampling (ADC) delay, limited resolution of ADC and DPWM,

quantization error and limit cycle and requirements of real-time regulation, etc. Low-power

digital controller architectures are seldom available that can support operation at constant

switching frequencies significantly higher than MHz, which results in high power

consumption in control-law algorithm computation and DPWM generator. The power

consumption of controller is always compared with system output power, which causes a poor

efficiency in low-power portable system at high-frequency, where the analog counterparts

take less power.

2.1.1 Resolution Requirement of the A/D Converter

Normally analog control provides a very fine resolution in the output voltage. The output

voltage can be adjusted to any arbitrary value, which is only limited by loop gain and noise

levels. However because of the quantizing elements exist in the ADC and DPWM, the digital

controller has a finite set of discrete levels in nature. Thus the quantization of A/D converter

and DPWM is critical to both static and dynamic performance of power converters.

The need for a certain amount of accuracy in representing analog signals by their digital

equivalents governs the ADC resolution or the ADC number of bits. Resolution of the A/D

converter should be such that the output voltage error of power converter tightly falls within

the allowed voltage range. That is the least significant bit (LSB) of the ADC has to be

less than the allowed maximum scaled output voltage variation

( LSBV )V∆ ,

max

2 ADC

refLSB N

out

VVV V GV

= ≤ ∆ ⋅ = ∆ ⋅V

(2.1)

Where is the scaled factor of voltage sensor and, , and are the reference,

output and maximum output voltage respectively. Then the required resolution of

ADC with respect to a chosen reference voltage level can be acquired by:

G refV outV maxV

ADCN

11

max2int log out

ADCref

V VNV V

⎡ ⎤⎛ ⎞≥ ⋅⎢ ⎥⎜⎜ ∆

⎟⎟⎢ ⎥⎝ ⎠⎣ ⎦ (2.2)

Where function int[ ] takes the upper rounded integer value of the product.

Equation (2.2) indicates the minimum number of bits of the ADC to meet output voltage

regulation requirement of power converters. For example, a voltage regulator with 1.5V

reference voltage, 5mV allowed voltage variation, if 1G = and the voltage scale range of

ADC is 1.8V, then a minimum 9-bit resolution will be required for the ADC.

Hence any sensed voltage higher than should be scaled down to , and

appropriately reflected in feedback gain while designing the control loop. In a particular

SMPS application, the need for sensing output voltage or inductor current decides the

minimum required resolution, since the resolution should be higher than the tolerable output

voltage or inductor current ripple. The Higher the ADC resolution the faster would be the

system response as errors in the loop can have higher resolution and can be quickly corrected.

refV refV

Another important criterion for the choice of ADC is its conversion time and power

consumption from time of measurement at the input to the availability of the digital word at

its output register. Modern high speed ADCs still have around hundreds of nanoseconds of

conversion time. The conversion time can also be interpreted as the maximum allowable

sampling frequency sampf of an ADC. There are three important effects of conversion time

delay. Firstly, such a delay prevents immediate controller action due to this time delay and

secondly, its presence is a limit to the sampling frequency and hence limits the bandwidth of

the system. Finally for low-power high-frequency SMPS applications, the power consumption

of ADC is becoming critical with the increase in sampling frequency.

2.1.2 Resolution Requirements of DPWM

12

By nature the signal generated by the DPWM can only provide discrete duty cycle values.

Therefore the output voltage is also only a set of discrete output voltages. In order to ensure

steady state behavior in controlled variable, it is necessary that the resolution of the DPWM

output is higher than the resolution of the ADC. This is to make sure that any quantized

control value from output of DPWM can drive the control variable to a zero error in binary.

This is a necessary condition to avoid a low frequency oscillation called limit cycle oscillation

[A7, H4, Z3, J5]. Fig. 2-2 shows the output voltage behavior with DPWM resolution

lower and higher than ADC resolution respectively. It is essential that the resolution of the

DPWM should be high enough to avoid the limit-cycle oscillation phenomenon.

outV

A necessary condition to avoid the limit cycle oscillation is that the change in the

output voltage caused by one LSB change in the duty cycle ratio (

V∆

D∆ ) has to be smaller than

the analog equivalent of the LSB of the ADC. For the SMPS synchronous buck converter

widely used for voltage regulators,

max

2 2DPWM ADC

in outin N N

ref

V V VV V DV

∆ = ⋅∆ = ≤ ⋅ (2.3)

Where is the input voltage, inV DPWMN is the bit number of DPWM resolution.

VoutVoltage

t

Vref

VoutVoltage

t

Vref

DPWM levels ADC levels

0 LSB error-1 LSB error

1 LSB error2 LSB error

-2 LSB error

(a) limit cycle oscillationNDPWM < NADC

DPWM levels ADC levels

0 LSB error

- 1 LSB error

1 LSB error

- 2 LSB error

2 LSB error

(b ) non limit cycle conditionNDPWM > NADC

Fig. 2-2 Behavior of Vout with (a) DPWM resolution lower than the ADC resolution

and (b) DPWM resolution two times the ADC resolution

Thus the minimum number of DPWM is given as:

2max

int log refDPWM ADC

VN N

V D⎡ ⎤⎛ ⎞

≥ +⎢ ⎥⎜ ⋅⎝ ⎠⎟

⎣ ⎦ (2.4)

Where D is the duty ratio in steady-state /out inD V V= .

In order to avoid limit cycle oscillation, it can be seen from equation (2.4) that the number

of bits required for the DPWM generator, DPWMN , is at least larger by one bit than the ADC

resolution in steady-state, thus DPWMN is given by:

1+≥ ADCDPMW NN (2.5)

13

Indeed if the DPWM resolution is lower than the ADC resolution, there is no DPWM level

that maps into the ADC binary code corresponding to the reference voltage. In steady-state

the controller will be attempting to track the zero-error binary code. However due to the lack

of corresponding DPWM level, it will alternate between the DPWM levels around the

zero-error binary code (see Fig. 2-2 (a)). This will result in a non-equilibrium behavior, such

as steady-state limit cycling [A7]. Therefore it is very important to achieve a high resolution

in DPWM generation in digital control of DC-DC converters. Theoretically as long as the

clock frequency of the digital circuit is high enough compared to the switching frequency, the

limit cycle oscillation can be avoided. Unfortunately the required clock frequency will be too

high to be implemented efficiently.

The relationship between system clock clockf and switching frequency sf , is shown in Fig.

2-3 and can be written as:

2 DPWMNclock sf f= ⋅ (2.6)

and the DPWM resolution is determined by d∆1

2 DPWM

sN

clock

fdf

∆ = = (2.7)

1/fs

Ton Toff

resolution

Ton TonToff Toff

d∆

2 1DPWMN −

Fig. 2-3 Relationship between DPWM and switching frequency

For instance considering a buck converter with 3.3V DC battery input, 2V maximal output

voltage and switching frequency of 1MHz, in order to achieve 0.2% accuracy, a 10-bit ADC

is needed (see equation 2.2), and then DPWM should be at least 11-bit according to equations

(2.6) and (2.7). In this case a clock frequency larger than 2GHz would be needed. It becomes

too high to be practical.

A high resolution DPWM is required to eliminate limit cycle oscillations on output voltage.

However the increase in DPWM resolution implies the increase in system clock frequency.

The system clock reflects the power consumption of the digital control system in future ASIC

implementations. Moreover Electro-Magnetic Compatibility (EMC) is distributed over the

harmonics of the system clock signal. Higher frequency would mean a possible correlation

with communication signals in radio-frequency embedded systems for example.

2.2 Review of ADC Design in Low-power SMPS

14

As described above many portable devices are expected to require less tolerance of output

voltage and faster dynamic response. The precision with which a digital controller positions

the output voltage is determined by the resolution of the ADC module. For example, outV

regulation resolution of at 5mV 5inV V= corresponds to ADC resolution of

. Further topologies with low ADC latency are desirable in

the cases when the ADC is inside a feedback loop, since delays in the ADC correspond to a

phase shift that may degrade the loop response. Consequently the ADCs used in digital SMPS

controllers should have very low latency. Thus a high resolution and low latency ADC

topology is desirable for high dynamic performance in SMPS design. High resolution and fast

response are the most important of the required ADC design.

( )2 5 / 5 10ADCN log V mV bits= ≈

A wide choice of ADC architectures exist that differ in resolution, bandwidth, accuracy, and

power requirements. The major conventional ADC devices that are designed for general

industrial applications mainly have architectures of Parallel Flash ADC [J1], Successive

Approximation (SAR) ADC [S1, S2], and Pipelined ADC [K1, Y3]. However, both SAR and

pipelined ADC are operated with multiple stages, which introduce larger latency since they

need several cycles to convert the analog signal. Although multistage ADC topologies can

have high sampling rate, they have larger latency due to either multiple comparisons or digital

filtering. By contrast, the single stage flash architecture has the advantage of being very fast

because the conversion occurs in a single cycle. The performance of fast conversion is to meet

the demand of fast response in digital controller. Therefore the single stage flash ADC

architecture is preferable for the design of digital controller for these portable applications.

The main disadvantage of the flash structure is that it requires a large number of comparators

(2N-1 comparators for an N-bit ADC). With the example above, the 10-bit full range ADC will

require 1023 (210-1) comparators, which results in large silicon area and power consumption.

15

It can be seen that using a high resolution flash ADC that covers the full range between

ground and will demand excessive power and silicon area. However in PWM mode,

under normal operation the output voltage of the SMPS should not deviate substantially

from the reference voltage . Since is regulated to be in the vicinity of , and the

output voltage has to be quantized only over the regulation window around the

reference voltage , which is shown in Fig. 2-4. Thus an ADC that can handle a rail-to-rail

input is not necessary, and a so-called window concept [A7, A8, H3, J2, J3, J4, B1, N1, Z1, Z2]

of ADC topology can be conceived, which has high resolution only in a small window around

. The main idea of window ADC is to reduce the quantization window to the possible

variation range, which is usually tens of milli-volts centered around .

maxV

outV

refV outV refV

outV

refV

refV

refV

t

V

+3+2+10-1-2-3

e[n] binVout_upper

Vref

∆V

Vref -VoutADC error output

Vref = VoutVout_bottom

e[n]

V∆V(max)

+3

+2

+1

0

-3

-2

-1

Vref

∆VOnly a few bits of digital error

output

Fig. 2-4 Window ADC for the error between reference and output voltage

In recent years, based on the concept of window ADC, several alternative ADC such as

Flash ADC [A7, A8], Delay-line ADC [B1, H3, N1, Z1, Z2] and Ring-Oscillator ADC [J2, J3,

J4], have been proposed for digital controller in low-power high-frequency SMPS.

2.2.1 Flash ADC

A block diagram of a window flash A/D converter is presented in Fig. 2-5 [A7, A8,].

+_

+_

+_

+_

+_

+_

+_

+_

+_

+_

+_

+_

∆Vref

∆V=Vref -Vout

comparators2N

refV∆

2NrefV∆

2NrefV∆

2NrefV∆

2NrefV∆

2NrefV∆

Decoder2N to N

MSB

LSB

De

N-bitDAC

Dref

Fig. 2-5 Diagram of a Window flash ADC module [A7, A8]

16

The Digital-to-Analog Converter (DAC) converts the digital reference word to an

analog voltage , which is the input reference range of the ADC. Note that this DAC can

be slow compared to the response time of the regulator, since is constant, then a

number of comparators ( ) are connected to

refD

refV∆

refD

2NrefV∆ through an offset network with steps

2NrefV∆ , creating quantization bins around 2N

refV∆ . The controlled quantity of error

voltage is fed in the other input of the comparators. Note that, since ref outV V V∆ = − V∆ is

compared against , the resulting digital signal refV∆ ( )eD is the difference between the two,

which is like a window of digital representation for the error signal V∆ . Hence, the window

architecture implements both an ADC and an error amplifier.

For example if the regulation tolerance of the converter is 50refV mV∆ = , then will not

exceed ±50 mV around under normal operation. In this case ADC resolution of

seems reasonable to provide good control of within the tolerance window. Then only

ADC bins are required to cover the range of , which corresponds to

ADC resolution between 3-bit (2

outV

refV 10mV

outV

2 50 /10 10mV mV× = outV3 bins) and 4-bit (24 bins). Thus a 4-bit ADC is sufficient.

The window flash ADC has the advantage of fast conversion within only one cycle.

However if exceeds the range of the V∆ refV∆ window during a large transient, these

comparators turn all the converter on or off (depending on the direction of the transient), in an

attempt to clamp . To solve this issue, a larger window and faster comparators are needed,

which results in the cost increase of silicon area and power consumption.

V∆

2.2.2 Delay-Line ADC

In order to void the increase of silicon area and power consumption, a Delay-Line ADC has

been proposed in [B1, H3, N1, Z1, Z2]. The delay-line A/D converter is based on the

principle that the propagation delay of a logic gate in a standard CMOS process increases if

the gate supply voltage is reduced. To the first order, the propagation delay as a function

of the supply voltage dt

DDV is given by:

2(DD

dDD th

Vt KV V

=− )

(2.8)

where is the MOS device threshold voltage, is a constant that depends on the

device/process parameters and the capacitive loading of the gate. It can be observed that

increasing

thV K

DDV results in a shorter delay. For supply voltages higher than the threshold ,

the delay is approximately inversely proportional to thV

DDV . A possible alternative

implementation of the delay cell is shown in Fig. 2-6. To control the cell delay, additional

gates can be added to this cell implementation.

Delay cellVDD VDD

Input IOutput O

Supply voltage VDD

NORINVERTER

Reset R

17

Fig. 2-6 Possible implementation of the delay cell for the delay-line A/D converter [B1]

A basic delay-line A/D converter consists of a series of such delay units shown in Fig. 2-7.

A string of delay cells (consisting of logic gates) forms a delay line supplied from the sensed

analog voltage DD senseV V= . Each delay cell has an input, an output and a reset. SENSE

test VDD VDD VDD VDDVDD

R R R R R

delay cell

t1 t2 t3 t8

D D D DQ Q Q Q

q1 q2 q3 q8

Encoder

Digital output e

sample

Analog input Vsense

Fig. 2-7 Basic delay-line A/D converter configuration

Initially at the beginning of each switching cycle, a "start" signal is sent to the delay-line ADC.

After a fixed time ( sampleT ), a sampling pulse is generated and pass through a string of

D-flip-flop register; the output of each unit delay cell will be stored in a register. Fig. 2-8

shows timing waveform when the signal is transmitted at the sixth sampling moment,

[ ]00111111eD = , the output of low-voltage delay unit is "1", the high-voltage output units is

"0". When the reset input is active high, the cell output is reset to zero. Since the logic signal

transmitting speed has an inverse proportion to power supply DDV , the number of "1" of

sampling results will augment with the increase of power voltage DDV . The sampled tap

outputs ( to ) give the A/D conversion result in the “thermometer” code. Because this

operation is based on the thermometer code conversion, it needs additional coding circuit in

accordance with pre-set reference code to decode the error signal to the binary form. It should

be noted that a high resolution can only be achieved in a small window range of the ADC.

1q 8q

Startconversion

Endconversion

1

11

11

10

0

q= 11111100

e= -2

testt1

tdt2

t3

t4

t5

t6

t7

t8

sample

0 Ts

18

Fig. 2-8 Timing waveforms in the basic delay-line A/D converter

The basic delay-line A/D (shown in Fig. 2-7) converter results in a reference voltage

that is indirectly determined by the length of the delay line and by the delay-versus-voltage

characteristic of the delay cell. In practice because of process and temperature variations, the

reference value obtained by the basic delay-line A/D configuration cannot be precisely

controlled. Variations in the effective result in variations of the regulated output voltage,

and the power supply may fail to meet the specified static and dynamic voltage regulation.

Therefore, the delay-line A/D converter with the precise self-calibration ability against

process and temperature variations is needed. One Delay-line A/D converter configuration

with digital self-calibration [B1] is illustrated in Fig. 2-9.

refV

refV

The two conversions are performed in each switching period. In one half of the switching

period, the reference voltage is applied to the A/D converter. The result of the reference

conversion is ideally 0, but the actual value can be different because of process and

temperature variations. The reference conversion result is stored in a register. In the

second part of the period, the input analog voltage

refV

refe

refe

senseV is applied to the A/D converter, and

the result is subtracted from to obtain the (precisely calibrated) value of the error signal.

If desired, the reference conversion for the purpose of calibration of the delay-line A/D

converter does not have to be performed every switching period.

refe

2.2.3 Ring-Oscillator ADC

19

The block diagram of the ring-ADC [J2, J3, J4] is shown in Fig. 2-10, which is based on

the observation that the oscillation frequency in a CMOS ring oscillator. Biased in the

subthreshold region, it has a linear dependency on the bias current illustrated in Fig. 2-11. The

ADC consists of a simple analog block and a synthesizable digital block. A differential

transistor pair 1 2M M− drives two identical ring oscillators as a matched load. The bias

current is such that the voltage swing on the ring oscillator is below threshold. Thus, each ring

oscillator’s frequency is linearly dependent on its supply current. The error voltage

develops differential current in the two branches that results in instantaneous differential

frequency at the two oscillators. The frequency of each oscillator is captured by a counter that

is reset at the beginning of each sampling cycle. At the end of the cycle, one counter output is

subtracted from the other, and the result is used to calculate digitized error voltage .

Since there is uncertainty in the initial and ending phase, instead of looking at one output per

eV

eC eD

ring, all of the M taps on each ring oscillator are observed for frequency information. It can be

shown that, ignoring quantization error and assuming good linearity in the input differential

pair, is given by eC

1e m sampC Mk g T Vle e= (2.9)

where M is the number of taps on each ring, is the constant characterizing the ring

oscillator frequency sensitivity to bias current, is the transconductance of the input

differential pair, and

1k

mg

sampleT is the ADC sampling period, which equals the switching period

sT of the converter. Finally, digitized error voltage is calculated by scaling . Since

the saturation behavior of the input differential pair is dependent on the ratio of the input

signal and the overdrive voltage of the differential pair, good linearity of the input transistors

can be obtained by designing the overdrive voltage a few times higher than the differential

input voltage. Since is usually less than 100 mV, the overdrive voltage needs to be only a

few hundred millivolts.

eD eC

eV

testVDD VDD VDD VDD VDD

R R R R R

delay cell

t1 t2 t3tm

D D D DQ Q Q Q

q1 q2 q3 qm

Encoder

sample

Analog input Vsense

Vref

Register

Register

－＋

＋

eref

select

Digital output e

Fig. 2-9 Delay-line A/D converter configuration with digital calibration [B1]

Analog Bolck

Digital Block

VDD

Vo Vref

N

N

VSS

LevelShifter

LevelShifter

LevelShifter

LevelShifter

Counterl

CounterN

Counterl

CounterN

Σ

Σ

－

D1

D2

De

20

Fig. 2-10 A block diagram of Ring-Oscillator DAC

3.0E+06

4.0E+06

5.0E+06

6.0E+06

7.0E+06

4.E-07 5.E-07 6.E-07 7.E-07 8.E-07 9.E-07bias current Ibias (A)

freq

uenc

y

Fig. 2-11 frequency–current dependency of a ring oscillator biased in the subthreshold region

Compared to ADCs based on a Delay-Line, this ring-ADC has invariant resolution under

different reference voltage levels due to the common-mode rejection capability of the

differential pair and thus is suitable for a wide range of applications. Furthermore, the

resolution of the ring-ADC can be controlled through the bias current, which can be made

either constant or adjusted for automatic gain control (AGC). For example, the bias current in

the differential pair of the ring-ADC can be made a function inverse to the square of the input

voltage. Thus, when the input voltage is reduced, the gain of the ADC increases and, hence,

the controller gain is also raised proportionally, resulting in an invariant loop gain. The

quantization resolution of the ring-ADC can be scaled by changing the number of stages in

the ring and varying the bias current of the differential pair.

Table 2-1 shows a comparison for three kinds of window ADC architectures applied for

digital controller for low-power high-frequency SMPS.

Table 2-1 Speed, cost, power and accuracy comparison of ADC

Architecture Speed Cost Power Accuracy

Flash ADC Middle High High High

Delay-line ADC High Middle Middle Middle

Ring-oscillator ADC Middle High Middle Middle

2.3 Review of DPWM Design in Low-power SMPS

21

As shown in Fig. 2-1 the DPWM with the power stage acts as a D/A converter in the

system of digital close-loop control. Compared to analog controller, one of the critical blocks

of digital controller is DPWM generator, where the most important characteristic of the

DPWM is its resolution which has been described in section 2.1.2. A high resolution DPWM

is necessary to accomplish precise voltage and avoid undesirable quantization effects such as

limit-cycle oscillations.

Theoretically as long as the clock frequency of digital circuit is high enough compared to

the switching frequency, the limit cycle oscillation can be avoided. Unfortunately as it is

analyzed in section 2.1.2, the required clock frequency will be too high to be implemented

efficiently. Thus a high-frequency high-resolution DPWM circuit with reasonable clock

frequency is one of the challenges for successful practical realization of digital control for

switching power converters.

Recently, extensive research work [D7, R3, R4, R5, Y2, A9, A10, E1, A13, S9, M1, A6, A8,

J4, J2, J3, T2, H2, V1, B1, A7, O1, O2, N1, K2, Z1, Z2, A11] have focused the generation of

highly accurate time intervals for this purpose. Though a number of implementations are

possible, the chosen method should ideally minimize both area and power consumption. Some

of these typical methods are (1) fast counter-comparator [Y2, A9, A13, S9, M1], (2) delay-line

[A9, A10, A13], (3) hybrid delay-line [T2, H2, V1, B1], (4) segment delay-line [O1, O2], (5)

ring oscillator [A6,A8, J4, J2, J3], (6)segment ring-oscillator [N1, K2] and (7) digital dither

[A7].

2.3.1 Fast Counter-Comparator DPWM

One simple method to achieve high resolution in DPWM is to use a fast-clocked

counter-comparator scheme [Y2, A9, A13, S9, M1]. Fig. 2-12 shows the structure of fast

counter-comparator scheme. This implementation uses a cycling counter and a comparator,

setting a set-reset (SR) latch high when the counter value is zero and low when the counter

reaches the chosen duty-cycle value, [ ]1: 0d k − . In this scheme a system counter ( bits) is

used to generate the fixed sampling and the resolution of DPWM signals hereby is

k

1 2k . By

comparing counter value and the numerical duty cycle value (from control law), the switch of

the converter is turned on/off. This scheme has high linearity of the digital-to-time-domain

conversion and is very simple and easy to implement.

22

However in this circuit, a very high frequency clock frequency ( 2ksf ) and related fast logic

circuits are needed to achieve sufficient DPWM resolution at high switching frequency. For a

typical 11-bit resolution at a switching frequency of 1 MHz, a clock frequency exceeding 10

GHz is required, which is impractical in most applications and would also consume excessive

power.

A

BA=B?

A

BA=B?

S

RQ

k0

Counter

Clockk

Comparator

Duty Cycle d[k-1:0]

Comparator

PWMOutput

Fig. 2-12 Fast counter-comparator DPWM

2.3.2 Delay-Line DPWM

An alternative method to generate DPWM signal with high resolution at low power is to

employ a delay-line structure [A9, A10, A13] that takes advantage of the latency of common

circuit elements (e.g. logic gates, flip-flops, etc.) by connecting them in series, as shown in

Fig. 2-13. A pulse from the reference clock at the switching frequency sf will take a finite

time to pass through each delay components, so by “tapping” their individual outputs to the

inputs of a multiplexer it is possible to choose an amount by which to delay the signal. A

pulse-width modulated output may be generated by setting an SR-latch high when a pulse

enters the delay-line and low again when the pulse appears at the multiplexer output, having

been delayed by an amount determined by the selected tap. The total delay of the delay line is

adjusted to match the reference clock period.

m-Element Delay-LineClock

MUXm:1

Duty Cycle

d[(Log2m)-1:0]0 1 m-2 m-1

= Delay ElementPWM

OutputS

RQ

Fig. 2-13 Delay-Line DPWM

23

The power loss is significant reduced compared with the fast counter-comparator scheme as

the fast clock is replaced by a delay line, which operates at the switching frequency of the

converter. However, the disadvantage of this method is that the size of multiplexer increases

exponentially 2M with a resolution of M-bit. For 11-bit resolution this requires at least 2048

(211) delay stages and, consequently a very large silicon area. Besides when the switching

frequency fs is high, this kind of DPWM may be difficult to implement. For instance a 10MHz

DPWM featuring a 10-bit resolution requires delay cells with propagation time less than 101/ (2 10 ) 100MHz ps⋅ = . Such small time delay can be achieved only with the most advanced

and expensive IC fabrication technologies (0.12-µm CMOS and smaller technologies).

Moreover, the linearity of digital-to-time-domain conversion depends on the delay cell. Like

the delay-line ADC (section 2.22), the accuracy of delay propagation is sensitive to the

various effects such as temperature, manufacture process, voltage supply DDV , etc.

2.3.3 Hybrid Delay-Line DPWM

In order to reduce silicon area taken by large number of multiplexers and improve the

linearity of digital-to-time-domain conversion, a combination of the Fast Counter-Comparator

and Delay-Line architecture is proposed [T2, H2, V1, B1], which takes the trade-off between

the high frequency and the chip area. The so-called hybrid delay-line DPWM shown in Fig.

2-14 requires a relatively low frequency counter clock with a short delay-line and, thus, a

reduced-area multiplexer.

A

BA=B?

A

BA=B?

S

RQ

PWMOutput

MUX2m-k:1

2m-k-1

2m-k-2

1

0

2m-k-ElementDelay Line

= Delay Element

Comparatork-bit

Duty Cycle

Counter Comparatork-bit

d[m-1:0] d[m-1:m-k]c[k-1:0]

d[m-1:0]

k111...11

Fig. 2-14 Hybrid Delay-Line DPWM

24

In this implementation, the m-bit digital duty cycle [ ]1:0d m− is divided into LSB

for the delay tapping, and MSB [ 1:0d m k− − ] [ ]1:d m m k− − for counter-comparator. By

using a cycling counter and a comparator, a set-reset (SR) latch will be set high when the

counter value is zero and low once a pulse arrives at the tap of delay line selected by its

multiplexer for the time. Compared to the delay-line DPWM, for an M bits hybrid

delay-line DPWM, the number of multiplexers can be reduced from 2

thKM to 2M K− with a fast

counter-comparator at clocked frequency 2Ksf⋅ .

2.3.4 Segment Delay-Line DPWM

Based on the delay-line DPWM, another similar structure of the delay-line with multiplexer

scheme is the segmented DPWM [O1, O2], where the delay blocks are not of equal length,

but are assembled in a way that allows them to be driven directly by a digital code. For

example, a 6-bit DPWM with 3 segments of delay-line is shown in Fig. 2-15. Each segment

has a 4-to-1 multiplexer controlled by two bits of [ ]d n . The delay in each of the four elements

of the segment is given by (2):

2 14 16t t∆ = ∆ = ∆ 0t (2.10)

For 6-bit DPWM implementation with Delay-line DPWM, it will require delay cells

with fine-delay characteristic of . By contrast, with the implementation in segment

delay-line DPWM, only delay cells of fine-delay and coarse-delay are

required, of which 4 “coarse” cells with

62 64=

0t∆2 2 2(2 2 2 ) 12+ + =

2t∆ delay, 4 “moderate” cells with delay and 4

“fine” cells with delay. That greatly reduces the number of fine-delay cells and

consequently save the area and power consumption.

1t∆

0t∆

The segment delay-line DPWM has the benefit of reducing the total area required in system,

but also suffers from degraded linearity as well as delay-line DPWM.

Δt Δt Δt

MUX4:1d[3:2]

Δt Δt Δt

MUX4:1d[1:0]

Δt Δt Δt

MUX4:1

delaycells

d[5:4]

2 2 2 1 11 00 0

SR

Q

1/fs

DPWM

Coarse DelayDummy Loads

Fine Delay

clk

delaycells

Δt2 Δt1 Δt0delaycells

25

Fig. 2-15 Segment delay-line DPWM

2.3.5 Ring-Oscillator DPWM

A ring-oscillator DPWM scheme is presented in [A6, A8, J4, J2, J3], which has area and

power considerations similar to those of the delay line approach. In this scheme, the ring

oscillator in the DPWM runs in current starved mode and by adjusting the supply current

frequency can be controlled in the entire ring. The ring frequency obeys the relationship:

/avg load swingf I C Vα= ⋅ ⋅ (2.11)

Where avgI is the current supplied to the ring-oscillator, is the equivalent capacitor in

the ring, loadC

swingV is the voltage swing in the ring, and α is a technology coefficient. Thus the

switching frequency of the converter can be controlled by adjusting the ring oscillator current.

A DPWM scheme using ring-oscillator for 4-phase application is shown in Fig. 2-15. The

scheme is composed of 128 differential stage ring oscillators which yield 256 symmetrically

oriented taps, and a 256-to-4 Mux that can select the appropriate signals from the ring. During

the operation, a square wave propagates along the ring. When the rising edge reaches tap zero

in the ring, the rising edge of the PWM signal for phase one is generated. The falling edge of

this PWM signal is generated when the rising edge of the propagating square wave reaches a

specified tap in the ring.

Diff_Inv Diff_Inv Diff_Inv Diff_InvX_1(m)

X_2(m)X_N-1(m)

X_N(m)

8 bit

Duty Cycle256/4 MUX

4

Level Converters

4 Channel PWM turn-off signals

Ring Element

in 1

in 2

out 1

out 2

Fig. 2-16 A 4-phase 8-bit Ring-Oscillator DPWM

Although this scheme has also the limitation of linearity and sensitivity to variation, it has

the advantage of symmetric structure. Since the different phases can be tapped out from

symmetric positions on the ring, this technique is especially suitable for multiphase PWM

generation such as digitally controlled multiphase SMPS.

2.3.6 Segment Ring-Oscillator DPWM

26

In ring-oscillator DPWM, the number of ring-oscillators and multiplexers increase

exponentially (2M ) with the number of resolution bits M, which results in an increase in area.

Like the segment delay-line, the trend of segment ring-oscillator structure [N1, K2] is to

reduce the area and power consumption. Segment blocks contain ring-oscillator are not in

equal length, but are assembled in a way that allows them to be driven directly by a digital

code. An 8-bit DPWM with segment ring-oscillator architecture is shown in Fig. 2-17.

d[n]

fsw[n]

8-bit 4-bit

Current SourceBiasing

Current SourceBiasing4-bit

st

dLSB[n]MUX-A MUX-B

S

R

Qc(t)

dMSB[n]

En

10 2 3 14 15 15 14 13 2 1 0

Fig. 2-17 Segment Ring-oscillator DPWM

It consists of two 16:1 multiplexers and two sets of delay lines connected as a ring. The

first delay line consists of 16 fast delay elements in series. Each intermediate node is passed

onto a 16:1 multiplexer (MUX-A), whose selected signal are the 4 LSB of the digital duty

ratio [ ]d n .The second delay line consists of 16 slow delay elements in series. These delays

are 16 times slower than the fast delay elements. The outputs of slow delays are connected to

a second 16:1 multiplexer (MUX-B). The selected 4 MSB signals for the MUX-B are

connected in reverse order, such that the MSB of [ ]d n is tied to the LSB of MUX-B. In this

way, the 4MSB of [ ]d n define the start point of the pulse-width modulated signal that sets

the SR latch. The 4LSBs of [ ]d n , connected to the selected input of MUX-A, are not

reversed and define the end point of the fraction of switching period during which the PWM

signal is high. This connection always ensures that the signal stop point is defined by 4LSB

and hence an accurate duty ratio adjustment is achieved. It can be seen that the DPWM can be implemented with very small hardware. It takes only

1/15 of the resources needed for the implementation of a conventional 8-bit ring-oscillator

based DPWM that employs a large 256:1 multiplexer.

2.3.7 Comparison of DPWM

27

Fast Counter-Comparator has the advantage of excellent linearity in the digital-to-time

domain conversion. For an n-bit DPWM and a switching frequency sf , it uses a clock 2nsf⋅ to

divide the time period 1s sT = f . The drawback exists evidently that the power consumption is

very high when the DPWM requires a high resolution. The Delay-Line, Segment Delay-Line,

Ring-Oscillator can be seen as the same type of DPWM structure that uses the logic delay cell

to get delay time. Although this kind of DPWM can achieve much higher resolution than the

counter-based DPWM, it requires larger silicon area than the fast Counter-Comparator one.

Besides, when the switching frequency sf is higher, the delay cell may be difficult to generate.

For instance, a 10MHz Ring-Oscillator DPWM having 10-bit resolution requires cell whose

propagation time is less than 100ps. Such small time delay can be achieved only with the most

advanced and expensive IC fabrication technologies (0.12-µm CMOS or smaller). Moreover

the accuracy of the delay time of the delay-cell is limited due to variations in the operating

temperature, manufacturing process and the supply voltage. Hybrid Delay-line DPWM

combines the counter comparator with the delay line as a trade-off between the high frequency

and the chip area. Table 2.2 shows the comparison of area, power, accuracy and suitability for

multiphase DPWM architectures in SMPS.

Table-2.2 Area, power, accuracy and suitable for multiphase comparison of DPWM Architecture Area Power Accuracy Easy for multiphase

Fast counter-comparator Low High High - Delay-line High Middle Middle - Hybrid Delay-line Middle Middle Middle - Segment Delay-line Low Low Low - Ring-oscillator High Middle Middle √ Segment Ring-oscillator Low Low Low √

28

Unlike those hardware DPWMs mentioned above which either rely on high-power

consuming counters or use the most advanced and expensive CMOS technologies for tight

delay cells, digital dithering [A7] and Delta-Sigma (∆-Σ) [R6, D2] are practical soft methods to

increase effective resolution of DPWM. Digital dithering is implemented using averaging

process based on average principle [A7], and ∆-Σ is realized using noise-shaping technology

[R6, D2]. They both have been proved two effective methods to minimize hardware

requirements of DPWM, and consequently able to design a high-resolution DPWM in software

way without increasing chip area and power consumption. Especially when DPWM comes to

practical implementation in FPGA-based system, a very attractive digital technique, the Delay

Locked Loop (DLL) [M3] has been recently proposed. It utilizes the available DLL phase-shift

functional blocks on the FPGA to reduce the required clock frequency. In these DLL

architectures, the few MSB are implemented using the counter comparator and LSB are

implemented using the single/or segmented DLL phase-shift.

Based on the advantage of DLL phase-shift characteristics available on FPGA resources, in

this work we propose two hybrid 11-bit DPWMs which associate with digital dithering and ∆-Σ

modulators respectively. One is the hybrid dither DPWM which takes the digital dithering

approach and combines a DLL phase-shift block with a counter comparator. The other is the

hybrid ∆-Σ DPWM which takes the multi-stage ∆-Σ modulator and combines a DLL phase-shift

block with a counter comparator. The two hybrid DPWMs along with the digital dithering

approach and the ∆-Σ modulator will be detailed in Chapter 3.

2.4 Review of Digital Control-Law Applications in High-frequency Low-Power SMPS

Although the application of advanced ADC architectures (described in section 2.2) and

DPWM schemes (described in section 2.3) can improve output voltage accuracy, relax the

quantizer effects and limit cycle in SMPS, it should be noted that achieving high accuracy of

output voltage is only one part of the digital control. As it was mentioned early, the most

important advantage of digital control is to enable implementation of advanced control laws

that are always difficult to realize in analog control, especially it breaks bandwidth limitations

with respect to analog control at high-frequency [A4].

Thus as shown in Fig. 2-1, a more important part is to apply advanced control algorithm

that can take advantages of digital circuits and improve the dynamic performance of the

SMPS. Considerations of complexity, dynamic performance, cost and calculation speed, area

and power consumption, should be evaluated comprehensively in design of digital control law.

For example, a SMPS with 10MHz switching frequency has the period time of only 100ns.

Such short time is critical for general DSP controllers to accomplish all the tasks, such as A/D

conversion, DPWM generation and algorithm calculation, etc.

29

A number of research studies have been performed on advanced digital control algorithms

applied in low-power high-frequency SMPS for portable system. Basically, most of them are

implemented by DSP in voltage control way or current control way, such as linear PID,

nonlinear predictive control, adaptive control, slide mode control and fuzzy control etc.

Thanks to digital control technique, these control algorithms are employed to improve

dynamic performance as well as static performance in digitally controlled SMPS. Because of

the limit in calculation speed of DSP, the operation frequency of these advanced control laws

are limited in range of kHz which is much lower than the analog controller in SMPS.

Due to the restraint of complex/performance in digital controller, most of the digital

controllers in ASIC standard implementation [A1, A3, A7, B1, J2, J3, T2, Z1, Z2] employ the

PID algorithm in high-frequency lower-power SMPS. Also there several multi-PID control

algorithms [A12, S11] have been applied in ASIC standard implementation for SMPS. This

section will briefly review some typical control methods that have been applied in ASIC

standard implementation for digitally controlled SMPS.

2.4.1 Classical PID Control

In order to save area and calculation time, most of the existing digital controller in ASIC

standard implementation [A1, A3, A7, B1, J2, J3, T2, Z1, Z2] are with linear PID control.

Among these digital PID control controllers, a so-called Look-up Table PID [A1, A2, B1,

T2] associates with a window-ADC is typically employed in ASIC standard implementation

shown in Fig. 2-18. The goal of Look-up Table PID is to reduce area and/or clock frequency

and window-ADC (described in section 2.2) is to alleviate the range requirement for the A/D

converter itself. Since in the window-ADC, the error ( )e n signal can be represented with

only a few bits, it leads to an easier implementation of the compensator to reduce the chip

area. Taking advantage of the fact that only a few bits are used to represent the error signal

the look-up table compensator is proposed. The current and the previous values of the

digital error signal serve as address/ or index to read the corresponding location in the

look-up tables. Since the error signal

( )e n

( )e n

( )e n can take only a few different values, the number

of entries in the look-up tables is relatively small, and as a result the implementation area is

also small. In addition, the computation can be done in a single or in a few clock periods, so

that the clock frequency requirements are also low.

The general control law supported by the configuration shown in Fig. 2-18 is given by:

[ ] [ ] [ ] [ ] [ ]1 1d n d n a e n b e n c e n+ = + ⋅ + ⋅ − + ⋅ −1 (2.12)

30

Where a, b, and c are constants and can be updated by the Look-up table programming

interface, d[n] and d[n+1] are duty values corresponding to the basic PID control law. The

look-up table PID compensator can be programmed to achieve a desired closed-loop

bandwidth and adequate phase margin by choosing the coefficients, simply by programming

the entries in the lookup tables. As alternatives to the external memory, the tables could be

easily preprogrammed and hard-wired on the chip at design time, or programmed from other

system components via a suitable interface at run time.

It can be seen that the digital PID control is simple and easy to implement at low cost and

calculation time. However, due to the time delay effect and nonlinearity characteristics of

DC-DC power converter, it is difficult for a linear PID to acquire high dynamic performance

over wide operating condition and parameter range.

Table A

Table B

Table C

Ts

Ts

+

Ts

d[n+1]

d[n] e[n-1]

e[n-2]

e[n]

-4-3-2

0+1+2+3+4

-1

Vq

e

Vref V0

(ΔV0)maxVref

SENSE

DPWM

Digitalpulse-widthmodulator

Systemclock

Programmable compensator

Look-up table programming interface

External memory

OUT

c(t) Ts

dTs fs=1/TsVsense

Windows A/D converter

Fig. 2-18 Look-up table PID compensator with Window ADC

2.4.2 Multi-PID Control

31

In practical implementation, substantial parameter changes or external disturbances lead

to a sharp decrease in PID control performance. In the presence of disturbances, one set of

parameters of PID controller is usually faced with a trade-off between fast response with

significant overshoot and smooth but slow response. Thus based on the classical PID control,

the multi-PID controller has been proposed and implemented in ASIC application for SMPS.

The goal of the multi-PID is to adopt different sets of control parameters when the SMPS

output voltage located in different situations. The regulation rule of improved PID can be

drawn in IF-Then rules as below:

IF the output voltage is 10 outV V< < , or/and system located in situation ; 1S

Then the digital PID parameters are set [ ]1 1 1, , a b c ;

i i i i i i i

IF the output voltage is 1N out NV V V− < < , or/and system located in situation NS ;

Then the digital PID parameters are set [ ], , N N Na b c ;

For instance in [A12], two sets of PID parameters are used to improve the large signal

dynamic performance. One set of PID controller parameters, which has higher phase margin

and lower bandwidth, is used to regulate the converter under small signal response and steady

state. The second set of PID parameters, which has higher bandwidth and lower phase margin,

is used to regulate the converter when the output voltage derivation exceeds a predefined level.

In this way, the dynamic performance and efficiency of power converter are improved.

Similarly three sets of PID parameters are used in [S11] for three situations: , 0 out refV V< <

( ) ( )ref out refV V V−∆ < < +∆ and , where ( )ref outV +∆ <V ∆ is the error voltage chosen by user.

Under such a configuration, it is possible to realize a controller that has an optimal

performance for all operating conditions. However with the increase of situation number N,

the multi-PID will become complicated with large numbers of PID parameters and result in

increase of area in ASIC.

2.5 Summary

In this chapter, a comprehensive literature study for the digital control application in

low-power high-frequency SMPS was presented. Advantages of digital control application are

very attractive. However in the practical application, the issues exist as well as their merits.

32

The main issues of digitally controlled SMPS consist of resolution requirement and time

delay of ADC, resolution of DPWM, high-performance algorithm with high-speed

computation, etc,. An overview of ADC design for low-power high-frequency digitally

controlled SMPS was addressed in section 2.1. Different from the conventional

analog-to-digital converter, the dedicated window-ADC consumes less power while providing

enough effective analog-to-digital conversion. Thanks to the advanced CMOS technologies

and the window-ADC techniques, the challenge of speed and resolution of ADC is becoming

a less important issue in high-frequency SMPS application. In recent years efforts have been

made to obtain high resolution DPWM was described in section 2.3. Power consumption is

always the critical consideration in DPWM design. The digital control approaches applied in

low-power high-frequency SMPS were presented in section 2.4. Unfortunately, most of these

applications were implemented by DSP. They were either too simple to acquire high dynamic

performance though they can run at middle switching frequencies; or too complicated to

increase switching frequency though it can improve the dynamic performance. Due to the

restraint of complex/performance in digital controller, most of the digital controllers in ASIC

standard implementation employ the PID algorithm, and the dynamic performance is still

limited.

As for the implementation of digital controller, the conventional DSP is not adequate to

meet the requirements of high resolution DPWM and complex algorithm calculation at higher

switching frequency imposed by reduction of passive components. The main challenge of the

practical implementation of digital controller in low-power high-frequency SMPS is to reduce

the power consumption related to the high-resolution DPWM and ADC on one hand, and

increase computation speed for control algorithm (i.e. increase switching frequency) on other

hand. Thanks to the rapid development of VLSI technologies and digital CMOS technique, it

is feasible now to design all the three parts (ADC, DPWM and Control-Law) together as a full

digital controller in ASIC standard implementation to replace the discrete DSP control system.

33

The next chapter will provide the detail of two kinds of hybrid DPWM architecture, which

can operate in frequency range of hundreds of kHz to tens of MHz.

Chapter 3 High-Resolution DPWM Design

As described in Chapter 2, static and dynamic output voltage regulation capabilities

depend on the characteristics of the ADC resolution, the discrete set of duty ratios and

ultimately the discrete set of achievable output voltages depends on the DPWM resolution. If

the resolution of ADC and DPWM is not sufficiently high, an undesirable limit-cycle

oscillation may occur [A7, H4, Z3]. The requirement for a high-resolution ADC and DPWM is

an important consideration in the realization of digitally controlled low-power high-frequency

SMPS. Thanks to the advanced CMOS technologies and the windows ADC techniques, the

challenge of speed and resolution of ADC is becoming a less important issue. Because the

final ASIC implementation of the full digital controller is not available in the time of this

work (before April 2009), Thus the ADC design is not discussed in the dissertation and

practical validations are performed with FPGA and discrete ADCs.

High resolution DPWM is then the key module to restrain the undesired limit cycle.

Several alternative solutions have been proposed in recent years for high-resolution low-power

DPWM architectures reviewed in Chapter 2, such as the hardware methods: delay-line, hybrid

delay-line, segment delay-line, ring oscillator, segment ring-oscillator and Delay Locked Loop

(DLL), and the soft methods: digital dither and ∆-Σ modulator. These architectures can

increase DPWM resolution to some extent, however they either entirely rely on hardware

method such as the most advanced and expensive CMOS technologies for tight delay-cell/ or

ring-oscillator, or completely depend on soft method such as digital dither and ∆-Σ modulator.

In order to increase resolution and reduce power consumption simultaneously, the soft

methods and hardware resources should be fully utilized as furthest as possible. Based on the

advantage of DCM (Digital Clock Management) phase-shift [M3] characteristics available on

FPGA resources, in this work we propose two hybrid 11-bit DPWMs which associate with

digital dithering [A7] and ∆-Σ modulator[R6, D2] respectively. One is the hybrid dither DPWM

which includes a 3-bit digital dithering approach, a 4-bit DLL phase-shift block and a 4-bit

counter comparator. The other is the hybrid ∆-Σ DPWM which contains a 5-bit multi-stage ∆-Σ

modulator, a 4-bit DLL phase-shift block and a 2-bit counter comparator.

34

3.1 Design of a 11-bit Hybrid Dither DPWM

The idea of the hybrid dither DPWM architecture is to take the advantage of the

combination of hardware method (counter comparator and DLL phase-shift) and soft method

(digital dither) to alleviate the requirement of high frequency clock and reduce power

consumption. The proposed FPGA-based DPWM includes three blocks: 3-bit digital dithering

approach, 4-bit segmented DCM phase-shift and 4-bit counter comparator. As a consequent,

for operation at switching frequency fs, the counter comparator block merely needs a 24·fs

clock instead of the 211·fs, which dramatically alleviates the high clock frequency requirement.

Fig. 3-1 shows the schematic diagram of the hybrid dither DPWM. Each block will be

detailed in next sub-sections.

sf

fromd[10:0]

control-law

Digital dithering3-bit

approach

D[7:0]

D[7:4]Counter

Comparator

4-bit

D[3:0]

4-bit Segmented42 sf⋅

DCM Phase-ShiftSc

PWM

42 sf⋅

Fig. 3-1 A schematic diagram of proposed hybrid dither DPWM

3.1.1 Design of a 3-bit digital dither block

A. Principle of Digital Dither Approach

Analog dither has proved its efficiency for increasing the resolution of a PWM module [S3].

However it is difficult to generate and control as analog dither is sensitive to variations of

analog component values and it can only be mixed with analog signals in the converter and

not with signals inside a digital controller. On the contrary digital dither [A7] can be

generated inside the digital controller and it is easier to implement and control. Moreover it

does not suffer from the problem of component value variations. It is designed in a straight

forward manner in a FPGA using digital logic circuits.

The basic principle of digital dither is detailed in [A7]. It consists to distribute the

LSB of the duty value as 1-bit value of “0” or “1” in a pre-scheduled sequence, and put the

specific LSB effects into hardware MSB during an averaging process. The

bits duty value from control law will be modified in an averaging distribution

over switching cycles, so that the equivalent duty value is shaped in the value range of

adjacent quantized levels. By using dither method, the hardware bits DPWM

dithN

CoreN

( Core dithN N+ )2 dithN

2 dithNCoreN

35

can be increased by bits: ditherN

DPWM Core dithN N N= + (3-1)

where DPWMN is equivalent as the DPWM effective bit number. By using dither methods, the

LSB bit of the duty value is alternating between “0” and “1” in a specific look-up table

pattern during the switching cycles. As a result, the effective DPWM resolution can be

increased by bits. Fig. 3-2 shows the general schematic diagram of digital dither

implementation, where f

2 dithN

dithN

s is switching frequency. In order to avoid poor output regulation and

limit cycles, a rectangular-waveform [A7] dither pattern (shown in Fig. 3-3) is adopted.

sf Ndith -bitcounter

from control-law

(NCore+Ndith )

2Ndith x 2Ndith

Ndith

1-bitdither Ncore -bit

Saturated adder

row index

line indexlook-up table value

NCore

To Core DPWM

NCore

Fig. 3-2 Structure for adding arbitrary dither patterns to the duty cycle

For instance of a 2-bit dither approach, Fig. 3-3 shows how the dither schema realizes the

digital dithering during 22 duty cycles and Table 3-1 shows the dithering pattern [A7], where

Dc1 and Dc2 are two adjacent initial quantized levels with Dc2 = Dc1 + LSB. It can be seen that

when the duty value changes between Dc1 and Dc2 in a dither sequence during every 22

switching periods, a corresponding sub-bit level can be implemented by averaging over 4

switching cycles. Ts

time

average dutyDC1

DC1+1/4 LSBDC1+2/4 LSBDC1+3/4 LSBDC2=DC1+ LSB

LSB

Fig. 3-3 Scheme of 2-bit rectangular-waveform dither pattern

Table 3-1 2-bit digital dithering look-up table

2-bit LSB 22 switching cycles (row index) Sequence

(line index) 0 2 3 1 average

00 0 0 0 0 0 01 0 0 0 1 1/4 10 0 1 0 1 1/2 11 0 1 1 1 3/4

36

The dither method has advantages such as simple and easy implementation, and high

DPWM resolution can be achieved in high switching frequency without increasing the clock

frequency and power consumption. However, dither comes not free. The dithering of the duty

value results in duty ratio error and increases additional AC ripple at the output LC filter.

Considering the instance above, when the 11-bit duty ratio changes from 0.500244 to

0.503664 by 1-bit LSB per switching cycle, the dithering schema and look-up table for the

3-bit dither pattern are shown in Fig. 3-4 and Table 3-2 respectively. The comparison of

dithering results between 2-bit dithering and 3-bit dithering are respectively shown in Table

3-3 and Table 3-4. It can be seen that the duty ratio error (shadow area) of 3-bit dither pattern

is two times that of 2-bit dither pattern, and the duty ratio error will increase by double per

1-bit augment in dither. It is clear that the longer bits the dither patterns used, the larger the

duty ratio error (i.e. the larger the AC ripple). The higher output ripple increases and

sub-harmonic may occur, which may cause EMI problem during the operation. Thus this

consideration puts a practical limit on the number of dither bits that can be added to increase

the resolution of the DPWM. Ts

DC1+1/8 LSB

time

average dutyDC1

LSBDC1+2/8 LSBDC1+3/8 LSBDC1+4/8 LSBDC1+5/8 LSBDC1+6/8 LSBDC1+7/8 LSBDC2=DC1+ LSB

Fig. 3-4 Scheme of 3-bit rectangular-waveform dither pattern

Table 3-2 3-bit digital dithering look-up table 3-bit LSB 23 switching cycles (row index) Sequence

(line index) 0 5 4 2 7 3 6 1 average 000 0 0 0 0 0 0 0 0 0 001 0 0 0 0 0 0 0 1 1/8 010 0 0 0 1 0 0 0 1 2/8 011 0 0 1 0 0 1 0 1 3/8 100 0 1 0 1 0 1 0 1 4/8 101 0 1 0 1 1 0 1 1 5/8 110 0 1 1 1 0 1 1 1 6/8 111 0 1 1 1 1 1 1 1 7/8

37

Table 3-3 A 11-bit digital dithering in 2-bit pattern

2-LSB counter

desired duty value (11-bit)

desired duty ratio

Dither value

actual duty value (9-bit)

actual duty ratio

duty ratio error

0 10000000000 0.500244 0 100000000 0.500979 0.0735% 1 10000000001 0.500733 1 100000001 0.502935 0.2202% 2 10000000010 0.501221 1 100000001 0.502935 0.1714% 3 10000000011 0.501710 1 100000001 0.502935 0.1225% 0 10000000100 0.502198 1 100000010 0.504892 0.2694% 1 10000000101 0.502687 1 100000010 0.504892 0.2205% 2 10000000110 0.503175 1 100000010 0.504892 0.1717% 3 10000000111 0.503664 1 100000010 0.504892 0.1228%

Table 3-4 A 11-bit digital dithering in 3-bit pattern

3-LSB counter

desired duty value (11-bit)

desired duty ratio

Dither value

actual duty value (8-bit)

actual duty ratio

duty ratio error

0 10000000000 0.500244 0 10000000 0.501961 0.1717% 1 10000000001 0.500733 1 10000001 0.505882 0.5149% 2 10000000010 0.501221 1 10000001 0.505882 0.4661% 3 10000000011 0.501710 1 10000001 0.505882 0.4172% 4 10000000100 0.502198 1 10000001 0.505882 0.3684% 5 10000000101 0.502687 1 10000000 0.505882 0.3195% 6 10000000110 0.503175 1 10000001 0.505882 0.2707% 7 10000000111 0.503664 1 10000001 0.505882 0.2218%

B. Determine the Bit Number of Dither

In order to determine how many bits can be used under the maximum peak-to-peak voltage

ripple produced by dither in rectangular-waveform dither pattern, some useful

mathematical analysis (see [A7] for details) can give an estimate of the relation between

maximum peak-to-peak voltage ripple produced by the dither and the number of

dither bits .

_p p ditherV −

_p p ditherV −

dithN

For c dith zf f f< < :

2

2_

422

dith

Core

Ncp p dither N

s

inf VVf π−

⎛ ⎞≤ ⎜ ⎟⎝ ⎠

(3-2)

And for c z dithf f f< < :

2

2_

422

dith

Core

Ncp p dither N

z s

inf VVf f π−

⎛ ⎞≤ ⎜ ⎟⋅⎝ ⎠

(3-3)

Where sf is the switching frequency, is the bit number of dither, is the bit

number of hardware DPWM, V

dithN CoreN

in is the input voltage, cf is the LC filter cut-off frequency,

38

( )1 2cf LCπ= (3-4)

zf is the ESR zero frequency associated with the output capacitor,

( )1 2z ESRf R Cπ= (3-5)

and the dither waveform with the largest low frequency component is a square wave with

50% duty ratio at frequency dithf

2 dithNdith sf f= (3-6)

Once the amplitude of the dither is known, we can develop a condition on how

many bits of dither, , can be used in a certain system without inducing limit cycles. To

ensure that the dither does not cause steady-state limit cycling, the DPWM should always be an

effective level that completely fits into one ADC quantization bin, taking into account the dither

ripple. With bit dither, the effective DPWM quantization bin size

_p p ditherV −

dithN

dithN

2 2DPWM Core dithN NDPWM in inV V V +∆ = = N (3-7)

Assuming that the smallest dither ripple amplitude is when the DPWM levels are located at

one DPWM bin size (with two boundaries: upper and bottom) from the center of the ADC bin.

Then the tolerable peak-to-peak dither ripple amplitude is bounded by

(_12 p p dither ADC DPWMV V V− ≤ ∆ −∆ ) (3-8)

Where is ADC quantization bin size, ADCV∆

2 2 2ADC DPWM Core dithN N N N NADC in in inV V V V N−∆ +∆ = = = −∆ (3-9)

Where is the difference-bit number between DPWM quantization N∆ DPWMN and ADC

quantization , ADCN

( )DPWM ADC Core dith ADCN N N N N N∆ = − = + − (3-10)

As mentioned in section 2.1.2, it was suggested that making the resolution of the DPWM

one bit larger then that of the ADC adequately satisfies the condition to eliminate

steady-state limit cycling, hence the minimum 1N∆ ≥ . Substituting equation (3-7) and (3-9)

and (3-10) into (3-8),

( )_1 2 1 22

DPWMNNp p dither inV V ∆− ≤ − (3-11)

Combining equation (3-11) with (3-2) and (3-3), we can obtain a bound on (takes the

upper rounded integer value of the product): dithN

For c dith zf f f< < :

39

(2

21 2log 2 12 8 2

Core

DPWM

NNs

dith Nc

fNf

π ∆⎡ ⎤⎛ ⎞⎢≤ ⎜ ⎟⎢ ⎥⎝ ⎠⎣ ⎦

)⎥− (3-12)

And for c z dithf f f< < :

( )2 2

1 2log 2 12 8 2

Core

DPWM

NNs z

dith Nc

f fNf

π ∆⎡ ⎤⎛ ⎞⋅≤ −⎢ ⎥⎜ ⎟

⎝ ⎠⎣ ⎦ (3-13)

C. 3-bit Digital Dither Block

When the digital dither approach is applied to the 11-bit DPWM architecture, the bit

number of dither can be determined using those useful mathematical analysis [A7] mentioned

above part B. The parameters of buck converter are: C =22µF, RESR =10mΩ, L=4.7µH, fs

=2MHz, NDPWM = 11-bit, NCore = 8-bit, 1N∆ = and Vin =3.3V. According to equation (3-4),

(3-5) and (3-6), then ( ) 61 2 0.01565 10cf LCπ= = × and ( ) 61 2 0.90429 10z ESRf R Cπ= = × . The

maximum peak-to-peak voltage ripple produced by dither can be estimate by equation (3-11):

( )_ 2 2 1 2 3.2DPWMNNp p dither inV V ∆− ≤ × − = mV (3-14)

The rang of bit number of dither can be determined by equation (3-6):

for the condition dithN

1.487 11.305dithN< < c dith zf f f< < and 1.487dithN < for the condition

c z dithf f f< < . It should be noted that 1 dithN≤ , thus the dither frequency fits the condition

c dith zf f f< < . Consequently the maximum bit number of dither can be obtained by (3-12):

( ) ( )2 26 8

12 2 6 11

1 2 1 2 10 2log 2 1 log 2 1 4.82342 8 2 2 8 0.01565 10 2

Core

DPWM

NNs

dith Nc

fNf

π π∆⎡ ⎤ ⎡ ⎤⎛ ⎞ ⎛ ⎞×⎢ ⎥≤ − = − =⎢ ⎥⎜ ⎟ ⎜ ⎟×⎢ ⎥ ⎢ ⎥⎝ ⎠⎝ ⎠ ⎣ ⎦⎣ ⎦

(3-15)

which means that the bit number of dither should be limited 4.8234dithN < to satisfy the

tolerant voltage ripple (3.2mV). Thus the bit number of dither can be adapted from 2 to 4 in

this case. Here we use a 3-bit digital dithering pattern in the 11-bit hybrid DPWM.

The operations of the 3-bit dither pattern are already shown in Fig. 3-4 and Table 3-2

respectively. Fig. 3-5 shows the implementation of the 3-bit proposed digital dithering block.

The obtained 8-bit duty D[7:0] will be implemented by the hardware Core DPWM (a 4-bit

counter-comparator and a 4-bit segmented DCM phase-shift block) .

sf 3-bitcounter

from control-lawd[10:0]

23 X 23

look-up

d[2:0]

d[10:3]

1-bitdither 8-bit

saturatedD[7:0]

row index

line index

addertable value

To Core DPWM

Fig. 3-5 The diagram block of proposed 3-bit digital dithering

40

3.1.2 Design of a 4-bit Segmented DCM Phase-Shift Block

Digital Clock Manager (DCM) functionality block is available in most digital FPGA

devices. It includes the general DLL (Delay-Locked Loop) and/or PLL (Phase-Locked Loop)

modules, which can not only produce multi synchronous clocks with zero propagation delay,

but also offer multi asynchronous clocks with low skew phase-shift. Virtex-II FPGA provides

advanced DCM clocking capabilities to optionally multiply and divide the incoming clock

frequency to synthesize a new clock frequency [X2]. DCM shifts the clock phase optionally

to delay the incoming clock by a fraction of the clock period. For instance shown in Fig. 3-6,

the DCM divides the incoming clock FCLK (50% ratio) into four equal clocks clk_0, clk_90,

clk_180 and clk_270 respectively, then the four phase-shifted clocks can act as an equivalent

22×FCLK clock with a 4:1 multiplexer. Thus the clock for the DCM architecture can be reduced

by 22 times for a fixed-resolution DPWM, or the resolution can be increased by 22 bits for a

fixed-frequency DPWM. Since the relationship between system clock FCLK, hardware Core

DPWM resolution NCore and switching frequency fs can be written as:

2 C o reNC L K sF f= ⋅ (3-16)

Then the required clock FDCM for the four-phase-shift DCM module can be expressed as:

( )( 2) 22 2DCM Core DCMN N NDCM CLK sF F − + −= ⋅ = ⋅ f (3-17)

where NDCM is the bit number of DPWM implemented by four-phase-shift DCM module.

DCM

4-phaseshift

f

clk_0

clk_270

clk_90

clk_180 4 f⋅

f_0

f_0

f_90

f_180

f_270

f

f_90f_180f_270

clk_0clk_90clk_180clk_270

equ alent ivequivalent

4·f

Fig. 3-6 DCM four-phase-shift scheme

Based on the advantage of DCM phase-shift module, a segmented DCM phase-shift

architecture which uses two DCM phase-shift modules in series for digital clock application

was introduced in [M3]. This segmented DCM architecture is employed as a 4-bit DPWM

block of high-frequency digital control in our work.

The proposed DPWM including a 4-bit counter comparator, then the hardware clock

frequency FCLK = 24·fs. According to equation (3-17), the incoming clock frequency FDCM for

41

the segmented DCM module, FDCM = FCLK ·2 (4+4-2) = 26· FCLK. The diagram block of the 4-bit

segmented DCM phase-shift architecture is shown in Fig. 3-7, where the input clock FCLK,

propagates in zero delay through the first DCM block, DCM-I in this case, and the first phase

shifted versions, PX0, PX90, PX180 and PX270, are generated. The clock FDCM, four times

incoming clock FCLK, is operated at the second DCM block, DCM-II, and further phase shifted

signals of the clock are produced, PY0, PY90, PY180 and PY270. As observed from Fig. 3-7,

the resolution is now increased by 16 times without the need of operating the whole system at

16 times higher FCLK.

from digital dithering

DCM-I

4-phaseshift

x0

Mux

4:1

D[3:2]PX0

PX90

PX180

PX270

D[1:0]

x90

x180

x270DCM

4x= 4xFCLK

CLKF

FDCM

1x

DCM-II

4-phaseshift

y0

Mux

4:1

PY0

PY90

PY180

PY270

y90

y180

y270

C L KF

D[3:0]

S1

S2

Sc

Fig. 3-7 A diagram block of 4-bit segmented DCM phase-shift

Using two multiplexers to select the corresponding shifted clock signals, the whole block

realizes the 4-bit DPWM duty D[3:0] from digital dithering block. Depending on duty value

D[3:2], S1 can be derived from the one of four phase-shifted clock signals PX0, PX90, PX180

and PX270. The selected S1 acts as an equivalent clock of four times (x4) the phase-shifted

signals. Similarly, duty value D[1:0] selects one of the four phase-shifted clock signals PY0,

PY90, PY180 and PY270 for S2 which acts an equivalent clock of four times (x4) the

phase-shifted signals. Then the two selected signals are operated in logic AND circuit to

generate the final phase-shift signal Sc which has 16 times (double x4) incoming FCLK and will

be sent to counter comparator. The most attractive merit for this segmented DCM phase-shift

architecture is that the final output signal Sc has 24 kinds of clock possibilities during each of

FCLK clock cycle, where S1 has 22 kinds of “coarse” phase-shift and S2 has 22 kinds of “fine”

phase-shift. Thus this segmented DCM block can either increase 4-bit DPWM resolution (for

fixed fs) or increase the switching frequency by 24 times (for fixed NDPWM). The operation

waveforms of the 4-bit segmented DCM phase-shift module are shown in Fig. 3-8.

42

3.1.3 Design of a 4-bit Fast Counter-Comparator Block

Fast counter-comparator is one simple hardware method to achieve digital-to-time

conversion in Core DPWM. This architecture uses a cycling counter and a comparator, setting

a set-reset (SR) latch high when the counter value is zero and low when the counter reaches

the control duty value D. This scheme has the advantage of a simple structure and an excellent

linearity in the digital to time-domain-conversion. According to equation (3-16), it needs 2N·fs

clock to achieve an N-bit DPWM at switching frequency fs. However when operating at the

high frequency fs, it falls into the drawback of very high power consumption. Thus the fast

counter-comparator is usually used as the solution for the implementation of few MSB rather

than a whole DPWM architecture.

Linking to the 3-bit digital dithering and 4-bit segmented DCM phase-shift blocks above; a

4-bit counter-comparator block shown in Fig. 3-9 is adopted in this hybrid DPWM. It

includes a 4-bit counter, a 4-bit comparator and a FDP (D Flip-Flop with Asynchronous

Preset). Where D[7:4] and Sc respectively come from the 3-bit digital dithering block and the

4-bit DCM phase-shift block. An example is employed to explain the operation for the 4-bit

counter-comparator block, where D[7:4]=”1010” and D[3:0]=”1011”, the operation

waveforms are shown in Fig. 3-10. FCLK

4xFCLK

[ ]

00 001 90

3:2 110 18011 270

PXPX

D SPXPX

⎧ ⎧⎪ ⎪⎪ ⎪= ⇒ =⎨ ⎨⎪ ⎪⎪ ⎪⎩ ⎩

[ ]

00 001 90

1:0 210 18011 270

PYPY

D SPYPY

⎧ ⎧⎪ ⎪⎪ ⎪= ⇒ =⎨ ⎨⎪ ⎪⎪ ⎪⎩ ⎩

D[3:2]=00

0 2Sc PX S= =∩

D[3:2]=0190 2Sc PX S= =∩

D[3:2]=10

180 2Sc PX S= =∩

D[3:2]=11

270 2Sc PX S= =∩

Fig. 3-8 Operation waveforms of the 4-bit segmented DCM phase-shift module

43

4-bitcounter

CLKF

PRE

CQ

A

BD[7:4]

PWMA<B?

Set

Rset

Sk

LTD

42 sf= ⋅

Scfrom DCM phase-shift

from digital dithering

FDP

Fig. 3-9 4-bit counter-comparator block linked to digital dithering and segmented DCM

•••

•••

• • •

ScSk

Set

RsetPWM

• • •• • •

• • •

• • •

D[7:4]=1010

1111

0000

• • •

4-bit counter D[3:0]=1011

Fig. 3-10 Operation waveforms of the 4-bit counter comparator block

3.1.4 Operation of the Hybrid Dither DPWM

Taking a combination of three blocks described above: 3-bit digital dithering, 4-bit DCM

phase-shift and 4-bit counter comparator, the completed DPWM can be figured in Fig. 3-11.

adder

sf 3-bitcounter

from control-law

d[10:0]

23 X 23

look-up

d[2:0]

d[10:3]

1-bitdither 8-bit

saturatedD[7:0] 4-bit

counter

CLKF

PRE

CQ

row index

line index A

BD[7:4]

PWMA<B?

Digital dithering Counter-comparator

DCM

4-phaseshift

x0

Mux

4:1S1

D[3:2]PX0

PX90

PX180

PX270

D[1:0]

DCM Phase-Shift4-bit

3-bit 4-bit

addertable value

x90

x180

x270DCM

4x= 4xFCLK

C LKF

FDCM

1x

DCM

4-phaseshift

y0

Mux

4:1

PY0

PY90

PY180

PY270

y90

y180

y270

C L KF

Sc

S2

Set

Rset

Sk

LTD

FDP

Fig. 3-11 The proposed 11-bit hybrid dither DPWM acts as 3-bit digital dither, 4-bit segmented DCM

phase-shift and 4-bit counter comparator in FPGA implementation

The operation procedure of the DPWM is described as follows: The duty value d is

generated by the digital control law in 11-bit and varies from the minimum value

d[00000000000] (0) to the maximum value d[11111111111] (2047), which is sent to DPWM

architecture at beginning of each switching cycle. Initially the 11-bit duty value d goes into

44

digital dithering block, where the 3-LSB d[2:0] acts as the line index and the 3-bit counter

value indicates the row index in the look-up table (shown in Fig. 3-4 and Table. 3-2). Then a

1-bit dither value is acquired and added to duty ratio MSB d[10:3] in an 8-bit saturated adder,

where a new 8-bit duty ratio D[7:0] is generated. For the new duty D, the MSB D[7:4] are

delivered to the 4-bit counter-comparator block and the LSB D[3:0] are assigned for the

4-bit segmented DCM phase-shift block. The selected signals Sc (from segmented DCM

phase-shift block) and Sk (from counter-comparator block) are operated by logic AND circuit,

resulting in another signal Rset. The signals Set and Rset respectively connect to the ports PRE

and C of the FDP logic circuit to change the PWM states ON/OFF. For instance, supposing

that the duty value from the control algorithm is d[01010101010] and the 3-bit counter value

in digital dithering block is “010”. According to Table 3-2, the 1-bit dither value ‘1’ will be

added to d[10:4] by a saturated adder resulting in a new duty D[01010110]. The D[7:4]

(“0101”) is implemented by the 4-bit counter-comparator, D[3:2] (“01”) is used to select

phase-shifted clock PX90 for signal S1, and D[1:0] = ”10” is set to select phase-shifted clock

PY180 for S2. Through the logic AND operation of S1 and S2, the final phase-shifted signal SC

is obtained and sent to FDP to change PWM signal. The logic waveforms for the example

operation are shown in Fig. 3-12.

FCLK

S2S1

Sc

0000 0101…... 1111…...

…...…...…...

…...…...

…...

fs=FCLK /24

Sk

SetRset …...

PWM counter comparator DCM phase-shift

Fig. 3-12 Logic waveforms for the example operation of 11-bit hybrid dither DPWM

In the FPGA implementation, the 11-bit DPWM signal with 2MHz switching frequency is

realized by the proposed hybrid DPWM, where 3-bit are implemented by digital dithering

(Ndith = 3), 4-bit are achieved by segmented DCM phase-shift block (NDCM = 4), and 4-bit are

generated by counter-comparator (NCore = 4). According to equations (3-16) and (3-17)

respectively, the FPGA system clock is FCLK = 24·fs and the clock signal shifted in DCM

module is FDCM = 22· FCLK = 26·fs. When operating at fs = 2MHz the FCLK is merely 32MHz,

which dramatically alleviates the system clock requirement and reduces the power

45

consumption of DPWM. For example, when a 11-bit DPWM operating at 2MHz in the digital

dithering approach [A7] or in the segmented DCM phase-shift [M3], respectively, the FCLK

will be required 28·fs = 512MHz or 27·fs = 256MHz. By contrast, the proposed hybrid dither

DPWM can allow operation at higher switching frequency with lower power consumption.

The implementation of the proposed 11-bit hybrid DPWM is performed on a XC2VP30

FPGA and the simulation is verified in post-placed route using Xilinx ISE9.2 tool. The single

four-phase-shift DCM functionality shown in Fig. 3-6 is verified and the timing-waveform is

shown in Fig. 3-13. The timing-simulation results for the segmented DCM phase-shift shown

in Fig. 3-7 are figured in Fig. 3-14, where fs =2MHz, FDCM = 128MHz, FCLK = 32MHz and the

duty ratio 50% with D[7:0]= “10000000”. Finally the timing-simulation waveforms of the

complete 11-bit hybrid DPWM shown in Fig. 3-11 is illustrated in Fig. 3-15 with an example

duty value D[7:0]= “10000011”. The experimental tests of the hybrid DPWM based on a

discrete buck converter will be detailed in Chapter 6.

Fig. 3-13 DCM four-phase-shift simulation waveforms

Fig. 3-14 4-bit segmented DCM phase-shift timing-simulation waveforms

Except the DCM parts, the blocks of the proposed DPWM are implemented in VHDL. Like

the DLL and PLL functions, the DCM is provided by FPGA manufacturing as an IP Core

(Intellectual-Property Core). Recently large numbers of research have focused on low-jitter

46

low-skew DLL/and PLL design. The technique of designing a similar DLL IP Core in ASIC is

not a critical issue in IC design. This issue is not discussed here.

Fig. 3-15 Timing-simulation waveforms of the 11-bit hybrid dither DPWM

3.2 Design of a 11-bit Hybrid MASH ∆-Σ DPWM

Section 3.1 describes an 11-bit hybrid dither DPWM which can operate up to 2MHz

switching frequency in FPGA-implementation. The most valuable advantage of the DPWM is

that the hybrid architecture can dramatically alleviate the requirement of high clock frequency

and consequently reduce the power consumption. For operation of 11-bit DPWM at 2MHz, it

merely requires a system clock 32MHz (128MHz for DCM block only).

Like the method digital dither, another one practical soft method to increase effective

resolution of DPWM is Delta-Sigma (∆-Σ) modulator, which is based on the well known

noise-shaping technology [R6, Y4, S10, D2]. As an alternative, it is very interesting to employ

a ∆-Σ modulator to increase the resolution and reduce power consumption for DPWM.

3.2.1 MASH ∆-Σ Modulator Design

A. Principle of ∆-Σ modulator

Delta-Sigma (∆-Σ) has been widely used in analog-to-digital and digital-to-analog

conversion. It is based on the well-known noise-shaping concept which can be fabricated in

low-cost CMOS technologies [R6, D2]. Fig. 3-16 shows the general structure of a

signal-quantizer ∆-Σ modulator, where Loop Filter is to process the input signal by

noise-shaping modulator that generally is a delay or integrator block, E is the noises, Q is the

quantizer and V is the output signal. For a first order ∆-Σ, the modulator can be transformed

into a detailed linear model in z-domain as shown in Fig. 3-17.

47

L0

L1

Loop Filter Q

U

Y V

E

Fig. 3-16 General structure of a single stage ∆-Σ modulator

U(z) + + +Z-1

E(z)

-V(z)Y(z)

Z-1

Δ Σ

Fig. 3-17 A z-domain block of first-order ∆-Σ modulator

From the diagram, it can be written:

( ) ( ) ( ) ( )1Y z z Y z U z z V z−= + − 1− (3.18)

Thus

( ) ( ) ( )( ) ( ) ( ) ( ) ( ) ( ) ( ) ( )1 1 1

V z Y z E z

z Y z U z z V z E z U z z Y z V z E z− − −

= +

= + − + = + − +⎡ ⎤⎣ ⎦ (3.19)

Then

( ) ( ) ( ) ( )11V z U z z E z−= + − (3.20)

Equation (3.20) can be rewritten in the digital signal process form

( ) ( ) ( ) ( ) ( )V z STF z U z NTF z E z= ⋅ + ⋅ (3.21)

where STF is the signal transfer function which is unity here, STF(z)=1, and NTF is the noise

transfer function with . In steady-state, when the ∆-Σ loop has infinite gain

at zero frequency, i.e., z ≈ 1 and consequently ||NTF(z)|| << 1, it suppresses the quantization

noise at and near dc component. Therefore the ∆-Σ modulator can dramatically eliminate the

quantization noise and then the input signal can be well remained,

1( ) (1 )NTF z z−= −

( ) ( )V z U z→ (3.22)

Similarly a second-order ∆-Σ modulator can be transformed to a detailed linear model in

z-domain shown in Fig. 3-18.

U(z) + + +Z-1

E(z)

-V(z)Y(z)

Z-1

+Z-1

- +

Fig. 3-18 A z-domain block of second-order ∆-Σ modulator

48

From the schema, the output signal V(z) can be written: 1 1

1 1

( ) ( ) ( )( ) ( )(1 ) (1 )z V z z V z U zV z E z

z z

− −

− −

− − += + +

− − 2 (3.23)

Through simplification

( ) ( ) ( ) ( )211V z U z z E z−= + + ⋅ (3.24)

Rewritten in the digital signal process form of (3.21), here 1STF = and . ( )211NTF z−= −

B. ∆-Σ Modulator Application in DPWM

For the DPWM application in ∆-Σ digital signal process, the loop architecture function is

similar to that of the noise-shaping loop in application of analog-to-digital and digital-to-

analog, namely to reduce the resolution of the large-bit input signal to a few-bit value without

significant quantization error-bit in the process. An architecture configuration for ∆-Σ DPWM

is illustrated in Fig. 3-19 (a), where the discarded LSBs (error e(n)) are filtered and fed-back

to the input port. The filter He generally is a delay or integrator block. To simplify the DPWM

schematic diagram, the process “Limit” and “Truncate” can be incorporated as a “Truncation”

block shown in Fig. 3-19 (b).

TruncatureU(z) V(z)

+

+-e-

E(z)

LSB(LSB+MSB)

MSBY(z)Truncation

U(z) V(z)+

E(z)MSBY(z)

Limiter

MSB-

+ LSB

HeHe

(a) (b)

Δ

Σ

Fig. 3-19 Error feedback filter ∆-Σ modulator for DPWM (a) and its simplified block (b)

From Fig. 3-19, the transfer function in the linear model is given by

( ) ( ) ( )V z Y z E z= + (3.25)

where E(z) is the quantization error of truncation, and Y (z) can be expressed as:

( ) ( ) ( ) ( ) ( ) ( )Y z U z He z E z He z V z= + ⋅ − ⋅ (3.26)

Thus equation (3.25) can be rewritten:

1 ( ) ( )

( ) ( ) ( ) ( ) ( ) ( ) ( )

( )= He z E z

V z U z He z Y z He z V z E z

U z ⎡ ⎤−⎣ ⎦

= + ⋅ − ⋅ +

+ ⋅ (3.27)

Assuming that the filter He is a delay, z-1, equation (3.27) is identical to (3.20), which

demonstrates that the ∆-Σ modulator can be applied in DPWM as well as in ADC and DAC.

From the equation (3.27), it can be seen that 1STF = , and in digital

signal process. This equation shows how the transfer function NTF influences the truncated

( )1NTF He z= −

49

signal. When the loop filter has infinite gain (||He|| ≈ 1) at zero frequency, the noise can be

eliminated dramatically (||NTF(z)|| << 1). Therefore the high-resolution PWM input signal is

almost unchanged, the quantization error is suppressed, and consequently the output PWM

signal becomes approximately equal to the input PWM signal.

Although the ∆-Σ noise-shaping modulator is not new in IC design for ADC, it has not yet

been widely used in recent booming digital PWM control. As far as the relevant literature,

two ∆-Σ DPWM modulators have been proposed in digitally controlled high-frequency

low-power SMPS by Z.Lukic et al. The first ∆-Σ DPWM was proposed in 2005 [Z2], where a

first-order ∆-Σ DPWM was adopted (shown in Fig. 3-20 (a)). The other was proposed in 2007

[Z1], where a second-order ∆-Σ DPWM was presented (shown in Fig. 3-20 (b)).

Truncation Core DPWM

yLSB

MSB

m2 LSBs

c(t)

Z-1

-Z-1 2

y

Truncation Core DPWM

yLSB

MSB

LSB

c(t)V(z)U(z)Y(z)

E(z)

Z-1

+U(z) V(z)

+

E(z)

(a) (b)

Fig. 3-20 A first-order ∆-Σ DPWM (a) and a second-order ∆-Σ DPWM (b)

Although the low-order ∆-Σ DPWM has the advantages of simplicity, robustness, stability

and ease for realization, the noise-shaping performance of this DPWM is still limited such as

it has the potential problems of low-frequency tones and slow convergence [Z1, R6, S10]. By

contrast, the high-order ∆-Σ architecture has higher noise-shaping performance such that can

strongly suppress low-frequency tones and have faster convergence [R6, D2]. However as a

contradictory term with noise-shaping performance, the stability must be considered in the

design for high-order error-feedback loop.

As illustrated in equation (3-20) and described in previous part A, since STF acts essentially

like a pre-filter, the stable input range of a ∆-Σ modulator is primarily determined by NTF and

the bit number of the quantizer. However due to absence of standard criterion for NTF

properties that are necessary and sufficient for stable operation, it is difficult to exactly

analyze the stability of a high-order ∆-Σ modulator [D2]. Especially it has no solid theoretical

foundations to estimate the stability of a multi-bit-signal DPWM. Evidently high-order ∆-Σ

may cause the potential instability problem, however it is hard to evaluate the performance of

stability and it needs to be conformed by extensive simulation and experimental results [R6].

50

C. Proposed MASH Second-Order DPWM

A different structure which eases the stability problem in high-order ∆-Σ is the cascade

modulator, also called the Multi-stAage-noise-SHaping (MASH) modulator [R6, D2]. The

basic concept of the MASH (two-stage) ∆-Σ is illustrated in Fig. 3-21.

L0

L1

Loop Filter Q

U(z)Y1(z) V1(z)

E1(z)

L0

L1

Loop Filter Q

E2(z)

+

H1

H2

&

V2(z)

V(z)

Y2(z)-e1

-e2

-

First Stage

Second Stage

-

Fig. 3-21 A cascade structure of the two-stage MASH ∆-Σ modulator

Where Loop Filter is noise-shaping modulator that generally is a delay or integrator block, E

is the noises of quantizer, Q is the quantizer and V is the output signal. The output signal of

the first-stage is given by:

(3.28) 1 1 1 1( ) ( ) ( ) ( ) ( )V z STF z U z NTF z E z= ⋅ + ⋅

where STF1 and NTF1 are the signal transfer function and the noise transfer function of the

first-stage loop respectively. The output signal of the second-stage is given by

2 2 1 2( ) ( ) ( ) ( ) ( )V z STF z E z NTF z E z= ⋅ + ⋅ 2 (3.29)

where STF2 and NTF2 are the signal transfer function and the noise transfer function of the

second-stage loop respectively. The digital filter stages H1 and H2 at the outputs of the two

loops are designed such that in the overall output V(z) of the system, the first-stage error E1(z)

is cancelled by setting [R6]:

1 2 210H NTF H STF⋅ ⋅− = (3.30)

Usually the choice for H1 and H2 which satisfies the above equation is H1 = k·STF2 and H2 =

k·NTF1 , where k is a constant chosen to give unity signal gain and STF2 is often a delay z-1.

For easy discussion in this case, let k =1 and the overall output is then given by

1 1 2 2 2 1 1 2 2( ) ( ) ( ) ( ) ( )z H V z H V z STF STF U z NTF NTF E zV ⋅ ⋅ ⋅ ⋅ ⋅ ⋅− = −= (3.31)

In practical implementation, both stages of the MASH ∆-Σ may contain a first-order or a

second-order loop.

51

Compared with the single-stage ∆-Σ modulator such as first-order [Z2], [A11], and

second-order one [Z1], the MASH structure shown in Fig. 3-21 has the advantages that makes it

possible to use low-distortion loop filter in all stages to obtain the first-stage error e1(n) without

any subtraction, for entering it into the second stage with low-distortion. Besides the remaining

error in the output V(z) is the shaped quantization error e2(n) of the second-stage, operating

with an input e1(n) which is itself noise-like, hence the second-stage quantization error e2(n) is

very similar to a true white noise [R6]. In addition the MASH structure is very helpful for the

use of a multi-bit quantizer in the second-stage, without any correction of the nonlinearity [D2].

For example both stages are first-order loops, then:

1 2 1STF STF= = and 11 2 1NTF NTF z−= = − (3.32)

and the output is

( ) ( ) ( ) ( )2121V z U z z E z−= − − ⋅ (3.33)

This is identical to a single second-order ∆-Σ modulator stated in equation (3-24).

Thus this MASH ∆-Σ modulator has the noise-shaping performance of a second-order

loop, while preserving the robust stability properties of first-order loops. Similarly for the

second-order loops in both stages, then

1 2 1STF STF= = and (3.34) 1 21 2 (1 )NTF NTF z−= = −

and the output is

( ) ( ) ( )4121V z U z z E−= − − ⋅ (3.35)

Thus this MASH ∆-Σ modulator has the noise-shaping performance of a fourth-order loop,

while preserving the robust stability properties of second-order loops.

Based on the useful MASH ∆-Σ modulator, a two-stage ∆-Σ DPWM with 11-bit resolution

is proposed here. The proposed MASH ∆-Σ DPWM is shown in Fig. 3-22 where both stages

contain a first-order loop, resulting in a global second-order noise-shaping performance, while

preserving the robust stability properties of first-order loops. In the 11-bit MASH ∆-Σ

DPWM, ,1 2 1STF STF= = ( )11 2 1NTF NTF z−= = − , 1 2 2, H STF H NTF1= = , and the output

( ) ( ) ( ) ( ) ( ) ( )211 1 2 2 21V z H V z H V z U z z E z−= ⋅ − ⋅ = − − ⋅ , which is identical to equation (3.33).

The 11-bit DPWM duty value from control algorithm is sent to the first-stage loop, and then

4-MSB for output and 7-LSB for error-feedback e1. After the second-stage loop, the 2-MSB is

delivered for output and 5-LSB for error-feedback e2. Finally the 6-bit combination signals

(4-MSB and 2-MSB) are sent to the hardware Core DPWM.

52

+ 1

H1

H2Z-1

++-

&++U(z)

7 LSB

c(t)d[10:0]

Z-1

++

+Z-1

-e2

-e1

E1

E2

4 MSB

5 LSB

2 MSB

HardwareDPWM

D[5:0]Truncation

Truncation 2-bit

-

Fig. 3-22 The proposed DPWM based on two-stage ∆-Σ modulator

3.2.2 Operation of the Hybrid ∆-Σ DPWM Scheme

The 6-bit hardware Core DPWM is implemented by a 4-bit segmented DCM phase-shift

block and a 2-bit counter-comparator which have been previously introduced in section 3.1.2

and section 3.1.3 respectively. Taking a combination of three blocks described above: MASH

∆-Σ modulator, 4-bit segmented DCM phase-shift block and 2-bit counter-comparator, the

completed 11-bit hybrid ∆-Σ DPWM architecture can be figured in Fig. 3-23.

2-bitcounter

CLKF

PRE

CQ

A

BD[5:4]PWM

A<B?

Counter-comparator

DCM

4-phaseshift

x0

Mux

4:1S1

D[3:2]PX0

PX90

PX180

PX270

D[1:0]

DCM Phase-Shift4-bit

2-bit

x90

x180

x270DCM

4x= 4xFCLK

CLKF

FDCM

1x

DCM

4-phaseshift

y0

Mux

4:1

PY0

PY90

PY180

PY270

y90

y180

y270

C L KF

Sc

S2

Set

RsetSk

LTD

FDP

11-bit truncation4-bit MSB

Q

7-bit 7-bit LSB

truncation5-bit

5-bit LSB 2-bit

Adderab

clkD a

clk

Adderb

out

outclk

QD

clk

(a+b)

(a+b)

truncation3-bit

a

clk

Adder

b out(a+b)

2-bit MSB

QD

clk

5-bit MASH ∆—Σ Modulator

& D[5:0]=22·fs

=22·fs

Fig. 3-23 The proposed 11-bit hybrid ∆-Σ DPWM acts as 5-bit MASH ∆-Σ modulator, 4-bit segmented DCM phase-shift and 2-bit counter comparator in FPGA implementation

Similar to the operation of hybrid dither DPWM, the operation procedure of the hybrid ∆-Σ

DPWM can be described as follows: The duty value d is generated by the digital control law in

11-bit and varies from the minimum value d[00000000000] (0) to the maximum value

d[11111111111] (2047), which is sent to the hybrid ∆-Σ DPWM architecture at beginning of

each switching cycle. Initially, the 11-bit duty value d goes into the MASH ∆-Σ modulator,

where a new 6-bit duty value D[5:0] is generated. For the new duty ratio D, the MSB D[5:4]

are delivered to the 2-bit counter-comparator block , and the LSB D[3:0] are assigned for the

4- bit segmented DCM phase-shift block. The selected signals Sc (from segmented DCM

53

phase-shift block) and Sk (from counter-comparator block) are operated by logic AND circuit,

resulting in another signal Rset. The signals Set and Rset respectively connect to the ports PRE

and C of the FDP logic circuit to change the PWM states ON/OFF. For instance, supposing the

n-cycle duty value from the control algorithm is ( ) "10010101010"d n b= , feedback value

and in the MASH ∆-Σ modulator, then the new

duty is generated. 1( 1) "0101010"e n b− = 2 ( 1) "01010"e n b− =

( ) "100101"D n b= [ ]5 : 4 "10"D = b is implemented as the 2-bit counter

comparator, [ ]3: 2 "01"D = b is used to select phase-shifted clock PX90 for S1, and

[ ]1: 0 "10"D = b is set to select phase-shifted clock PY180 for S2. Through the logic AND

operation of S1 and S2, the final phase-shifted signal SC is obtained and sent to FDP to change

PWM signal. The logic waveforms for the example operation are shown in Fig.3-24.

FCLK

S2S1

Sc

00 01 10

fs= FCLK /22

Sk

Set

Rset

PWM counter comparator DCM phase-shift

11

Fig. 3-24 Logic waveforms for the example operation of 11-bit hybrid ∆-Σ DPWM

In the FPGA implementation, the 11-bit digital PWM signal with 4MHz switching

frequency is realized by the hybrid ∆-Σ DPWM architecture. Among the 11-bit DPWM, 5-bit

are implemented as MASH ∆-Σ modulator (N∆-Σ = 5), 4-bit are achieved by segmented DCM

phase-shift block (NDCM = 4), and 2-bit are generated by counter-comparator (NCore = 2).

According to equations (3-16) and (3-17) respectively, the FPGA system clock is FCLK = 22·fs

and the clock signal shifted in DCM module is FDCM = 22· FCLK = 24·fs. When operating at fs =

4MHz the FCLK is merely 16MHz, which dramatically alleviates the clock requirement and can

allow operation with low power consumption. For an example duty value of D[5:0]=

"100011"b in FPGA implementation, the timing-simulation waveforms of the 4-bit segmented

DCM phase-shift is shown in Fig. 3-25, and the waveforms of the complete 11-bit hybrid ∆-Σ

DPWM is shown in Fig. 3-26. The experimental tests of the hybrid ∆-Σ DPWM based on a

discrete buck converter will be detailed in Chapter 6.

54

Fig. 3-25 Timing-simulation waveforms of the 4-bit segmented DCM phase-shift

Fig. 3-26 Timing-simulation waveforms of the 11-bit hybrid ∆-Σ DPWM

3.3 Summary

To improve the output voltage precision, the resolution of the ADC and DPWM is expected

to the higher the better. Based on the hardware Core DPWM, the effective resolution of the

DPWM architecture can be boosted with soft methods as digital dither and delta-sigma,

allowing for high-frequency, low-power and small-area implementations. A summarization for

the two types of hybrid DPWM is given by Table 3-5.

The hybrid dither DPWM includes the digital dithering approach and the hardware Core

DPWM. The bit number of dither can be determined according to useful analysis in

part B of section 3.1.1. However dither is not coming free. The more bits of dither, the more

additional ripple will occur. Whatever the soft method dither is valuable to increase the

effective DPWM resolution to support operation at higher frequency than 1MHz with 11-bit

effective resolution, which is impractical for most of pure hardware DPWM.

dithN

The hybrid ∆-Σ DPWM uses the noise-shaping technique to increase DPWM resolution

55

while consuming less power and area in higher frequency range. Although ∆-Σ architecture

has been used for years in the design of ADC and DAC that can be implemented with low

cost CMOS technologies, it is still rarely applied to the DPWM design in digital controller for

high-frequency low-power SMPS. There are several reasons accommodating this. Firstly

there is lack of understanding in the design of ∆-Σ DPWM principle by power-supply

engineers. No systematic procedure is available for the design of ∆-Σ DPWM. Secondly there

are seldom discussions regarding the usefulness and advantages of ∆-Σ DPWM in theoretical,

not to mention the practical implementation proven. Thirdly due to absence of standard

criterion for NTF properties that are necessary and sufficient for stable operation, it is difficult

to exactly estimate the stability of a high-order ∆-Σ modulator. If we have standard criterions

to solve this stability problem of a high-order ∆-Σ as well as the guarantee minimum-ripple

digital dither, the ∆-Σ modulator will be a huge potential in DPWM application for digitally

controlled SMPS.

As alternative methods, the two proposed Hybrid DPWMs evidently offer higher-frequency

and higher-resolution operation. However it does not have enough proof to evaluate their

performance and prove which one is better. When DPWM applied to practical implementation,

the consideration of hardware resources, power consumption and output voltage accuracy, etc

should be carefully taken into account.

This chapter discussed the digital PWM implementation of a switching converter, and

presents two kinds of high resolution hybrid DPWM design. The next chapter will detail the

design of digital control law as classical PID and robust RST controllers.

Table 3-5 Summarization of two kinds of hybrid DPWM

symbol Definition Hybrid dither DPWM Hybrid ∆-Σ DPWM

DPWMN Bit number of DPWM effective resolution 11-bit d[10:0] 11-bit d[10:0]

CoreN Bit number of counter-comparator 4-bit d[10:7] 2-bit d[10:9]

phase shiftN − Bit number of segmented DCM 4-bit d[6:3] 4-bit d[8:5]

softN Bit number of soft method (dither or ∆-Σ) 3-bit d[2:0] ( )dithN 5-bit d[4:0] ( )N∆−Σ

sf Operation switching frequency in FPGA Up to 2MHz Up to 4MHz

CLKf System clock for hardware Core DPWM 2 CoreNsf⋅ = 32MHz 2 CoreN

sf⋅ =16MHz

DCMf Phase-shift clock inside DCM block only 22 CoreNsf

+ ⋅ =128MHz 22 CoreNsf

+ ⋅ =64MHz

56

57

Chapter 4 Design of a Digital Tri-mode Controller

As described in section 2.4, digital control is not new in the field of Power Electronics. It is

often associated with DSP or other micro-processors. Generally the digital control system

presents sufficient resources to accommodate the modest switching frequency of the converter

in the range of kHz. However in low-level battery-powered applications, switching

frequencies in the range of MHz and plus are necessary to reduce the size of passive

components, which challenges the feasible DSP-implementation. Thus for the considerations

of computation speed and power consumption, the dedicated digital controllers used in high-

frequency low-power SMPS are supposed to implement in the FPGA/ or ASIC with the

capability of high-speed computation and low-power consumption.

One issue of the monolithic integrated digital controller design is to meet the high-speed

real-time control with high-performance, while consuming low power with small area.

Sophisticated control strategies can possess better dynamic performances, but the power

consumption cost is increasing with added performances. Thus for the high-power converter,

the power consumption of its digital controller is not so critical when it is compared with the

system overall output power. However in low-power SMPS, the power consumption of the

digital controller may become intolerable and can not be neglected. Besides with the

switching frequency increasing, the algorithm computation will consume more and more

energy. Furthermore at a certain constant switching frequency, the power consumption

depends on the algorithm complexity, such as the step number of computation and area

(multipliers and adders etc.). Thus the challenge of digital controller design is to reduce power

consumption while keeping high-dynamic performance.

Due to the cost/complexity constraints existing in low-power SMPS with integrated digital

controller, most existing digital controller for high-frequency low-power SMPS with ASIC

standard implementation [A1, A3, A7, B1, J2, J3, T2, Z1, Z2] are designed using PID. The

dynamic performances of these controllers with respect to load variations are still limited. In

order to satisfy the constraints on the load variation to achieve high transient performances

and accuracy, the auto-tuning process of the digital PID controller are proposed [W1].

Unfortunately on-line tuning solutions increase algorithm complexity and thus the silicon area

of the IC controller and power consumption as well. The practical implementation in high

frequency (>1MHz) and very low power (<1W) is still questionable.

58

In this chapter an off-line tuning RST controller is presented [X1]. The so-called RST

robust controller offers better performances and rejection of disturbance when it is compared

to a PID controller. Based on the pole-placement method combined with the sensitivity

function shaping, this chapter investigates an off-line automated approach using fuzzy logic

and genetic algorithm to correctly specify the desired performances by adjusting the

sensitivity functions in the frequency domain where it is necessary.

The robust RST controller has better performance than that of PID but pays at cost of a

structure with more multipliers, which probably results in larger area in future ASIC

implementation. In order to minimize power consumption and offer fast dynamic response, a

Tri-mode controller including transient-state, steady-state and stand-by three modes is

proposed. The robust RST control which gives access to high dynamic performances is

adopted in transient state. In steady-state a PID control law is applied to maintain the output

stable, and in stand-by the controller is clocked at a frequency lower than the converter

switching frequency.

4.1 Sensitivity Functions for Robust Control

The closed-loop system operates in presence of disturbances and it is important to assess

the effects of these disturbances upon the plant output and input. In order to quantify system

dynamics, robustness and noise rejection properties of tested controllers, the sensitivity

functions are introduced [C4]. These sensitivity functions play a critical role in the design of

the controller. These functions (or some of them) will be “shaped’’ for the rejection of the

disturbances and the stability of the closed-loop system [I4].

4.1.1 Sensitivity Functions for SMPS

For DC-DC switching converter, three types of disturbances will be considered in the

modelling: the output disturbance yW (e.g. load variation), measurement noise bW (e.g. A/D

converter noise) and control noise uW (e.g. PWM noise). Fig. 4-1 represents the model of a

SMPS (P) and its controller (K) with the three disturbances.

From Fig. 4-1, it can be established the following relation that leads to the sensitivity

functions. The SMPS output voltage of SMPS is given by

ref yy y yb b yu uy V S W S W S W (4.1)

59

(DPWM)

Wu

(Load variation)

Wy

-

+x

x

x x++

++

(A/D converter)

Wb+

+

refVK P y

Controller Plant

Fig. 4-1 Block diagram of a typical SMPS with disturbances

where is the closed-loop transfer function, let the open-loop transfer function yyL K P ,

1 1

yy

yy

LK P

K P L (4.2)

yyS , ybS and yuS are respectively the output-to-output, measure-to-output and control-to

output sensitivity function. The output-to-output sensitivity yyS between the load variation

disturbance yW and plant output y is given by

1 1

1 1yy

yy

SK P L

(4.3)

The measure-to-output sensitivity ybS between the disturbance measurement noise bW and

plant output y is given by

1 1

yy

yb

yy

LK PS

K P L (4.4)

The control-to-output sensitivity yuS between the disturbance PWM noise uW and plant output

y is given by

1 1

yu

yy

P PS

K P L (4.5)

Constraints or disturbance rejections are naturally expressed in terms of frequency

sensitivity shapes. For a given controller, the sensitivity functions allow to evaluate the

controller behavior in relation to the desired attenuation constraints.

Fig. 4-2 is an example of the gain plot of sensitivity functions for a buck converter. PWM

and output noise attenuations are pointed considering a 1MHz PWM frequency and a 13kHz

(output filter frequency LCf ) output disturbance resonance. yyS at low frequency determines

the steady-state properties of the system. The bandwidth of ybS defines the influence of

measurement noise on the output voltage and the closed-loop bandwidth since it has the same

transfer function as expect for the sign. The gain of yuS verifies the rejection of control

perturbations such as the PWM-related noises.

60

100

101

102

103

-90

-80

-70

-60

-50

-40

-30

-20

-10

0

10

fs [KHz]

S [

dB

]

Syy

output

disturbance

rejection

attenuation of

steady-state

Syb

Syu

PWM

noise

attenuation

Band

widthModulus

margin

Fig. 4-2 Example of sensitivity functions for a buck converter

4.1.2 Robust Modulus and Delay Margins

Among these sensitivity functions, the output-to-output sensitivity function yyS is the key

indicator for the nominal and robust performance as well as for the robust stability of the

closed-loop system. The inverse of the maximum value of the output sensitivity function yyS ,

i.e., the inverse of its H norm, gives the minimum distance between the Nyquist plot of the

open-loop system and the critical point (-1, j0) (see Appendix A). This quantity, called the

modulus margin M , is a significant robustness indicator as compared to the phase and gain

margins. Moreover conditions for ensuring a certain delay margin which is also a very

important robustness indicator, particularly in the high frequency region, can also be

expressed in terms of the shape of the output sensitivity function.

The modulus margin M corresponds to the tolerance related to the model mismatch in the

high frequency range, and the delay margin gives the maximum delay which can be

neglected. The briefly review of the definition of modulus margin M and delay margin

are described in Appendix A. In order to ensure robustness, generally the modulus margin

M is kept higher than 0.5 and the delay margin must be higher than the switching

period sT [I2, I4], i.e.

0.5

1s

M

T (4.6)

4.2 Design of PID and Robust RST Controllers

Based on the useful state-space averaging model, the transfer functions of a switched buck

converter can be developed using small signal analysis [D3]. Considering the Current

61

Continuous Condition (CCM) mode, the transfer function of the buck converter can be written

in continuous-time s-domain (see Appendix B and C):

2

ˆ ( 1)

ˆ (1 ) ( ) 1

out C in

C L C L C L

V s sR C VP s

s R R LC s R C R C R R C R L R R Rd s (4.7)

Transfer equation (4.7) into discrete-time z-domain, the buck converter can be regarded as a

second-order system [R2]:

1 2

2

1 2

b z bP z

z a z a (4.8)

4.2.1 PID Control Design

As mentioned in section 2.4.1, the PID controller is the most common type of digital

control used in digitally-controlled high-frequency and low-power integrated SMPS. Here a

discrete-time PID controller is designed for comparison purpose with RST controller.

The discrete-time filtered PID controller can be written as [X1]:

2 1 202

0 00 1 2

1 11 1PID

r rr z z

r rr z r z rK z

z z s z z s (4.9)

where 0r , 1r , 2r and 1s are the controller parameters to be determined by the pole placement

method.

The digital control system including the PID controller PIDK z and a buck converter

P z is shown in Fig. 4-3.

-

+xrefV

P(z)

PID controller Buck converter

PIDK z outVe z d z

Fig. 4-3 Block diagram of PID-controlled buck converter

Where refV is the reference voltage, outV is the output voltage, e is the voltage error, and d is

the PWM duty ratio. The closed-loop transfer function is:

1

out PID

ref PID

V z K z P z

V z K z P z (4.10)

Setting 1 0 1r r a and 2 0 2r r a to cancel the poles of P z with the zeros of PIDK z , then

0 1 0 2 0 1 0 2

2 2

1 0 1 0 2 1 1 21

r b z r b r b z r b

z s r b z r b s z p z p (4.11)

62

where 1p and 2p are to be determined by the desired closed-loop dynamics which correspond

to the second-order dynamics with a pulsation cr and a damping ratio cr (in s-domain

2

2 22

cr

cr cr crs s). Finally the parameters are determined as

0 1 2 1 2

1 1 0

2 2 0

1 0 2 2

1r p p b b

r a r

r a r

s r b p

(4.12)

The buck circuit elements are 4.7L µH , 22C µF , 5R , 3.0inV V , 1.5outV V and

sampling frequency is set to switching frequency 4sf MHz . Thus the parameters of discrete-

time transfer function for buck converter in equation (4.8) can be obtained:

1 2 1 21.9891, 0.9895, 0.0034, 0.0021a a b b (4.13)

and the open-loop pulsation can be calculated 0 98342rd/s . Considering the trade-off

between the dynamic behavior and robustness (modulus and delay margins), cr is set to 16

times the open-loop pulsation 0 corresponding to 1538500 /rd s . It can be noted that this

pulsation is 15 times smaller than the Nyquist-Shannon sampling frequency (4MHz). With the

closed-loop damping ratio 0.7cr , the parameters 1p and 2p of discrete-time equation (4.11)

can be calculated:

1 21.4293, 0.5586p p (4.14)

Substituting equation (4.13) and (4.14) into (4.12), then the parameters of PID controller can

be acquired:

0 1 2 1141.5872, 281.6306, 140.1043, 0.7959r r r s (4.15)

From equation (4.9) and Fig. 4-3, we can get the digital PID controller:

2

0 1 2

1

1

PID

d z r z r z rK z

e z z z s (4.16)

Substituting equation (4.15) into (4.16), the PID controller is detailed as follows:

0 1 1 2 2 1 1 1 2

1 2 1 2

1

141.5872 281.6360 140.1043 1.7959 0.7959

d k r e k re k r e k s d k s d k

e k e k e k d k d k (4.17)

where d k is the discrete value of PID output (duty ratio), e k is the discrete value of the

error signal between refV and outV , id k and

ie k are the values in i cycles before the

current k cycle respectively. The determination of the fraction precision of the PID

parameters will be discussed latter in section 4.2.3 (Matlab simulation).

63

The corresponding sensitivity functions yyS , ybS and yuS of PID controlled system are

presented respectively in Fig. 4-4. For an output disturbance with a pulsation of 0 (LC filter

resonance), the gain of yyS on 0 gives the information on the disturbance rejection. In the

studied case 0 2 15kHz . It can be seen that 0yyS is about -28dB. Concerning the

stability robustness, the modulus margin PIDM , phase margin PID and delay margin

PID respectively are: 0.83PIDM , 62PID , 2.5PID sT . Due to the sampling

effect, sensitivity functions are plotted until the Nyquist frequency.

100

101

102

103

104

-60

-50

-40

-30

-20

-10

0

10

fs[KHz]

S [

dB

]

Syy

Syb

Syu

Syy

(w0)

Fig. 4-4 Sensitivity functions for the PID-controlled system

4.2.2 Robust RST Control Design

Compared to the PID control, RST allows taking different dynamics for the reference

tracking and the rejection of disturbance rejection [I1, I3]. A RST controller is considered

here in order to obtain a better output disturbance rejection while keeping a good robustness.

The structure of a RST-controlled buck converter system is presented in Fig. 4-5.

-

+x x

++Vref

T(z)

R(z)

1/S(z)

(Load variation)

Wy

x

x

++

+

+

P

Plant

(DPWM)

Wu

(A/D noise)

WbRST control

d ze zm

m

B z

A z

y z

Fig. 4-5 Digital RST-controlled buck converter system

where ( )R z , ( )S z and ( )T z are the polynomials of the digital RST controller, ( )P z is the

discrete-time model of the buck converter, yW , bW and uW are respectively the disturbances

of output-to-output (load variation), measure-to-output (A/D sampling noise) and control-to

64

output (PWM signal noise) and ( ) ( )m mB z A z is a reference model which determines the

reference tracking dynamics. The reference tracking model is generally designed as a second-

order transfer function so that the reference dynamics may be slower than the disturbance

rejection in order to avoid control saturation. This tracking model not discussed here, and the

design attention is mainly paid to the issue of attenuation for the rejection of load variation.

If the discrete-time buck model ( )P z is described in form of the transfer

function P z B z A z , where B(z) and A(z) are polynomials, then the sensitivity

functions can be expressed as:

( ) ( )

( ) ( ) ( ) ( )

( ) ( )

( ) ( ) ( ) ( )

( ) ( )

( ) ( ) ( ) ( )

yy

yb

yu

A z S zS

A z S z B z R z

B z R zS

A z S z B z R z

B z S zS

A z S z B z R z

(4.18)

From these expressions, it can be noted that the three sensitivity functions have the same

denominator ( ) ( ) ( ) ( ) ( )D z A z S z B z R z which determines the closed-loop poles and can be

distinguished to the dominant and auxiliary closed-loop poles.

The knowledge of disturbances leads to design the RST controller in terms of pole and zero

assignments. Some fixed parts can be specified for the polynomials ( )S z and ( )R z . For

example to insure the output accuracy, a pole for 1z (integral part) in S(z) is necessary for

static error elimination. The closed-loop poles are chosen either for filtering effects in certain

frequency regions or for improving the robustness of the closed-loop system. For an output

disturbance at pulsation 1 , the lower the gain of yyS the better the attenuation of the output

disturbance rejection. However it can be shown that the larger the attenuation of yyS at 1 ,

the larger the area of yyS over the zero value [I1, I2, I3, I3, I4]. It can induce an increase in

the maximum value of yyS . As the maximum value of yyS is inversely proportional to M , a

larger output noise rejection leads consequently to a worse robustness. More details can be

found on [I1].

How to determine a controller which offers a trade-off between the robustness and a good

rejection of disturbances? This can be described as an optimization problem by defining a cost

function which qualifies the controller robustness and noise rejection properties.

65

Fuzzy logic is suitable to qualify the robustness of a controller and noise rejection

properties [C2]. Indeed the frontier between a good controller and a bad controller is not strict.

For example if one considers the modulus margin is correct if it is higher than 0.5, it is clear

that a controller will not be qualified with a bad robustness getting to good by crossing this

value. With membership functions of fuzzy logic, the controller quality can be evaluated

continually from bad to good across medium.

An example of membership functions qualifying the gain at 1 ( 1G ) and the modulus

margin ( M ) is shown in Fig. 4-6 and Fig. 4-7 respectively. 1G is normalized over -10 0

and M uses its natural scale. The output membership function is given in Fig. 4-8. The

stability robustness can be expressed by fuzzy rules as defined in Table. 4-1. After the

“disfuzzyfication”, the robustness analysis is quantified by the function

1 1,V f G M which corresponds to a surface as presented in Fig. 4-9. It can be seen that

for 0.5M , the lower the values of 1G the better the output function 1V .

In the same way other membership functions and fuzzy rules related to the delay margin

( ) and other sensitivity functions can be defined to quantify constraints of robustness and

satisfy the requirements of disturbance rejection performances. A weighted sum of all fuzzy

functions defines the quality function to maximize.

-10 -8 -6 -4 -2 0Mem

bers

hip

fu

ncti

on

of

Gw

1

Good Medium Bad

0

0.5

1

Gw1

0 0.2 0.4 0.6 0.8 1Mem

bers

hip

functi

on o

f ∆

M

GoodBad

0

0.5

1

∆M

Fig. 4-6 Input membership function for 1G Fig. 4-7 Input membership function for ∆M

0 2 4 6 8 10

Mem

bers

hip

fu

ncti

on

of

V1

GoodMediumBad

0

0.5

1

V1

12 14

Table 4-1Fuzzy Rules

GoodMediumBad

Bad

Good

∆M

Gw1

Bad

Bad

Bad

Medium

Medium

Good

Fig. 4-8 Output membership functions

66

The optimization problem is addressed by a genetic algorithm which is a stochastic

approach based on the mechanism of natural selection. Each variable iX ( chromosome ) are

coded on in bits between a minimum value, mini, and a maximum value maxi. An initial

population of strings ( individual ) is arbitrarily created. Genetic algorithm makes it change by

using three main operations: reproduction, crossover and mutation in order to maximize an

objective function ( fitness value ) [D4]. The performed computation time can be important

but it is offline, so this is not a limitation for real-time implementation.

The offline approach used to determine the controller parameters is summarized in Fig. 4-

10. This optimization problem is solved in the Matlab/ Similink environment.

Fig. 4-9 Fuzzy function V1

Initial parameter setting

Computing sensitivity functions

Computing module margins

Output disturbance rejections...

Evaluating control performances

(fuzzy logic)

Generating new parameter sets

(genetic algorithm)

Terminnation

Criteria satisfied ?

Optimal parameter set

No

Yes

Fig. 4-10 Off-line approach used to determine the controller parameters

67

For the same buck converter as described previously in section 4.2.1, the denominator of

the sensitivity function yyS is chosen as follows to determine a RST controller which presents

a good robustness and a good attenuation of the influence of the output disturbance

at 1 15kHz (output filter cut-off frequency). The denominator ( ) ( ) ( ) ( ) ( )D z A z S z B z R z

can be represented as:

1 1 2

0 1 21 1D z c z p z p z (4.19)

Where the dominant closed-loop part 1

01 c z determines the desired performance of

disturbance rejection, the auxiliary part 1 2

1 21 p z p z allows introducing filtering effects

in some frequency regions. So the coefficient 0c can be varied between 0.1 and 0.99,

1 2

1 21 p z p z corresponds to a pair of complex zeros for which the frequency band

varies between 5

0 10 /rad s to 53 10 /rad s and damping ratio 0 is between 0.3 and 1.

Thus the coefficients 0c , 0 and 0 constitute three degrees of freedom (or chromosomes) for

the optimization problem. For each combination of 0c , 0 and 0 (i.e. each individual for the

genetic algorithm), the fuzzy logic quantifies the quality function (or fitness value). The

genetic algorithm then finds the optimal solution for 0c , 0 and 0 over twenty generations

with about thirty individuals for 16in , 0.9crossover probability and

0.02mutation probability .The individuals which have been tested by the genetic algorithm

are plotted in Fig. 4-11, where 0 0.7c , 5

0 1.8 10 /rad s and 0 0.6 .

0.20.3

0.40.5

0.60.7

0.80.9

1

0.20.3

0.40.5

0.60.7

0.80.9

11

1.251.5

1.752

2.252.5

2.753

3.253.5

3.754

x 105

The best set of parameters

0

0c

0 /rad s

Fig. 4-11 Diagram of individuals’ distribution in the genetic algorithm

68

In the RST structure of Fig. 4-5, the corresponding optimal polynomial ( )R z , ( )S z and

( )T z are calculated by solving the Bezout equation [I1]:

0 0 1 1 2 2 3 3

0 1 1 2 2

1 1 2 2

S d k T w k T w k T w k T w k

R y k R y k R y k

S d k S d k

(4.20)

where d k is the discrete value of RST output (duty ratio), w k and y k are the discrete

values of the refV and outV respectively, id k ,

iw k and iy k are the values in the precious

thi cycles respectively. For 4sf MHz application the parameters of the RST controller are

listed as below. 2

2

3 2

75.5459 145.4335 69.1413

1.629 0.6297

298.4724 815.587 743.5419 226.1755

R z z z

S z z z

T z z z z

(4.21)

The corresponding sensitivity functions of yyS , ybS and yuS for the RST controller are

given in Fig. 4-12. The gain of yyS at 1 (LC filter resonance) is -47dB. The good robustness

is represented with modulus margin 0.79RSTM , phase margin 61o

RST and delay

margin 2.2RST Ts ( Ts is the switching period). The determination of the fraction

precision of the PID parameters will be discussed latter in section 4.2.3 (Matlab simulation).

10-3

10-2

10-1

100

101

102

103

104

-90

-80

-70

-60

-50

-40

-30

-20

-10

0

10

fs [kHz]

S [

dB

]

Syy

Syb

Syu

Syy

(w1)RST

Fig. 4-12 Sensitivity functions for RST controller

The hardware implementation of the controller is quite simple: it just needs a few memories,

multipliers and adders in FPGA/ASIC.

69

4.2.3 Simulation Comparison

In order to quantify the controller dynamics, robustness and noise rejection properties, the

most important output-to-output sensitivity function yyS is presented in frequency domain in

Fig. 4-13 for the comparison between RST and PID controllers (derived from Fig. 4-4 and Fig.

4-12 respectively).

It can be seen that the gain of yyS at 15kHz (output filter cut-off frequency) determines the

rejection of the load variation disturbance at the output voltage. The lower the gain of yyS at

15kHz, the better the attenuation of this output disturbance. In addition the maximum value of

yyS corresponds to the inverse value of the modulus margin M . It is clear that the gain of

yyS at 15kHz is -47dB for RST controller against -28dB for the PID controller whereas their

robustness are similar. In other words RST has better attenuation of the load variation

disturbance performance than PID. The performance characteristics of the two controllers

(at 4sf MHz ) are shown in Table. 4-2.

Table. 4-2 The characteristics comparison of RST and PID controllers

Controller Modulus margin Delay margin Phase margin attenuation of load variation

RST 0.83RSTM 2.5RST Ts 62o

RST -47db

PID 0.79PIDM 2.2PID Ts 61o

PID -28db

101

102

103

-60

-50

-40

-30

-20

-10

0

f [KHz]

S[d

B]

-20dB

PID Syy

RST Syy

Fig. 4-13 Syy comparison plot of RST and PID controllers

The time domain behaviour of both controllers (PID and RST) is studied using Matlab/

Simulink. Considering that the digital controller is finally to be implemented in FPGA/ASIC,

the controllers’ parameters and all computations must be represented in fixed-point data

70

presentation instead of float-point form. The fixed-point parameters with limited precision

probably affect the accuracy of the computation. In order to obtain high accuracy, the

parameter’s precision is expected to be the highest. However for a fixed word-width register,

the availability of parameter’s range is contradictory with its precision. Furthermore for

certain FPGA/ASIC process, the available register’s word-width is contradictory with the

algorithm computation speed. Therefore the choice for the parameter’s precision should be

taken into account carefully with the restraints of word-width, parameter’s range and capacity

of process. In the studied case the ADC model has a 10-bit (i.e. ( )e k ) resolution and the

DPWM ratio (i.e. ( )d k ) is set to 11-bit resolution, which meets the condition of non-limit

cycle DPWM ADCN N [A7]. Thus the precision of the controller’s parameters are expected to

be at least as high as that of DPWM. Here we adopt a 13-bit (binary) precision for the

parameters which can achieve a 4-bit (decimal) fraction as fine as 0.0001 (see the parameters

above). The modelling of the digitally controlled buck converter is shown in Fig. 4-14, where

the buck converter is modelled by a hybrid model [S12] using Matlab s-function. In order to

keep the simulation close to practical implementation, all the calculation are computed in

fixed-point computation with 13-bit fraction.

Fig. 4-15 shows the dynamics response of the RST and the PID controller operating at

4MHz respectively when the load changes from 0.3A to 0.46A (R: 5Ω→3.3Ω). In order to

validate the disturbance rejection in larger range of variation, Fig. 4-16 shows the dynamic

results when the load changes from 3mA to 0.46A (R: 300Ω→3.3Ω). It can be seen that both

controllers can work in large range of load variation. The transient response of the RST

controller is superior to the PID controller since it offers shorter response time and produces

smaller undershoot and overshoot on the output voltage.

In1 Out1 Vref d C(t)D[N] Buck

S-function

In1Out1

Vref sampling

controller Buck

Vout sampling

FixPit

Fixed-Point

Setting

t

clock

Ramp Soft start Vout

Vin

R

PWM10-bit

10-bit

11-bit

Fig. 4-14 The modelling of the digitally controlled buck converter in Simulink

71

2.6 2.8 3 3.2 3.4 3.6

x 10-4

1.49

1.4913

1.4925

1.4937

1.495

1.4962

1.4975

1.4987

1.5

1.5012

1.5025

1.5037

1.505

Time: S/ div

Unit:

V /

div

PID control

RST control

(a) Output voltage Vout

2.6 2.8 3 3.2 3.4 3.6

x 10-4

0.2836

0.3086

0.3336

0.3586

0.3836

0.4086

0.4336

0.4586

0.4836

Time: S / div

Unit:

A /

div

RST control

PID control

(b) Inductance current IL

2.5 2.51 2.52 2.53 2.54 2.55 2.56 2.57

x 10-4

0.5065

0.5465

0.5865

0.6265

0.6665

0.7065

0.7465

0.7865

0.8265

0.8665

0.9065

0.9292

Time: S / div

duty

ratio

RST control

PID control

(c) PWM duty ratio d

Fig. 4-15 Dynamic response of both controllers when load changes from 0.3A to 0.46A:

output voltage Vout (a), inductance current IL (b) and PWM duty ratio d (c)

72

2.6 2.8 3 3.2 3.4 3.6

x 10-4

1.4685

1.4735

1.4785

1.4835

1.4885

1.4935

1.4985

1.5035

1.5085

1.5135

1.51851.5185

Times: S/div

Unit:

V /

div

PID control

RST control


2.6 2.8 3 3.2 3.4 3.6

x 10-4

-0.0465

0.0035

0.0535

0.1035

0.1535

0.2035

0.2535

0.3035

0.3535

0.4035

0.4535

0.5035

0.5535

0.6035

0.6535

0.6982

Time: S / div

Unit:

A /

div

RST control

PID control


2.5 2.51 2.52 2.53 2.54 2.55 2.56 2.57 2.58 2.59

x 10-4

0.456

0.496

0.536

0.576

0.616

0.656

0.696

0.736

0.776

0.816

0.856

0.896

0.936

0.976

1.015

Time: S / div

duty

ratio

RST control

PID control


Fig. 4-16 Dynamic response of both controllers when load changes from 3mA to 0.46A:

output voltage Vout (a), inductance current IL (b) and PWM duty ratio d (c)

73

4.3 Tri-mode Controller Based on RST and PID

In order to reduce the energy consumption of the digital controller in the future ASIC

implementation, a so-called Tri-mode controller is proposed here. The idea of the Tri-mode

controller is to minimize power consumption of the control algorithm when it is in steady-

state and stand-by mode, and obtain the highest performance dynamic response when the load

features a transient variation. The Tri-mode controller includes the PID and robust RST

controllers which have been designed previously.

4.3.1 Design of a Tri-mode Controller

Previous section has detailed the RST controller for high-performance of dynamic response.

So it is preferred when the converter load changes fastly. However compared with the PID

controller, this advanced RST algorithm needs more resources such as multipliers, adders, and

computation steps to realize. Review the digital PID controller formula in section 4.2.1,

0 1 1 2 2 1 1 1 21d k r e k re k r e k s d k s d k (4.22)

and the digital RST controller formula in section 4.2.2,

0 1 1 2 2 3 3

0 1 1 2 2

1 1 2 2

d k T w k T w k T w k T w k

R y k R y k R y k

S d k S d k

(4.23)

then the resource consumption and performance of the both controllers can be summarized in

Table 4-3. From the simulation results in section 4.2.3, the dynamic and steady-state

performances of both controllers can be also summarized in Table 4-3. It can be seen that the

RST implementation in FPGA consumes more area than that of PID. This means it would

consume more area in ASIC implementation, resulting in an increase in power consumption.

Table. 4-3 Resource consumption and performance of RST and PID controllers

Controller Multipliers Adders Computation steps FPGA area Dynamic Steady-state

RST 9 8 8 More Good Good

PID 5 4 4 Less Medium Good

In fact when the buck converter works in steady-state, i.e., the load is stable, the primary

task of the controller is to maintain the output voltage stable. Thus the control law PID which

features less area but well maintains the output voltage stable is suitable with respect to power

consumption. Therefore using the PID controller for steady-state can not only keep the output

voltage stable, but also relax tight requirement of algorithm computation, and save energy in

future ASIC application.

74

In addition many portable devices spend a large part of time in idle mode, i.e. in stand-by

mode. Under stand-by conditions, the portable device can not only turn off some external

functions such as display backlight, but also can reduce internal power consumption inside the

controller. Thus a so-called “Quarter PID” controller which has the same structure as the PID

applied in steady-state but clocked at a quarter of the switching clock sf , is considered for

stand-by modes. That is to say that the PID controller will be updated under-sampled mode,

i.e. 4sf changing rate mode, and its computation will renew once per four periods with

respect to the buck converter operation.

The Tri-mode controller shown in Fig. 4-17 consists of a mode selection block, the RST

and the PID controllers. According to different modes, the mode selection block will select

the different controllers: RST for transient-state, PID for steady-state and Quarter PID for

stand-by mode.

Mode-selection

block

DPWM

block

Vref[n]

Vout[n]

e[n]

Delay

z-1

Transient-state

RST control

Steady-state

PID control

Stand-by

Quarter PID control

fsmode-signal

m

Activity signal FCLK

c(t)

d[n]

d[n]

d[n]

Fig. 4-17 Block diagram of the Tri-mode controller

4.3.2 Operation of the Tri-mode Controller

The Tri-mode controller depends on an external activity signal m or a sensor to select the

proper controller. Obtaining this activity-signal is out of the scope of the paper but the digital

functions inside any low-power systems are able to issue such a signal. For instance in the

operation of a portable phone, the activity signal is set low-voltage level m =’0’ when it is in

stand-by and high-voltage level m =’1’ when it is in working state. The change among the

three states is performed through a mode-selection block. The function of this block is to

detect the state of activity signal and select the corresponding control mode. To eliminate

potential stability problems related to dynamic mode switching between different control

75

modes [R1], the operation of the Tri-mode is designed as shown in Fig. 4-18 (a), and the

mode changes procedure management is shown in Fig. 4-18 (b). The tuning time 1t and 2t

of RST controller for transient tuning can be adjusted to meet the practical application. For

example the constant tuning time 1tunet is set for 1t and 2tunet for 2t here. The e n from the

voltage error between refV and outV is normalized in discrete-time data and the maximum

tolerant voltage error is set 1e n , where the number “1” means a certain voltage such as

15mV or other values which are chosen by user. In brief the requirements of the signal m, the

tuning time 1t and 2t , and the maximum tolerant voltage error e n , can be adapted in

practical implementation. This is not discussed here.

Fig. 14 (a)

Mode I

Quarter PID

Stand-by

Mode II

RST Control

Transient

Mode III

PID Control

Steady-state

Transient

Mode II

RST Control

Mode I

Quarter PID

Stand-by

1 2 3 4 1

load

t

m=’0' m=’1' m=’1' m=’0' m=’0'

t1 t2 t3 t40∆t1 ∆t2

Tuningtime

Tuningtime

(a)

Stand-by

PID control (Quarter)

Mode I

Transient

RST control

Mode II

Steady-state

PID control

Mode III

loading

e[n]<1 and ∆t1>ttune1

unloading

e[n]>1 or ∆t1<ttune1

e[n]>1 or ∆t2<ttune2

e[n]<1

m=’1'

e[n]<1

m=’0'e[n]<1 and ∆t2>ttune2

e[n]>1

e[n]>1

(b)

Fig. 4-18 Operation procedure of the Tri-mode controller (a) and its state change management (b)

The operation procedure of the Tri-mode controller is detailed as follow:

1) Initially, after the SMPS initialization, it is assumed that the controller is in stand-by

mode, using the Quarter PID to regulate the output voltage. It will be kept in this state until

the output variation is larger than error unity, i.e., 1e n (normalization), or an activity

signal m=’1’ is detected. Then the controller switches to procedure 2).

2) The controller will switch to transient-state using RST control law to regulate the SMPS

output voltage, and this control mode will be maintained long enough tuning ( 1 1tunet t ) to

obtain 1e n condition, which means the SMPS enters a steady-state mode.

3) In steady-state, controller selects the PID controller to regulate the output voltage. This

state will be maintained until the output variation is larger than error unity, i.e., 1e n , or an

activity signal m =’0’ is detected.

76

4) The RST controller will be selected again for the regulation of unloading in transient-

state. This control mode will be held long enough tuning time 2 2tunet t until 1e n

condition occur, which means that unloading has finished and the SMPS arrives in a steady-

state mode again.

5) After quit the RST transient tuning, the controller stays in an unloaded situation and will

be set in stand-by, which returns to procedure 1) again for a next transient cycle.

Compared with the Dual-mode controller designed with the simple hysteretic logic method

in [Z2], this Tri-mode controller offers more flexible selection with three modes to save the

energy consumption of control algorithm. Due to the Tri-mode controller where the Quarter

PID updates the whole control-law computation under-sampled mode at 1 4 sf frequency,

evidently it can reduce the energy consumption compared with those alone PID and RST

controllers. Unfortunately there is no sufficient proof to prove the point that how much energy

can be saved and how much efficiency can be improved in this current case of FPGA

prototype implementation. A 0.35µm CMOS technology ASIC implementation of the digital

controller is under process and the chip will be available in a coup of months, which enables

the performance analysis and energy evaluation.

4.4 Summary

In this chapter a classical PID controller and a robust RST approach have been

designed for the voltage-controlled buck converter operating in CCM. Based on the

sensitivity functions with respect to the modulus margin M and delay margin , an off-

line automated design of a robust RST digital controller is detailed. In Matlab/Simulink tool

box, the Fuzzy logic is used to qualify the robustness of a controller and noise rejection

properties, and a Genetic algorithm is used to optimize the robust RST controller. The

simulation results are presented to verify that the RST controller offers better performances

compared with a classical PID controller. For the consideration of energy reduction inside

digital controller, a Tri-mode controller based on the PID and robust RST controllers is

proposed here. In steady-state, the PID control law is applied to minimize power consumption

and keep output voltage accuracy. While in stand-by mode if the converter is light-loaded,

then the controller is clocked at a frequency lower than the converter switching frequency for

consideration of energy consumption. In transient load, the RST robust control law is adopted

to obtain high performance response.

77

Chapter 5 Design of a Digital Sliding Mode Controller

In chapter 4 the linear controllers PID and RST are developed to regulate the Buck

converter output voltage. Furthermore based on the PID and RST control laws, a Tri-mode

controller is proposed to reduce power consumption inside. However SMPS converters are

nonlinear system in nature due to their switching property. One of the most important features

of the DC-DC converter is related to Variable Structure Systems (VSS) characterises. VSS are

systems physically changed intentionally during time with respect to the structure control law.

The instances at which the changing of the structure occurs are determined by the current state

of the system. From this point of view SMPS represents a particular class of VSS since their

structure is periodically changed by the action of controlled switches and diodes. Thus to

enhance the dynamic performance of SMPS, nonlinear control methods, especially those

nonlinear controllers with VSS are essential.

Sliding-Mode-Control (SMC), a form of the large group of VSS controller was

theoretically introduced a few decades ago. SMC for VSS offers an alternative way to

implement a control action which exploits the inherent variable structure nature of DC-DC

converters [L1, P2, P3]. In particular the converter switches are driven as a function of the

instantaneous values of the state variables in such a way so as to force the system trajectory to

stay on a suitable selected surface on the phase space called the sliding surface. SMC has

been improved suitable for DC-DC converters by several researchers in recent literatures [R7,

R8, A5, S4, S5, S6].

However because of the SMC principles, the operation requires virtually infinite switching

frequency that challenges the feasibility of SMC in low-power SMPS converters. In order to

fix the very high and variable switching frequency, a fixed-frequency PWM-based SMC

which derived from Hysteresis Modulator (HM) based SMC [B3, P4, M2] has been recently

proposed in [S6, G1] but as an analog control for medium power SMPS applications where

the switching frequency is in the range of hundreds kHz. Unfortunately analog PWM-based

SMC is difficult to control high-frequency low-power SMPS. It is sensitive to analog

component variations, and it can be mixed only with analog signals in the converter and not

with signals inside a high-level digital power management unit. By contrast, digital DPWM-

based SMC designed inside the controller is easier to implement, is insensitive to analog

78

component variations and offers more flexibility. Therefore, this chapter presents an original

implementation of a DPWM-based SMC for a high-switching frequency SMPS.

5.1 Review of Sliding Mode Control

Before SMC application for digitally controlled SMPS, it is necessary to briefly introduce

the theory and operation of SMC. This section covers the theoretical aspects of the SMC.

5.1.1 Sliding Mode Controller: An Ideal Controller in Theory

Sliding Mode Control (SMC) was introduced initially for the robust control of Variable

Structure Systems (VSS) [C3, W2]. The basic principle of SMC is to employ a certain sliding

surface as a reference path, such that the state variables trajectory can be directed towards the

desired equilibrium. Theoretically such ideology of the SMC can be fully achieved only with

the absolute compliances to certain conditions, namely the existence conditions, and the

condition that the system operates at infinite switching frequency.

In such respect what is derived is an idealized controlled system, whereby no external

disturbance or system uncertainties can affect the ideal control performance for zero

regulation error and very fast dynamic response. These features fundamentally describe the

expectancy of an ideally controlled system. Hence in a certain sense, the SMC is actually a

type of ideal controller for the class of VSS.

5.1.2 Theory of Sliding Mode Controller

SMC theory has been applied to many nonlinear VSS to improve the systems performance.

Variable Structure Controllers (VSC) act as a high-speed switched feedback control resulting

in sliding mode. The purpose of the switching control law is to drive the nonlinear plant state

trajectory onto a pre-specified (user-chosen) surface in the state space and to maintain the

plant state trajectory on this surface for subsequent time. The surface is called a switching

surface. When the plant state trajectory is “above” the surface, a feedback path has a given

gain and another gain when the trajectory drops “below” the surface. This surface defines the

rule for proper switching. The surface is also called a sliding surface (sliding manifold).

Ideally, once intercepted, the switched control maintains the plant state trajectory on the

surface for all subsequent time and the plant state trajectory slides along this surface until the

origin. For example the surface 0S and the plant state trajectory of a SMC is shown in Fig.

79

5-1, where the SMC includes three state variables 1x , 2x and 3x . The main idea of SMC is to

bring and keep the error on a sliding surface such that the system is insensitive to the

disturbances and parameter changes. Therefore the SMC is very robust.

The SMC design approach consists of two components:

<1> The first step is to build a sliding surface with the different forms of control objectives.

<2> The second step is to determine the existence of sliding motion and ensure the stability.

1x

2x

3x

O

Plant state

trajectory

Converging

to the origin

Surface S=0

Fig. 5-1 Graphical representation of the plant state trajectory behaviour in SMC process

Considering a general SISO (single-input-single-output) autonomous nonlinear system, the

sliding-mode controlled system can be modelled by:

( ) ( )

( ) T

x f x g x u

S x K x (5.1)

Where nx is the variable vector of SMC, f and g are state vectors defined on n , S is the

sliding surface, 1,. . . ,TT

nK K K is the sliding gains parameters and u is the switch

position which makes the system discontinuous:

, ( ) 0

, ( ) 0

u if S xu

u if S x (5.2)

where u and u are the switching signals respectively in the range of ( ) 0S x and ( ) 0S x .

In order that the sliding motion can exist, the state variable phase trajectory must be

directed towards the sliding surface ( ) 0S x to obtain a stable solution of the system as

shown in Fig. 5-1. Thus it is necessary to determine the sliding motion range for the SMC, i.e.

to determine the existence conditions [F1, J7, V2] and ensure the surface exist. This task can

be performed using the Lyapunov‟s second method [J6], where the Lyapunov‟s function V is

generally defined as 2

1 2V S x . The existence conditions must be satisfied:

( ) ( ) 0 S x S x (5.3)

Thus the existence conditions of SMC can be written as:

80

( ) 0 ( ) 0

( ) 0 ( ) 0

S x if S x

S x if S x

(5.4)

Substituting equation (5.1) and (5.2) into (5.4) then the existence conditions of SMC can be

rewritten as:

( ) ( ) ( ) 0 0

( ) ( ) ( ) 0 0

T

T

S x K f x g x u if S x


(5.5)

In that way the existence conditions for the SMC are ensured.

5.2 Sliding Mode Control for DC-DC SMPS

DC-DC converters, a type of VSS, are non-linear in nature. Moreover the parameters of

SMPS change with the load variation. One of the important features of the SMC in the VSS is

its robustness, which makes the system insensitive to the parameters variation. From this

point of view the SMC is particularly suitable for the application of SMPS converter.

5.2.1 Quasi-Sliding-Mode (QSM) Controller

In order to acquire high performance for VSS, the ideal SMC must be operated at high

enough switching frequency on the sliding surface. Thus the nature of the sliding mode

controller is to ideally operate at an infinite switching frequency such that the controlled

variables can track a certain reference path to achieve the desired dynamic response and

steady-state operation [V2]. This requirement for operation at infinite switching frequency,

however, challenges the feasibility of applying SMC in DC-DC power converters. Hence for

SMC to be applicable in power converters, their switching frequencies must be constricted

within a practical range.

In order to limit the switching frequency, different methods such as Hysteresis-Mode,

Constant-on-Time and Limited-Maximum-Frequency are proposed [B3]. Among these

conventional limiting-frequency methods, the most popular way is the Hysteresis-Mode (HM-

based) SMC that will be introduced in next sub-section.

Nevertheless this restriction of the sliding mode controller switching frequency transforms

the sliding-mode controller into a type of quasi-sliding-mode (QSM) controller, which

operates as an approximation of the ideal SMC. Since all SMC in practical power converters

81

are frequency-limited, they are, strictly speaking, a type of quasi-sliding-mode (QSM)

controllers.

5.2.2 Conventional HM-based SMC

A review of the literature [L1, B3, M2, P4, V3] shows that most of the previously proposed

SMC for switching power converters are Hysteresis-Modulation (HM) based, which requires

a bang–bang type controller to perform the switching control shown in Fig. 5-2.

u

O

Hysteresis-base

SMC

S

O t

S1u

Switch on

S 0uSwitch off

0u 1u

1u0u

S S

Fig. 5-2 Hysteresis Modulation-based SMC

Since there are only two available choices “ON” ( 1u ) and “OFF” ( 0u ) for switch action

in SMPS, then this method is easily accomplished as shown the equation (5.2):

1 ' ' ( )

0 ' ' ( )

ON if S x

u OFF if S x

previous state otherwise

(5.6)

where is an arbitrarily small value around zero.

The introduction of a hysteresis band with the boundary conditions ( )S x and

( )S x provides a form to limit the infinite high switching frequency. However due to the

lack of systematic design methods and implementation criteria, the implementation of HM-

based SMC for SMPS still relies on the trial-and-error tuning of the magnitude to achieve

the desired switching frequency for a particular operating condition. The performance of HM-

based SMC depends on the experience of designer and engineer.

5.2.3 The Requirement of Fixed-Frequency SMC

Clearly from equation (5.6) that the infinite high switching frequency is limited by the

hysteresis band value , but the SMPS operation frequencies yet rely on the bang-bang

magnitude , i.e. HM-based SMC switching frequency is still variable, which inherits the

typical disadvantages of having variable switching frequency operation and being highly

control-sensitive to noise. Obviously, when switching frequency is variable, designing the

82

filters under a worst-case (lowest) frequency condition will result in oversized filters.

Moreover, the variation of the switching frequency also deteriorates the regulation

performance of the converters.

In order to keep the switching frequency fixed, two basic approaches have been proposed

in the implementation of conventional HM-based SMC. One approach is to incorporate a

constant ramp or timing function directly into the controller [P2, B3, L2]. However this

method comes at an expense of additional hardware circuits, as well as deteriorated transient

response in the system performance caused by the superposition of the ramp function upon

the SMC switching function. Another approach is to include some forms of adaptive control

into the HM-based SMC to contain the switching frequency variation [V3, S7]. However the

architecture of this adaptive sliding mode controller is relatively more complex, and increase

the implementation cost of the controller.

On the other hand, fixed switching frequency SMC can also be obtained by employing

pulse-width modulation (PWM) instead of HM [S4, V4, S8]. In practice, this is similar to

classical PWM control schemes in which the control signal is compared to the ramp

waveform to generate a discrete gate pulse signal [D5]. The advantages of PWM-based SMC

are that it does not need additional hardware circuitries since the switching function is

performed by the PWM modulator, which can be implemented inside the digital controller.

However in order to preserve the original sliding mode control laws, the practical

implementation of PWM-based SMC is nontrivial, especially when both current and voltage

state variables are involved. Hence this approach is not always implementable for some

conventional HM-based SMC types.

5.2.4 PWM-Based SMC

Conventional HM-based SMC application is based on the equivalent control [V2, C3, W2],

but PWM-based SMC application is based on the averaged duty control [S4, V4, S8, G1].

Because of the shortage of variable frequency operation in HM-based SMC, PWM-based

SMC recently has been used to replace the HM-based SMC. However there is seldom

theoretical analysis for the establishment of their relationship. In order to better understand

how the PWM can replace the HM-based sliding mode control, it is necessary to briefly study

equivalent control and averaged duty control.

83

A. Equivalent Control

As discussed previously, to achieve an ideal SMC operation, the system must be operated

at an infinite switching frequency so that the state variables trajectory is oriented precisely on

the sliding surface. However in the practical case of finite switching frequency, the trajectory

will oscillate in the vicinity of the sliding surface while moving towards the origin (see Fig. 5-

1 with three variables). It is possible to identify the movement of the trajectory as a

composition of two isolate components: a fast-moving (high-frequency) component and a

slow-moving (low-frequency) component shown in Fig. 5-3.

1x

2x

3x

O

Sliding

surface

Actual

trajectory

Converging

to the origin

=1x

2x

3x

O

Sliding

surface

slow moving

(low-frequency

component)

1x

2x

3x

O

fast-moving

(high-frequency

component)

Sliding

surface

++Ve

-Ve

Converging

to the origin

Converging

to the origin

Fig. 5-3 High and low frequency components of the state trajectory on sliding surface

where sliding surface 0S and 0S , ve and ve are the directions respectively below

and above the surface S . It can be seen that the high-frequency component is actually a

discontinuous trajectory that alternates between ve and ve direction, whereas the low-

frequency component is actually a continuous trajectory that moves along the sliding plane.

Since the movement of the trajectory is an effective consequence of the input switches action

u , it is therefore possible to relate the corresponding low-frequency and high-frequency

components of the trajectory to a low-frequency continuous switching action lowu , where

0 1lowu , and a high-frequency discontinuous switching action highu , and that

low highu u u . Under such assumptions, the switching action of highu produces only the high-

frequency trajectory component, and the switching action of lowu produces only the low-

frequency trajectory component.

Because the high-frequency component is often filtered out by the SMPS converter filter, it

is reasonable to consider the effect of the high-frequency discontinuous switching action

0highu , and only the low-frequency continuous switching action lowu acts as the desired

switching action u that will produce a trajectory that is a near equivalence to an ideal SMC

operation trajectory. This is the so-called equivalent control. The equivalent control signal,

i.e., equ , is actually the low-frequency continuous switching action lowu described above:

low

eq

low eq

u uu u

u u (5.7)

Then the sliding-mode controlled system in equation (5.1) can be rewritten as

84

( ) ( )

( )

eq

T

x f x g x u

S x K x

(5.8)

B. Averaged Duty Control

In conventional PWM control which is also known as the averaged duty control, the

control input u is switched between „1‟ and „0‟ once per switching cycle for a fixed small

duration . The time instance where the switching occurs is determined by the sampled value

of the state variables at the beginning of each switching cycle. Duty ratio d is then the

fraction of the switching cycle in which the control holds the value 1. It is normally a smooth

function of the state vector x , and it is denoted by d x , where 0 1d x . Then for each

switching cycle interval during the time , , the control input u can be written as

1

0

u if t d xu

u if d x t (5.9)

It allows that a system ( ) ( )x f x g x u can be expressed as

+gd x

d xx x x dt x f x x dt f x dt (5.10)

The ideal average model of the PWM-controlled system response is obtained by allowing the

duty ratio frequency to tend to infinity, i.e., to approach zero. Under such consideration,

the above equation becomes

0 0

0

lim lim

lim

d x d x

d x

d x

f x dt f x dt g x dtx x

f x dt g x dt

(5.11)

i.e.,

dx

x f x g x d xdt

(5.12)

which is referred as the averaged PWM-controlled system. Therefore, it is shown that as the

duty frequency tends to infinity ( 0 ), the ideal average behaviour of the PWM-controlled

system is represented by the smooth response of the system constituted by the duty ratio d . It

should also be noted that the duty ratio d replaces the discrete function u in the same manner

as the equivalent control equ of the SMC scheme to obtain (5.8). Hence the relationship

between equivalent control and averaged duty control can be established

equ d x (5.13)

85

C. PWM-Based SMC Replace HM-Based SMC

Hence from the above review of equivalent control for HM-based SMC and averaged duty

control for PWM-based SMC, it is very interesting that the PWM-based SMC can be used to

replace the HM-based SMC. The PWM-based SMC can not only limit infinite high switching

frequency but also can fix the variable switching frequency for SMPS application.

The analysis of equivalent control and averaged duty control has proven that their

relationship can be established. First in sliding mode control, the discrete control input (gate

signal) u can be theoretically replaced by a smooth function known as the equivalent control

signal equ [V2, C3, W2, S7]. Second at high switching frequency, the equivalent control is

effectively an averaged duty control signal d [S4, V4, S8, G1]. Since averaged duty ratio is

basically also a smooth analytic function of the discrete control pulses in PWM, we can obtain

a PWM-based SMC by mapping the equivalent control function into the averaged duty

control in the pulse-width modulator, i.e., eqd u . Finally the substitution of PWM-based

SMC for HM-based SMC can be shown in Fig. 5-4.

Sliding

Control

ueq u

O

HM-based SMC

udSliding

Control

tontoffclock

PWM

PWM-based SMC

Equivalent

controlDuty ratio

control

S S

Fig. 5-4 PWM-based SMC is sued to replace HM-based SMC

5.3 Design of a DPWM-Based SMC

Most of the existing SMC applied for SMPS converters are designed in analog control

operating at low to medium frequency range (hundreds of kHz). This is not adequate to meet

the requirements of small-size and high-frequency for today‟s low-cost high-performance

SMPS. These explain why the application of SMC in DC–DC converters has only been of

academic/research interest but of little practical application.

Fortunately as the theoretical groundwork of SMC is fairly matured, PWM technique has

been applied to SMC and digital CMOS technology has been rapidly developed, it is time to

direct more research efforts towards developing practical high-frequency digital PWM-based

SMC for SMPS converters. In this section we present a practical design of DPWM-based

SMC application to a buck converter. Our focus in this design is the application of SMC to

converter operating in continuous current mode (CCM), and the discontinuous current mode

86

(DCM) is not discussed here. The system modeling, derivation of existence condition and

selection of parameters for SMC are detailed in following sections.

5.3.1 System Modelling for Sliding-Mode Controller

The first step to the design of a SMC is to determine the state variables in terms of the

desired the sliding model controller. Fig. 5-5 shows the schematic diagrams of the proposed

PID-type SMC voltage controller for a buck converter. The sliding mode controller involves

the output voltage error and its integral and differential portions. Unlike most existing SMC

voltage controllers, besides the differential portion, it also takes into account an additional

voltage error integral term to reduce the steady-state dc error of the output voltage.

VinL

C R

Vout

PWM 1

Q2

PWM2

Q1

SMC

X

-

+Vref

Vout

x1ueq

1K

2

dK

dt

3K dt

X

++

+

S

( )c t

PWM

Hybrid

DPWM

iout iL iC

VC

VL

( ) 0 ( ) 0

( ) 0 ( ) 0

S x if S x

S x if S x

Fig. 5-5 The schematic diagram of a PID-type SMC for a digitally controlled buck converter

Where the output voltage outV is the SMC control objective, 1 2 3, ,

TK K K K is the sliding

parameter of SMC and the control variable x can be expressed as:

1

2

3

ref out

ref out

ref out

V V

xd V V

x xdt

xV V dt

(5.14)

where refV represents the reference voltage, 1x , 2x and 3x are respectively the voltage error

and its differential and integral portions. Extracting the time differentiation of equation (5.14)

leads to

1 2

2 2

13

ref out

ref out

ref out

dV V

dtx x

d V Vdx x x

dt dtx

xd

V V dtdt

(5.15)

87

For easy discussion, assuming that refV is constant and capacitor ESR is zero, then

1

out c cref out

dV dV idx V V

dt dt dt C (5.16)

From equation (5.15) and (5.16), 2x comes as:

2 1

Cid dx x

dt dt C (5.17)

Considering the CCM operation,

C L outi i i (5.18)

Substituting equation (5.18) into (5.17) results in

2

1L out outLi i didid

xdt C C dt dt

(5.19)

Under the situation of CCM and averaged duty control,

L L

L in eq out

V di

L dt

V V u V

(5.20)

Since

outout

Vi

R (5.21)

Then

1out outdi dV

dt R dt (5.22)

Substituting equations (5.20) and (5.22) into (5.19), we can obtain

2

1 1in eq out outV u V dV

xC L R dt

(5.23)

Because of 1 ref outx V V , equation (5.23) can be rewritten as

1

2

1in eq ref outV u V x dV

xLC LC RC dt

(5.24)

Substituting equation (5.16) into (5.24), then

1 12

in eq refV u V x xx

LC LC RC (5.25)

Equation (5.17) finally leads to:

1 22

in eq refV u V x xx

LC LC RC (5.26)

Substituting equation (5.26) into equation (5.15), then

11

2 2

33

0 00 1 0

1 1 0

1 0 0 0 0

refineq

xx

VVx x x u

LC RC LC LCx

x

(5.27)

88

Equation (5.27) can be rewritten in a standard form of state-space description:

eqx Ax Bu H (5.28)

Confronting with (5.8), it is clear that

1 1 2 2 3 3

,

eq

T

T T

eq

x f x g x u

f x Ax H g x B

S x K x K x K x K x

S x K x K Ax Bu H

(5.29)

5.3.2 Derivation of DPWM-Based SMC

As mentioned previously, since the relationship between equivalent control and averaged

duty control has been established and the equivalent control signal equ has been proven

equivalent to PWM duty ratio d for SMC, then the derivation of the DPWM-based SMC can

be achieved by the equivalent control on the sliding surface S . Combining the preceding

equations (5.4), (5.27) and (5.28) with (5.29), we can derivate the equivalent control input

signal equ using the invariance conditions by setting 0S x , i.e.,

0T T

eqS x K x K Ax Bu H (5.30)

Now solving for equivalent control function (5.30) yields

1

312 1

2 2

1 1 1T T

eq ref

in

KKu K B K Ax H LC x LC x V

V K RC K LC (5.31)

Substituting 1 ref outx V V and 2 1outdV

x xdt

into equation (5.31), then

31

2 2

1 1 1outeq ref ref out

in

dV KKu V LC LC V V

V K RC dt K LC (5.32)

where equ is continuous and equals to PWM duty ratio d , and 0 1equ d , parameters

1 2K K and 3 2K K are to be determined which corresponds to the desired SMC dynamics that

will be discussed in next section.

A close inspection of equation (5.32) reveals that the control signal equ involves the time

differentiation of output voltage, out CdV dt i C , which results in the need of measurements

(such as current sensor or current-to-voltage sampling circuit) for capacitor current Ci and

thus increase the size and cost of the digital controller. Since the buck converter has the

output voltage feedback outV and the SMC controller is implemented in full digital form, it is

feasible to design a software observer or a mathematic function for outV to eliminate the need

for hardware measurement. Unfortunately sophisticated software observer needs supplement

89

resources. The observer design issue is not discussed here. A simple numeric derivation is

adopted to calculate the rate of output voltage changing in the FPGA implementation:

1out outout

n

s

V n V ndVV

dt T (5.33)

where outV n and 1outV n are the output voltage in thn and 1

thn cycle respectively, sT

is PWM switching period. Link equations (5.32) and (5.33), we can obtain the duty ratio of

PWM-based SMC controller

31

2 2

1 1 1

0 1

neq ref ref out

in

eq

KKu V LC V LC V V

V K RC K LC

u

(5.34)

5.3.3 Determination of SMC Parameters

Equation (5.34) gives the complete information for the duty ratio signal equ of DPWM-

based SMC, where two sliding parameters 1 2K K and 3 2K K still need to be determined

corresponding to the desired dynamics. For this purpose we employ the Ackermann‟s

Formula [J7] to design the SMC also called as PID-type SMC to select the sliding parameters

in this case. The selection of sliding parameters is based on the desired second-order dynamic

properties. In this way, the sliding motion ensures that the state trajectory of the system under

SMC operation will always reach a stable equilibrium point. As stated in Equations (5.4) and

(5.14), the surface of the PID-type SMC at the stable equilibrium point, 0S x can be

detailed as:

11 1 2 2 3 3 1 1 2 3 1 0T dx

S x K x K x K x K x K x K K x dtdt

(5.35)

According to Ackermann‟s Formula [J7] for a standard second-order system dynamics, the

equation (5.35) can be transformed into

2

31 1 112

2 2

0Kd x K dx

xdt K dt K

(5.36)

Equation (5.43) can be rewritten as

2

1 1 12 0n nx x x (5.37)

where 3 2/n K K is the undamped natural frequency and

1 2 32K K K is the damping

ratio. Thus the sliding parameters now depend on the desired dynamic performance that can

be chosen by user.

90

5.3.4 Derivation of Existence Conditions

To achieve the design specifications, the SMC must maintain the variables state trajectory

on the surface for all subsequent time and the state trajectory slides along this surface. Thus it

is necessary to determine the sliding motion range for the SMC, i.e., to ensure the surface

exist and to determine the existence conditions for sliding surface. As stated previously, this

task is performed using the Lyapunov‟s second method [J6]. Recalling of the existence

conditions in equation (5.5), the existence conditions must be satisfied:

( ) ( ) ( ) 0 0

( ) ( ) ( ) 0 0

T

T



(5.38)

Substituting equation (5.2) and (5.29) into (5.30),

0

0

( ) 0 0

( ) 0 0

T

S

T

S

S x K Ax Bu D if S x

S x K Ax Bu D if S x

(5.39)

Detailing equation (5.39) leads to

Case 1: 0S , 1u , then 0S :

Equation (5.39) can be detailed:

2 2 21 2 3 10

0ref inS

K K KS x K x K x V V

RC LC LC (5.40)

Case 2: 0S , 0u , then 0S :

Equation (5.39) can be detailed:

2 21 2 3 1 20

0ref

S

VK KS x K x K x K

RC LC LC (5.41)

It can be seen that 1x , 2x and S x construct the sliding surface in a 3-D space, which is

the existence range of sliding motion for SMC. In order to simplify the analysis of the

existence, the 3-D space can be mapped onto the 2-phase-plane ( 1 2x x ). Assuming 2K is

positive, the existence range of surface for the PID-type SMC, equation (5.40) and (5.41), can

be represented with the two lines in 1 2x x phase-plane:

311 2 1

2 2

312 2 1

2 2

1 10

1 10

ref in

ref

V VKKx x x

K RC K LC LC

VKKx x x

K RC K LC LC

(5.42)

Thus the two lines 1 0x and

2 0x respectively determine the two boundaries of

sliding surface existence range. From equation (5.42), it can be seen the two lines has the

91

same slope in the 1 2x x phase plane, where line 1 0x passes through the point A:

3 2 1 , 0in refV V K K LC LC and point B: 1 20, 1in refV V K K RC LC ,

line 2 0x passes through the points point C:

3 2 1 , 0refV K K LC LC and

point D: 1 20, 1refV K K RC LC , and the axis

1 ref outx V V is limited with the

minimum value point E: , 0ref inV V and the maximum value point , 0refV . For

different values of the parameters 1 2K K and 3 2K K , the slope of the two parallel lines is

variable. Therefore the existence conditions can be illustrated in two situations: (1) positive

slope region and (2) negative slope region for each line. As stated above, the sliding

parameters 1 2K K and 3 2K K are variable with different dynamical response frequency crf ,

thus the points A, B, C and D will be located at axis in positive or negative region. The

regions of existence for SMC is shown in Fig. 5-6 with four possibilities: (a) 1 2 1K K RC

and 3 2 1K K LC , (b)

1 2 1K K RC and 3 2 1K K LC , (c)

1 2 1K K RC and

3 2 1K K LC , and (d) 1 2 1K K RC and

3 2 1K K LC , where (a) and (d) belong to

situation (2) with negative slope, (b) and (c) belong to situation (1) with positive slope.

According to equation (5.40), when the buck converter operates at 4MHz, the parameters

are 1 2 1K K RC and

3 2 1K K LC . Thus the existence region for the PID-type SMC

in this case can be represented in Fig. 5-6 (c). The existence conditions show the region of

existence of the SMC, which provides a range of employable sliding area that will ensure the

state trajectory keep sliding along the surface ( ) 0S x until reaching the stable operation at

the origin O. x2

x1

λ1=0

O

CA

S=0

(a) (b)

λ2=0

D

B

E F

x2

x1

λ1=0

O

A

C

S=0

λ2=0

B

D

E F

(c) (d)

x2

x1

λ2=0

OC

A

S=0

λ1=0

D

B

E F

x2

x1

λ2=0

O

AC

S=0

λ1=0

B

D

E F

Fig. 5-6 region of existence for the sliding mode mapped in the phase plane with four possibilities (a, b, c, d)

92

5.3.5 Stability for SMC

Besides the existence conditions, the sliding mode controller should also comply with the

stability conditions. The stability is an important item which is to ensure that the sliding

surface will direct the state trajectory toward the stable equilibrium points in existence regions.

In this work the analysis of dynamic response and stability for the PID-type SMC can be

started the surface 0S x and 0S x . Since the state variables 1 2 3, ,x x x x are in

phase canonical form, the 0S x can be rewritten in Laplace form as:

2 311 2 3

2 2

10 0

KKK X s K sX s K X s s s

s K K (5.43)

Firstly using the Routh‟s stability criterion to this second order linear polynomial to

determine the stability conditions, 2

3 2

1

1 2

0 2

1 3 2

1

0

s K K

s K K

s K K K

(5.44)

The condition for the stability must meet 0 , which means all the coefficients 1 2 3, , K K K

must be with the same sign (positive or negative), i.e., 1,2,3 0K or 1,2,3 0K . This can ensure

all roots have negative real parts.

Secondly Extracting the time differential, the 0S x can be rearranged into a stand

second-order system form:

2 22 0n ns s (5.45)

which is identical to equation (5.37), where the values of damping ratio , undamped natural

frequency n and two eigenvalues 1,2s are

3 2 1 3 2

2

1,2

, 2

1

n

n n

K K K K K

s j (5.46)

Since 0 then 1K must be positive. Recalling that 1 2 3, , K K K must be with the same sign,

thus finally all the coefficients should be positive for stable operation.

5.3.6 Matlab Simulation of SMC for a Buck Converter

The time domain behaviour of the proposed digital DPWM-based SMC is verified on a

buck converter using Matlab/ simulink shown in Fig. 5-6, where the buck converter circuit

elements are: 4.7L µH , 22C µF , 5R , 3.0inV V , 1.5outV V and switching

frequency 4sf MHz .

93

In1 Out1 Vref d C(t)D[N] Buck

S-function

In1Out1

Vref sampling

SMC Buck

Vout sampling

FixPit

Fixed-Point Settingt

clock

Ramp Soft start Vout

Vin

R

PWM10-bit

10-bit

11-bit

Fig. 5-6 The modelling of the PID-type SMC for a digitally controlled buck converter

To comply with the design equations regarding with the stability and the transient response,

the choice for system dynamic performance should be considered with the trade-off between

n and , where large of simulations have been carried out. Finally we set the bandwidth of

the SMC response f at one-fifteenth of the switching frequency sf , i.e., 15 2s nf ,

and choose the damping ratio 1. Thus the sliding parameters are determined as: 2 2 2

1 2 3 24 15 and 4 15s sK K f K K f (5.47)

The modelling of the buck converter is modelled in a hybrid model [S12] using Matlab s-

function and all the calculations are computed in fixed-point computation with 13-bit fraction

(see section 4.2.3). To meet the condition of non-limit cycle DPWM ADCN N [A7], the analog-

to-digital model has a 10-bit resolution and DPWM model has an 11-bit resolution. The

simulation results and their analysis are shown as below.

Initially the output voltage outV follows the reference refV by a slope function until steady

state. Then the load suddenly changes from 0.3A to 0.46A (R: 5Ω→3.3Ω), Fig. 5-7 shows the

transient response of the SMC at switching frequency 4MHz: output voltage (a), PWM duty

ratio (b) inductance current (c). It can be seen that the dynamic response of SMC is satisfying,

where the transient response is very fast and the undershot is small.

To illustrate the details of sliding trajectory in the SMC operation, Fig. 5-8 shows the

sliding trajectory in x1-x2-S(x) 3-D space (a) and in x1-x2 two phase plane (b). During the

operation of the slope function, the output voltage outV always tracks the refV and the sliding

surface S directs toward the equilibrium point until steady state out refV V . In steady state the

sliding trajectory is on the stable surface near the origin, and in dynamic state the equilibrium

is broken and the sliding trajectory will directs toward the new equilibrium point again.

Consequently as shown in Fig. 5-8 the sliding trajectory changes twice in two circles. In order

to clearly explain the change of the sliding trajectory during the SMC operation, the sliding

surface S is also illustrated in the time-domain. Thus the Fig. 5-9 shows the sliding trajectory

in t-x1-S(x) 3-D space (a) and in t-S(x) two phase plane (b). It can be seen when load changes

the sliding trajectory can quickly direct to the stable equilibrium.

94

2.5 2.55 2.6 2.65 2.7 2.75 2.8 2.85 2.9

x 10-4

1.4737

1.4762

1.4787

1.4812

1.4837

1.4862

1.4887

1.4912

1.4937

1.4962

1.4987

1.5012

1.5037

1.5058

Time: s / div

outp

ut

Voltage:

V /

div

transient output voltage at 4MHz


2.5 2.55 2.6 2.65 2.7 2.75 2.8 2.85 2.9

x 10-4

0.25

0.265

0.28

0.295

0.31

0.325

0.34

0.355

0.37

0.385

0.4

0.415

0.43

0.445

0.46

0.475

0.490.5

Time: S / div

Unit:

A /

div

transient inductance current at 4MHz


2.5 2.55 2.6 2.65 2.7 2.75 2.8

x 10-4

0.45

0.475

0.5

0.525

0.55

0.575

0.6

0.625

0.65

0.675

0.7

0.725

0.75

0.775

0.8

0.825

0.85

0.875

0.9

Time: s /div

PW

M d

uty

d

transient duty ratio at 4MHz


Fig. 5-7 Dynamic response of SMC when load changes from 0.3A to 0.46A (R: 5Ω→3.3Ω): output

voltage Vout (a), inductance current IL (b) and PWM duty ratio d (c) at switching frequency 4MHz

95

-0.0050.01

0.0250.04

0.055 -0.4-0.3

-0.2-0.1

00.1

0.20.3

0.4-5000

0

5000

10000

15000

20000

x2*C

x1=V

ref -V

out

S(x

)

sliding trajectory at fs=4MHz

X1=V

ref-V

out

(a)

-0.01 -0.005 0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04 0.045 0.05 0.055 0.06-0.3

-0.25

-0.2

-0.15

-0.1

-0.05

0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

x1= V

ref-V

out

x 2*C

sliding trajectory mapped onto x1-x

2 phase plane at fs=4MHz

(b)

Fig. 5-8 SMC Sliding trajectory in x1-x2-S(x) 3-D space (a) and mapped in x1-x2 two-phase plane (b) at

switching frequency 4MHz

96

01

23

45

6x 10

-4

-0.01

0

0.01

0.02

0.03

0.04

0.05

0.06

-5000

0

5000

10000

15000

20000

Time: t (s)

x1=V

ref-V

out

S(x

)

sliding trajectory at fs=4MHz

Initially, SMC operates

in a slope function,

steady

statedynamic

statesteady

state

X1=V

rev-V

out

Time: S

(a)

0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 3.25

x 10-4

-1

-0.75

-0.5

-0.25

0

0.25

0.5

0.75

1

1.25

1.5

1.75

2

2.25x 10

4

Time: t (s)

S(x

)

sliding trajectory in time-domain at fs=4MHz


in a slope function,steady

state

dynamic

statesteady

state

(b)

Fig. 5-9 SMC Sliding trajectory in time-domain: t-x1-S(x) 3-D space (a) and mapped in t-S(x) two-phase

plane (b) at4MHz switching frequency

97

2.5 2.55 2.6 2.65 2.7 2.75 2.8 2.85 2.9

x 10-4

1.4576

1.4616

1.4656

1.4696

1.4736

1.4776

1.4816

1.4856

1.4896

1.4936

1.4976

1.5016

1.5056

1.5096

Time: S

Un

it:

A/

div

transient output voltage


2.5 2.55 2.6 2.65 2.7 2.75 2.8 2.85 2.9

x 10-4

-0.03

0

0.03

0.06

0.09

0.12

0.15

0.18

0.21

0.24

0.27

0.3

0.33

0.36

0.39

0.42

0.45

0.48

0.51

0.54

Time: S

Unit:

A /

div

transient inductance current


2.5 2.55 2.6 2.65 2.7 2.75 2.8 2.85

x 10-4

0.450.475

0.50.5250.55

0.5750.6

0.6250.65

0.6750.7

0.7250.75

0.7750.8

0.8250.85

0.8750.9

0.9250.95

0.9751

1.0232

Time: S

Unit:

A /

div

transient duty ratio


Fig. 5-10 Dynamic response of SMC when load changes from 15mA to 0.46A (R: 100Ω→3.3Ω): output

voltage Vout (a), inductance current IL (b) and PWM duty ratio d (c) at switching frequency 4MHz

98

2.5 2.55 2.6 2.65 2.7 2.75 2.8 2.85 2.9

x 10-4

1.4737

1.4762

1.4787

1.4812

1.4837

1.4862

1.4887

1.4912

1.4937

1.4962

1.4987

1.5012

1.5037

1.5058

Time: S

outp

ut

Voltage V

/ d

iv

output voltage at 1MHz




2.5 2.55 2.6 2.65 2.7 2.75 2.8 2.85 2.9 2.95

x 10-4

0.425

0.45

0.475

0.5

0.525

0.55

0.575

0.6

0.625

0.65

0.675

0.7

0.725

0.75

0.775

0.8

0.825

Time: (s)

PW

M d

uty

(d)

duty ration at fs=1MHz



(b) PWM duty ratio d

0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 3.25

x 10-4

-1

-0.75

-0.5

-0.25

0

0.25

0.5

0.75

1

1.25

1.5

1.75

2

2.25x 10

4

Time: t (s)

S(x

)





in a slope function,steady

state

dynamic

statesteady

state

(c) Sliding trajectory S

Fig. 5-11 Comparison results of Vout, duty ratio d and sliding trajectory S for SMC when load changes from

15mA to 0.46A (R: 100Ω→3.3Ω) at 1MHz, 2MHz and 4MHz respectively

99

In order to validate the disturbance rejection in larger range of variation, Fig. 5-10 shows

the dynamic results when the load changes from 15mA to 0.46A (R: 100Ω→3.3Ω). It can be

seen that the SMC can well regulate the output voltage even in large range of load variation.

In order to compare the SMC operation performance at different switching frequency, Fig.

5-11 shows the comparison results of outV , duty ratio d and sliding trajectory S for SMC when

load changes from 15mA to 0.46A (R:100 Ω→3.3Ω) at 1MHz, 2MHz and 4MHz respectively.

It can be seen that the dynamic response of SMC is better with increasing switching

frequency. As stated previously that higher switching frequency performs in higher dynamic

performance, and an infinite frequency directs toward an ideal SMC.

5.4 Summary

In this chapter a nonlinear DPWM-based sliding mode controller which is derived from the

conventional analog HM-based SMC, is proposed for the digitally controlled high-frequency

low-power SMPS application. Firstly a brief review of sliding mode control is given in details,

which contains the fundamental theory and existence conditions for SMC. Subsequently the

SMC is introduced to the SMPS application domain. The ideal controller in theory is

redefined to meet practical limitations. Hence the Quasi-Sliding-Mode (QSM) control is

introduced to reduce the infinite high switching. For the sake of completeness, we present the

conventional HM-based SMC and reveal its shortage in practical design. To meet the

requirement of fixed-frequency, a PWM modulator is introduced to solve the problem of

frequency variation. The relationship between the equivalent control and averaged duty

control is derived, so that the PWM-based SMC is adopted to replace HM-based SMC. Most

of the conventional HM-based SMC and recent PWM-based SMC are designed as analog

controllers in low to medium power level, where the switching frequency and control

performance are not adequate for todays SMPS. Thus we present an original implementation

of a DPWM-based SMC for a high-switching low-power frequency SMPS. An example

design of DPWM-based SMC for a buck converter is detailed. The practical design involves

system modelling, derivation of DPWM-based SMC, selection of sliding parameters,

derivation of existence and stability analysis. The time domain behaviour of the proposed

digital DPWM-based SMC is verified on a buck converter using Matlab/ simulink. The

simulation results verify the performance of proposed SMC. The FPGA implementation will

be presented in chapter 6.

Chapter 6 Experimental Verification in FPGA

After the design of the proposed DPWMs (two kinds of Hybrid DPWM in Chapter3) and

the proposed digital control algorithms (PID, RST in Chapter4 and SMC in Chapter5), the

next step is to implement the proposed digital control system on a test platform and verify its

performances. Currently due to the absence of IC fabrication in the time of this work, all

experimental tests are implemented on a Virtex-II FPGA board. The analog-to-digital

conversion is performed using a discrete A/D chip (AD9203), while the DPWM and control

algorithms are implemented in FPGA.

Since the digital controller is applied to the high-frequency SMPS, the computation speed

and the capacity to process complex algorithms are the main concerns for the digital processor

in practical implementation. Compared to traditional digital processors such as DSP and

MCU, FPGA has very fast computation speed and more flexibility in word length for

algorithm calculation. In addition the most outstanding feature of FPGA is the advantage of

parallel calculation, i.e. the Concurrent Statements in Hardware Description Language (HDL).

Thus many components of a circuit can simultaneously operate and concurrently drive distinct

signals to new values. This would dramatically reduce the computation time when the control

algorithm is complicated. The proposed advanced control algorithms are initially verified

through FPGA implementation, but all developments are ready to be used for a final digital IC

design. It should be noted that the current discrete FPGA-based approach versus the final

monolithic IC approach falls into the limitation in the practical switching frequency that can

be achieved, less than 10MHz compared to 100MHz at least.

In this chapter, the hardware implementation of the digitally controlled buck converter

system and experimental results will be illustrated. The operation condition and parameters of

the buck converter are the same as those used in the simulation shown in Section 4.2 and 5.3.

6.1 Brief Introduction to FPGA “A field programmable gate array (FPGA) is a general purpose integrated circuit that is

programmed by the designer rather than the device manufacturer”. FPGA can be viewed as

the newer and more advanced form of the earlier complex programmable logic devices

(CPLDs) which dates back to late 1980s. One of the fundamental advantage of FPGA over

100

DSP and other microprocessors is the freedom of operation in concurrence. Since different

parts of the FPGA can be configured to perform independent functions simultaneously, its

performance is just not tied to clock rate as in DSPs. Once hardware is designed at the system

level, logic cell or Register-Transfer-Level (RTL) is performed using hardware design

language (VHDL or Verilog), and the synthesis software generates the configuration program

file. This program file also called bitstream is stored in a PROM (or other non-volatile

memory) and upon application of power is written into the FPGA.

6.1.1 VHDL And Design Flow

Very-high-speed-integrated-circuits Hardware Description Language (VHDL) and Verilog

are the two languages, which allow designers to specify digital logic. VHDL allows a

designer to work at various levels of abstraction. The design abstraction hierarchy (shown in

Fig. 6-1) gives increasing abstraction in the direction of the arrow according to Gajski-Kuhn

Y chart [D6]. The Y chart has three levels of design description: Behavioral, Structural and

Physical. Each level has many levels of abstraction. The design process is represented by

step-wise refinement in all three levels from outer levels towards the centre. It is possible to

represent synthesis, design verification and analysis tools for VLSI design on the Y chart. The

digital design is generally done in the behavioral and structural domain and does not start at

physical level, which however outputs the final chip layout.

Behavioral

System

Register-TranferLogic

Structural

Physical / Geometry

Architectural

Algorithmic

Functional Block

Logic

Circuit

TransistorGates, Flip-Flops

ALUs, Registers

BUS, Subsystem

Processor , CPU

Polygons

Cell, Modules plans

Marcos, Floor plans

Clusters

Physical partitions , Chips

Algorithms

Tranfer-Function

© IEEE [Gajski1983]

Fig. 6-1 Gajski-kuhn Y chart

101

Design starts with the functional designing at the Behavioral level, and then goes to system

level, algorithmic and the RT level. After top-bottom partitioning, a bottom-up approach is

necessary to describe the design flows at the RT levels, then algorithmic and then system

level. Once the design is written in HDL or drawn through a schematic editor, it is

synthesized by logic synthesizer, which transforms it into a net-list. Synthesis is done using

commercial synthesis tools (XST for Xilinx). During synthesis the HDL code is translated (or

compiled) to the corresponding structural elements. At this point a functional simulation is

generally carried out, which checks the correctness of the HDL description. ModelSim Xilinx

Edition-II is used as the verification software in this case. The generated net-list contains

information of the various logic gates and their interconnections in the structural level.

Next step is the Design Implementation stage. Here implementation tools physically maps

the gates and logics from the net-list into the FPGA. At this time the design path reaches the

physical level. Implementation consists of three stages: Mapping, Place and Route. The

Mapping tool fits the net-list gates into groups that fit into the LUTs (Look-Up Table) inside

the CLBs (Configurable Logic Block). Then the Place and Route tool assigns these gates to

specific CLBs and interconnect them through making and breaking of the appropriate gate

arrays. The choice of interconnection and CLBs are guided by the need to meet various

optimization targets. Optimization may be done for area/real estate of the design or

speed/fastness of the design. At this stage various design verifications can be done through

timing simulations based on the post-layout timing net-list, which contains various gate-to-

gate, gate-to-pad and pad-to-pad timing information extracted after placing and routing teps.

Such timing simulation gives more accurate results than the previous functional simulation.

After implementation, the bitstream which contains the gate and placing information is

generated and downloaded to the physical FPGA chip. In the Gajski-kuhn Y chart the final

stage of abstraction is reached at this point and design is complete. The in-circuit verification

can be carried out at this point.

Fig. 6-2 shows the design flow chart of the digital controller in the Xilinx FPGA

implementation, where the overall design is built on a top-down approach. The design flow

includes four parts: Design entry, Synthesis, Implementation and Verification. The design is

performed using Xilinx ISE 9.2i tool and verified on Virtex-II Pro FPGA board.

102

Idea/Plan/

Budget

VHDL Code /Schematic /

IP CoreSyntax Check

FunctionalSimulation

Synthesize to Generate NetlistTranslate

Mapping

Place & Route

Design Entry

Synthesis

TimingSilmulation

Generate bitsream File

DownloadProgramming

Implementation

Verification

UserConstraints

Fig. 6-2 Steps in VHDL based Xilinx ISE/Modelsim design-flow

6.1.2 Xilinx Virtex-II Pro FPGA Family

The FPGA device used is XC2VP30 from Virtex-II Pro family FPGA of Xilinx [X3]. The

package used is ft896 with speed grade -7. Xilinx Synthesis Tool (ISE9.2i) and VHDL are

used as synthesis tool and programming language respectively. ModelSim Xilinx Edition-II

from Model Technologies is used as the simulation tool. A Xilinx University Program Virtex-

II Pro Development System Board (Xilinx XUP Virtex II Pro) is used. XC2VP30 has 3

million gates, 136 dedicated 18x18-bit multipliers, 8 DCMs, 644 user I/Os. In this work, we

employ an external 32MHz clock and use inside DCMs to obtain several clocks for different

blocks, such as A/D converter (16MHz), algorithm computation (128MHz), DPWM counter-

comparator (32MHz, 64MHz and 128MHz with their four phase-shift 0o, 90o, 180o and 270o,

etc.). Compared with DSP which is tied by the unique rigid clock, FPGA facilitates the

configuration of clock resource and offers more flexible clock choices for diverse function

blocks. The maximum speed of signal process inside Virtex-II Pro family FPGA can reach

400MHz, and interface I/Os signal transfer speed can reach as high as 200MHz. The number

of I/Os can be a determining factor for device or family of FPGA suitable for any particular

application. Table 6-1 summaries the resource of Virtex-II Pro Family Members, where the

shadow area is XC2VP30 in this case.

6.2 Test Platform Description To demonstrate the functionality of the proposed digitally-controlled prototype buck

converter, a test platform is built and set up as shown in Fig. 6-3. A corresponding system

block diagram is shown in Fig. 6-4. The test platform consists of three boards.

103

Table 6-1: Virtex-II Pro/Prox Family Members

Device RocketIO Transceiver

PowerPC Processor Logic cells

CLBs (1=4 Slices=max 128bits)

SlicesMax Distr RAM (kb)

18x18 BitMultiplier

Block SelectRAM+

Max Block RAM (kb)

18 kbBlocks

DCMMaximum

User I/O Pads

XC2VP2 4 0 3,168 1,408 44 12 216 4 204

XC2VP4 4 1 6,768 3,008 94 28 504 4 308

XC2VP7 8 1 11,088 4,928 154 44 792 4 396

XC2VP20 8 2 20,880 9,280 290 88 1584 8 564

XC2VPX20 8 1 22,032 9,792 306 88 1584 8 552

XC2VP30 8 2 30,816 13,696 428 136 2448 8 644

XC2VP40 0 or 8 or12 2 43,632 19,392 606 192 3456 8 804

XC2VP50 0 or 16 2 53,136 23,616 738 232 4176 8 852

XC2VP70 16 or 20 2 74,448 33,088 1,034 328 5904 8 996

XC2VPX70 20 2 74,448 33,088 1,034 308 5544 8 992

XC2VP100 0 or 20 2 99,216 44,096 1,378 444 7992 12 1,164

12

28

44

88

88

136

192

232

328

308

444 1). A FPGA board with USB controller is used to connect to a host PC, which runs

software Xilinx ISE9.2i that can program on-line the digital controller. The implementation of

DPWM and digital algorithm are designed in VHDL and schematic editor using Xilinx ISE

tool (design, function simulation, time simulation, mapping, placement and route). The USB

connector is used to download the final bitstream (routed circuits) to FPGA.

2). A voltage feedback synchronous buck converter is fabricated with a dynamic load

trigger circuit. The elements of buck converter are: 6.8L µH= , , 22C µ= F 5R = Ω ,

, and switching frequency 3.0inV V= 1.5outV = V sf is set up to 4MHz. The dynamic load

trigger circuit is used to test the transient response of the buck.

3). A third board that serves as the feedback voltage sampling contains an A/D component

AD9203, which takes analog-to-digital sample at 16MHz rate and the sampling clock is

offered by DCM of FPGA.

The detailed functionalities of these three boards will be discussed in the following sections.

6.2.1 FPGA Board

Fig. 6-5 (a) shows the FPGA development board, where XCV2P30 FPGA supports the

DPWM (Chapter 3), and digital control algorithms PID, RST (Chapter 4) and SMC (Chapter

5). The FPGA board communicates with a host PC through an USB which downloads the

final synthesized circuit. The software Xilinx ISE9.2i supports the program on-line to modify

the function of the digital controller. Since the automatic synthesis, simulation, timing

analysis, and verification tools are available for FPGA implementation, it is delightful that

these well-established and automated tools can dramatically speed-up the design procedure.

104

Moreover the design can be easily moved to another target or be modified to meet new

requirements.

Except the DCM (Digital Clock Management) parts, the blocks of the proposed digital

controller (DPWMs and control-algorithms) are implemented in VHDL. Like the DLL/and

PLL functions, the DCM is provided by FPGA manufacturing as an IP Core. Recently large

numbers of research have focused on low-jitter low-skew DLL/and PLL design. The

technique of designing a similar DLL IP Core in ASIC is not a critical issue in IC design. This

issue is not discussed here. The complete design is reusable for the design of an ASIC.

Fig. 6-3 Experimental test platform

VinC(t)NMOS

L

CPMOS

Xilinx FPGA XC2VP30

Power supplies1.5V, 2.5V, 3.3V, 5V

USB Connector

PCFPGA Board

R2R1

R4R3

VoutADCBoard

V[n]

Buck Converterand Dynamic Load Borad

Vin

Fig. 6-4 Block diagram of the experimental test platform

105

(a)

(b)

(c)

Fig. 6-5 Test platforms: FPGA board (a), Buck converter board (b) and A/D converter board (c)

106

6.2.2 Buck Converter And Dynamic Load Board

The Buck converter and dynamic load board is shown in Fig. 6-5 (b). The Buck converter

board implements the hardware of the digitally-controlled single-phase voltage regulator with

switching frequencies range of hundreds of kHz to several MHz. Currently due to the speed

limit of discrete Mosfets and drivers, the experimental tests operate up to 4MHz. The low-

voltage high-frequency Mosfet STS8C5H30L is used with high-speed driver EL7457CS. In

the future ASIC application with proper technique of integrated circuit, the switching

frequency can be greatly increased to meet the miniaturization demand.

In order to test the dynamic performance of the digital controller, an additional transient

load variation circuit is also set on the board. In the steady-state, two parallel load-lines are

connected with the buck output terminal, where each load-line consists of two 5Ω resistors in

series, resulting in the total load ( ) ( )5 5 / / 5 5 5Ω+ Ω Ω+ Ω = Ω (see Fig. 6-4 and Fig. 6-5 (b)).

When the system switches into transient state, a 5Ω resistor of the first and/or second load-

line will be cut off and results in a final load of 5Ω//5Ω=2.5Ω or 5Ω//(5Ω+5 Ω)=3.3Ω. Table

6-2 summarizes the parameters of the voltage regulator (Appendix E shows the detailed

circuit schematic).

Table 6-2: Prototype buck voltage regulator parameters

N Number of phase 1

inV Input voltage 3.0V

refV Reference voltage 1.5V

maxI Max. load current 1.2A

sf Switching frequency 1MHz ~ 4MHz L TAIYO YUDEN Inductance CBC2518T4R7M (4.7µH)

Lr Inductance ESR (DC) 8mΩ C TAIYO YUDEN Capacitor JMK212BJ226MG-T (22µF)

Cr Capacitor ESR (1kHz) 10mΩ R TYCO Resistor 5Ω

High side MOS− ST Microchip Mosfet STS8C5H30L (P-Channel) Low side MOS− ST Microchip Mosfet STS8C5H30L (N-Channel)

Hr δ High-side switch on-resistance 0.018Ω ~ 0.055Ω

Lr δ Low-side switch on-resistance 0.020Ω ~ 0.075Ω MOS Driver Intersil Mosfet driver EL7457

107

6.2.3 A/D Converter Board

As discussed in section 2.1.1, the resolution of the A/D converter should be fine enough

such that the output voltage error of power converter tightly falls within the allowed voltage

range. Thus a high resolution and high speed ADC topology is desirable for high performance

SMPS. However high resolution and fast sampling rate will consume energy and deteriorate

the SMPS efficiency. In order to reduce the power consumption, a window ADC topology is

conceived (section 2.2), which has high resolution only in a small window around reference

voltage . The advantage of the window ADC is to reduce the quantization window to the

possible variation range, which is usually tens of milli-volts centered around the reference

voltage. As a consequent, the window ADC has fine resolution with low energy consumption.

refV

As the preliminary research work for the project, the experiment here is only dedicated to

validate the functional performance of digital controller. Strategy looking for evaluation of

energy consumption still relies on the subsequent IC fabrication. Thus the A/D conversion

here is implemented using an A/D component (AD9203) shown in Fig. 6-5 (c). Table 6-3 lists

the configuration of AD converter board and Appendix F shows the detailed circuit schematic.

The A/D device is probably a high energy consuming block in the system, and remains an

effort-consuming task in ASIC implementation. This issue is not discussed here.

Table 6-3: AD converter configuration parameters

A/D Converter Analog Device AD9203 V∆ Sampling voltage range 0V~2V

NADC ADC resolution 10-bit

samplef Sampling frequency 16MHz

_d outt Data output delay 5ns

DDV Power supply 3.3V

6.3 Experimental Results The proposed digital control system consists of a synchronous Buck converter, a discrete

ADC and a FPGA-based digital controller shown in Fig. 6-6. Fig. 6-7 shows the RTL level

schematic map of the FPGA-based digital controller implementation. Due to page limit, the

details of VHDL codes and logic schemas of the digital controller are not shown here, and

Appendix G only shows the top-level architecture of the digital controller.

The experimental results for open-loop operation are shown in section 6.3.1, where the 11-

bit Hybrid dither DPWM (Chapter 3) operates up to 2MHz and the 11-bit Hybrid ∆-Σ DPWM

108

(Chapter 3) operates up to 4MHz. The experimental results for closed-loop operation are

shown in section 6.3.2, where the digital PID, RST and Tri-mode (Chapter 4) and SMC

(Chapter 5) algorithms operate at switching frequency up to 4MHz with 11-bit Hybrid ∆-Σ

DPWM. The experimental results of closed-loop operation below 4 MHz (1MHz and 2MHz)

are posted in Appendix F to Appendix I.

A/Dc1(t) c2(t) Vout [9:0]

VinPMOS

NMOS

L 4.7µHC

22µF

R 5Ω

3.3Ω

3.0V AD 9203

Mosfetdriver

iload0.3A

0.46A

Softmethod

d[10:0]Control

lawe[9:0]

x

Vref[9:0]digital

algorithm

-+

NCore

Vref digital ramp

4-bit DCMPhase-shift

Dead-time

4

c(t)

Sc11-bit

Hybrid DPWM

Buck converter ADC

FPGA-based digital controller

NCore+4

CounterNCore-bit

Fig. 6-6 Diagram block of the digital controller of a synchronous buck converter

Slope_function Clk_count

AD_filter

DCM_Clk

System_on_off

PID_control

RST_control

Dynamic_load

Output_PWM

Output_LED

REST_system

CLK_32M

button_startbutton _stop

data_AD[9:0]

button _CANCELbutton_SW1button_SW2

Switch2

Switch1

PWM2

PWM1

LED_verf_slopeLED_system_onLED_power_charge

LED_clk_ready

Clk_AD

Control_flag

Fig. 6-7 The schematic map of the FPGA-based digital controller synthesized in RTL level

109

6.3.1 Open-Loop Test for DPWM

In this section, the experimental results of open-loop test for DPWM (Hybrid dither and

Hybrid ∆-Σ DPWM) are illustrated.

As detailed in Chapter 3, both of two kinds of Hybrid DPWM consist of soft method

(digital dither approach or MASH ∆-Σ modulator) and hardware Core DPWM (counter-

comparator and segmented DCM phase-shift block). The Hybrid dither DPWM (shown in Fig.

3-11) operates up to 2MHz in this case, where the digital dithering is mathematic way to deal

with the LSB [2:0], and the hardware Core DPWM is to implement the HSB [10:3]. The

Hybrid ∆-Σ DPWM (shown in Fig. 3-23) operates up to 4MHz here, where the MASH ∆-Σ

modulator is the soft way to deal with the LSB [4:0], and the hardware Core DPWM is to

implement the HSB [10:5]. The operation conditions of the two DPWM architectures are

illustrated in Table 3-5. The following pages will present the operation waveforms of the

DPWM in FPGA implementation.

To demonstrate the functionality of the four-phase-shift DCM (shown in Fig. 3-6), Fig. 6-8

shows the experimental waveforms verified in FPGA. It can be seen the experimental results

validate the previous timing-simulation (shown in Fig. 3-13).

Fig. 6-8 Experimental waveforms of four-phase-shift DCM at 16MHz

Fig. 6-9 shows the waveforms and spectrums of Hybrid dither DPWM in open-loop test

(2MHz switching frequency and duty ratio 50%), where (a) shows the PWM gate signals of

110

high-side (P-channel) Mosfet and low-side (N-channel) Mosfet, and (b) shows the high-side

(P-channel) Mosfet gate signal and output voltage . From the view of spectrums of PWM

gate signals and voltage , the performance of Hybrid dither DPWM is quite satisfying. outV

outV

(a)

(b)

Fig. 6-9 Waveforms and spectrums of Hybrid dither DPWM in open-loop test (2MHz and duty ratio 50%):

PWM gate signals of high-side and low-side mosfets (a), and high-side PWM signal and output voltage (b).

Fig. 6-10 shows the similar waveforms and spectrums, but using the Hybrid ∆-Σ DPWM in

open-loop test (4MHz switching frequency and duty ratio 50%), where (a) shows the PWM

gate signals of Mosfets, and (b) shows the high-side (P-channel) Mosfet gate signal and

111

output voltage . From the view of spectrums of voltage , the noise produced by

Hybrid ∆-Σ DPWM is less than that of Hybrid dither DPWM. outV outV

(a)

(a)

Fig. 6-10 Waveforms and spectrums of Hybrid ∆-Σ DPWM in open-loop test (4MHz and duty ratio 50%):

PWM gate signals of high-side and low-side mosfets (a), and high-side PWM signal and output voltage (b).

6.3.2 Closed-loop Operation

The experimental results of closed-loop operation of the digital PID, RST, Tri-mode and

Sliding-mode controllers are detailed in following pages. The buck converter operates at

switching frequency 4sf MHz= with the Hybrid ∆-Σ DPWM.

112

A. PID and RST Controller Operation

Fig. 6-11 shows the steady-state output voltage and the corresponding PWM gate

signals (high-side Pmos and low-side Nmos) of PID operation. Fig. 6-12 shows the similar

ones, where the results are generated using RST controller. It can be seen in steady-state the

PID controller with simple algorithm computation can obtain satisfying output voltage as well

as RST does. The spectrum waveforms of PWM signals and output voltage show that there is

no oscillation in closed-loop operation.

outV

(a)

(b)

Fig. 6-11 Experimental waveforms of PID controller in steady-state:

PWM gate signals of high-side and low-side mosfets (a), high-side PWM signal and output voltage (b).

113

(a)

(b)

Fig. 6-12 Experimental waveforms of RST controller in steady-state:

PWM gate signals of high-side and low-side mosfets (a), high-side PWM signal and output voltage (b).

Fig. 6-13 shows the steady-state characteristic of PID controller, of which (a) shows the

comparison between reference voltage and output voltage in from 0.15V to 1.90V,

and (b) pictures the output voltage linearity refV outV

ref out refV V V− . It illustrates that the low-cost PID

controller maintains a stable output voltage quite well.

114

0

0.25

0.5

0.75

1

1.25

1.5

1.75

2

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

Vout Reference (V)

Vout

Mea

sure

men

t (V

)ideal

measurement

(a)

33.453.9

4.354.8

5.255.7

6.156.6

7.057.5

7.958.4

8.85

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2Vout Reference (V)

∆Vou

t Er

ror (

%)

(b)

Fig. 6-13 Steady-state characteristics of PID controller: static error of output voltage (a) and linearity (b).

When the load suddenly changes from 0.3A to 0.46A (R: 5Ω→3.3Ω), the output voltage

transient responses of PID and RST controllers are respectively illustrated in Fig. 6-14 (a)

and (b). The PID controller takes 82µs to recover an undershoot (28mV) to the steady-state.

By contrast, the RST controller has a faster response (14µs) and smaller undershoot (20mV).

It can be seen that the RST controller has better dynamic performances than PID controller.

outV

115

(a)

(b)

Fig. 6-14 Transient output voltage of PID controller (a) and RST controller (b) when load goes from

0.3A to 0.46A (R: 5Ω→3.3Ω)

B. Tri-Mode Controller Operation

Under the same loading conditions from 0.3A to 0.46A (R: 5Ω→3.3Ω), Fig. 6-15 shows the

output voltage transient response using the tri-mode controller. It can be seen that when

the buck converter is in steady-state or stand-by mode, the PID controller maintains the

deserved output voltage. While in transient-mode, the RST robust controller can quickly

outV

116

regulate the dynamic output. It can be seen that the tri-mode controller offers the dynamic

performances of RST control but at the cost of a PID controller. Although the output voltage

suffers a small overshoot when the controller switches from transient mode (RST) to steady-

state mode (PID), this is acceptable compared to a PID controller alone (see Fig. 6-14 (a)).

These results show that the transient response time is small and the offset on the output

voltage is also less than 20mV, i.e. 1.4% of the output voltage (1.5V).

(a)

(b)

Fig. 6-15 Output voltage of Tri-mode controller when load varies from 0.3A to 0.46A (a) and 0.46 to 0.3A (b)

117

C. SMC Operation

Fig. 6-16 shows the steady-state output voltage and the corresponding PWM gate signals

(high-side and low-side Mosfets) of SMC operation. The spectrum waveforms of PWM

signals and output voltage show that there is no oscillation in closed-loop operation.

(a)

(b)

Fig. 6-16 Measured waveforms for CMS in steady-state: high-side (P-channel) and low-side (N-channel)

PWM signals (a), high-side PWM signal and output voltage (b).

When the load suddenly changes from 0.3A to 0.46A (R: 5Ω→3.3Ω), the output voltage

transient responses is illustrated in Fig. 6-17. It can be seen that the SMC has good

dynamic performances with short response time and low voltage overshoot/undershoot. outV

118

Fig. 6-17 Transient output voltage of SMC when load varies from 0.3A to 0.46A (R: 5Ω→3.3Ω).

6.4 Summary In this Chapter, the FPGA-based implementations of digital controllers on a discrete buck

converter are detailed. The experimental results of open-loop and closed-loop operations are

illustrated, which includes the experimental test of Hybrid dither DPWM and Hybrid ∆-Σ

DPWM in open-loop, and includes the operation results of PID, RST and SMC controllers.

Also introduce the result of Tri-mode controller.

From the above experimental results, the performance comparison of PID, RST and SMC

controllers can be drawn in Table 6-4. It is clear that both RST and SMC have better

performance than PID. In addition, the FPGA resources consumption of the three controllers

is summarized in Table 6-5. As described in equation (4.22), (4.23) and (5.34), the SMC has

the simplest calculation architecture and requires the least FPGA resource among three

controllers. That means the energy consumption will be least under the same manufacturing

process in future ASIC application.

The fast transient response, good configurability, high linearity and noise immunity, make

the proposed digital controllers attractive candidates for high-frequency and low-power SMPS.

Table 6-4 Performance comparison of PID, RST and SMC

Controller Response time Undershoot voltage Performance Computaion architecture

PID Long (82µs) Large (28mV) Medium Medium (5 Multipliers)

RST Fast (14µs) Small (20.4mV) Good Complicated (9 Multipliers)

SMC Fast (22.5µs) Small (19.8mV) Good Simple (3 Multipliers)

119

Table 6-5 FPGA Utilization for PID, RST and SMC Controllers (Xilinx Virtex-II Pro XC2VP30) Logic Utilization Controller Used Available Utilization

Number of Slice Flip-Flops PID RST SMC

771 1139 593

27,392

2.8% 4.16% 2.16%

Number of 4-input LUTs PID RST SMC

583 853 426

27,392

2.1% 3.11% 1.56%

Logic Distribution

Number of occupied Slice PID RST SMC

498 685 402

13,696

3.64% 5%

2.94% Number of Slice containing only related logic PID

RST SMC

498 685 402

Number of Slice containing unrelated logic PID RST SMC

0 0 0

Total Number of 4-input LUTs PID RST SMC

612 882 455

27,392

2.2% 3.2%

1.66% Number used as logic PID

RST SMC

583 853 426

Number used as a route-thru PID RST SMC

23 23 23

Number used as a Shift registers PID RST SMC

6 6 6

Number of bonded IOBs PID RST SMC

26 26 26

556

4.67% 4.67% 4.67%

IOB Flip-Flops PID RST SMC

5 6 7

Number of PPC405s PID RST SMC

0 0 0

2

0% 0% 0%

Number of MULT18x18s PID RST SMC

10 18 6

136

7.35% 13.24% 4.41%

Number of GCLKs PID RST SMC

4 4 4

16

25% 25% 25%

Number of DCMs PID RST SMC

2 2 2

8

25% 25% 25%

Number of GTs PID RST SMC

0 0 0

8

0% 0% 0%

120

Chapter 7 Conclusion and Perspective

Digital control of high-frequency low-power switching-mode power converter has received

significant research attention. Potential advantages include programmability and flexibility,

improved system interface, reduced design time, scalability and cost advantages of standard

digital CMOS process, as well as the ability to implement more sophisticated system control

and management techniques. While most of the advantages of the digital control have been

recognized and incorporated in high complexity applications that operate at low switching-

frequency and high-power level, high switching-frequency and low-power portable systems

such as phones, PDAs and music/video players are still mainly designed with analog PWM

control inside the voltage regulator blocks. It should be noted that broader acceptance of

digital techniques in low-power DC-DC applications is still hampered by practical problems

of the combination of cost issues, trade-off of performances and power consumption. The

research interest of the thesis is to explore practical ways of incorporating advantages of

digital control in practical realizations, which is considered for the size miniaturization of

high-frequency low-power SMPS. Two main objectives of this work are to implement high-

resolution high-frequency DPWM and high-performance digital control-law for SMPS in an

FPGA-based realization.

In this concluding chapter, we summarize the major contributions of this research work and

discuss the possible future work (as ASIC design was not available at time of this research).

7.1 Contributions First of all, it enhances understanding of current practical implementation issues of high-

frequency low-power digitally controlled SMPS. Issues such as resolution requirements of

ADC and DPWM (quantization effects), limit cycles and control law were reviewed. The

thesis presents an analysis of the technical difficulties associated with implementation of

digital control at high switching frequency. The performance-related requirements of high

speed and high resolution of the key controller building blocks, including ADC, discrete-time

algorithm and DPWM, must be met together with important practical constraints of low

complexity, power consumption and cost. The analysis of these technical obstacles and

limitations of conventional DSP digital solutions leads into the main part of the thesis where

121

new hardware and software solutions are proposed to enable successful practical

implementations of high-performance digital controllers.

In continuation, the thesis presents the results of our research concerning the practical

implementation of the digital controllers, where we proposed two kinds of 11-bit Hybrid

DPWM architectures (Hybrid dither and Hybrid ∆-Σ) and two algorithm applications (Tri-

mode and Sliding-mode controllers). All work and development were carried out using digital

circuitry methods based on FPGA. The developed prototypes are investigated and supposed to

be an alternative choice for SMPS realization. This is done in the hope of providing strong

justification to how the digital controllers may be better in some aspects than the analog

controlled systems, and to prove that not only the digital control implementation is very

possible now in the area of high-frequency low-power SMPS, but also that by using the

digital control we can achieve significant improvements of switching converters

characteristics.

The main contributions of the thesis can be listed as follow:

Three types of window-ADC and six kinds of DPWM methods are reviewed in detail for

their application in high-frequency low-power integrated SMPS. Furthermore two comparison

studies are carried out respectively for ADC and DPWM design techniques.

A 11-bit Hybrid dither DPWM taking the combination soft method (digital dither

approach) and hardware (segmented DCM phase-shift) is proposed, which dramatically

alleviates the tight requirement of high-frequency clock.

Another 11-bit Hybrid ∆-Σ DPWM based on the noise-shaping technology is proposed,

where the multi-stage ∆-Σ modular (2-cascade first-order) is the first time adopted in DPWM.

It increases the DPWM resolution while keeps clock frequency low simultaneously.

A robust RST controller is proposed, which has better dynamic behavior than the

classical PID controller but the same robust performance.

Based on the PID and RST controller, a Tri-mode controller (stand-by, steady-state and

transient-state) is proposed for the reduction of the energy consumption in IC implementation.

A DPWM-based SMC is designed first time for digital controller in high-frequency low-

power SMPS application. Modelling, existence condition and stability analysis are completed.

All proposed DPWMs and digital control algorithms are realized together and validated

on a FPGA-based discrete buck prototype.

122

Specially, the original contributions will be summarized below.

7.1.1 Two Efficient DPWM Architectures Design

To improve the output voltage precision and avoid limit cycling in digitally-controlled DC-

DC converters, the efficient DPWM is urgently expected to feature high-speed high-

resolution and low-power and small-area. In chapter 3, we proposed two efficient DPWM

architectures Hybrid dither DPWM and Hybrid ∆-Σ DPWM.

The 11-bit Hybrid dither DPWM consists of a 3-bit digital dithering approach, 4-bit

segmented DCM phase-shift modulator and a 4-bit counter-comparator. Where 4-bit d[10:7]

are achieved through the counter-comparator, 4-bit d[6:3] are obtained from the segmented

DCM phase-shift and 3-bit d[2:0] comes from digital dithering approach. The Hybrid DPWM

prototype is implemented in FPGA up to 2MHz in this case. Thus the clock requirement for

this system is merely 42 sf⋅ (32MHz) instead of 112 sf⋅ , which dramatically alleviates the

tight high-frequency clock for the digitally controlled system.

Following the analysis of minimum hardware requirements in Hybrid DPWM design,

another DPWM is developed based on the multi-bit ∆-Σ concept of Multi-stAge-noise-

SHaping (MASH) modulator. A 11-bit effective Hybrid ∆-Σ DPWM is proposed and

experimentally verified up to 4 MHz. This approach uses the noise-shaping technique to

increase DPWM resolution while consumes less power and area in higher frequency range.

Where 2-bit d[10:9] are achieved through the counter-comparator, 4-bit d[8:5] are obtained

from the segmented DCM phase-shift and 5-bit d[4:0] comes from MASH ∆-Σ approach block.

Consequently the system clock for this DPWM only required 22 sf⋅ (16MHz) instead of 112 sf⋅ , which dramatically reduce the clock frequency and can allow operation with low

power consumption.

7.1.2 Tri-Mode Controller Implementation

In chapter 4, an off-line RST controller which is based on the sensitivity functions with

respect to the modulus margin M∆ and delay margin τ∆ , is designed using Matlab/Simulink

tool box, where Fuzzy logic is used to qualify the robustness of the controller and noise

rejection properties, and Genetic algorithm is used to optimize the best combination of

parameters , 0c 0ω and 0ζ for the robust RST controller. Compared to classical PID, RST has

123

better dynamic performance but features more complicated calculation architecture, resulting

in an increase in area (as well as power consumption).

In order to improve the dynamic performance and reduce the energy consumption of

algorithm computation simultaneously, a Tri-mode controller consisting of PID and RST is

proposed. The Tri-mode digital controller addresses transient, steady-state and stand-by

modes. In order to accommodate fast dynamic response, the RST robust control-law is

adopted in transient mode. In steady-state, the PID control law is applied to minimize power

consumption and keep the output voltage accuracy. While in stand-by mode if the converter is

light-loaded, then the controller is clocked at a frequency lower than the converter switching

frequency for consideration of energy consumption. Experimental results operated at

switching frequencies up to 4MHz validate the functionality of the proposed PID, RST and

Tri-mode controllers.

7.1.3 Sliding-Mode Controller Implementation

SMPS is a nonlinear system in nature due to the switching property. One of the important

features of the DC-DC converter is related to Variable Structure Systems (VSS) characteristic.

To enhance the SMPS dynamic response, nonlinear control methods especially those with

VSS structure for switching systems are essential. Sliding-Mode-Control (SMC), a form of

the large group of VSS controller is introduced here for the digitally controlled SMPS.

In chapter 5 DPWM-based SMC is employed for high-frequency low-power SMPS. After a

brief review of sliding mode control theory, we focus the interest on the SMC application for

digitally controlled SMPS. The ideal controller in theory is redefined as a Quasi-Sliding-

Mode (QSM) controller to meet practical limitations. Based on the QSM control, we adopt the

fixed-frequency modulator to void the variable frequency limitation. The relationship between

the equivalent control and duty ratio control is derived, so that the PWM-based SMC is

adopted to replace HM-based SMC. A PID-type sliding mode is introduced to regulate the

output voltage of the buck converter. The practical design involves system modelling,

selection of sliding parameters, derivation of existence and stability analysis. Experimental

results operated at up to 4MHz validate the functionality of the proposed DPWM-based SMC.

124

7.2 Future Work Following the current work in this project, some of the possible future work can be

explored as below:

7.2.1 Stability Analysis of MASH ∆-Σ DPWM

Definitely, employing the multi-bit ∆-Σ approach that is based on the noise-shaping

technique, can increase DPWM resolution dramatically and consume less power and area in

higher frequency range. However due to the absence of standard criterion for NTF properties

that are necessary and sufficient for stable operation, it is difficult to exactly analyze the

stability of a high-order ∆-Σ modulator (see section 3.2.1). If we have standard criterions to

solve this stability problem of a high-order ∆-Σ as well as the guarantee of minimum-ripple

digital dither, the ∆-Σ modulator will be of huge potential in DPWM for digitally controlled

SMPS applications. This would need large mathematical stability analysis and extensive

simulations.

7.2.2 Observer for Output Voltage Derivation

In order to reduce the size and cost of digitally controlled SMPS, we employ a digital

observer for output voltage derivation ( ) to replace the capacitor current measurement outVi

Ci C in DPWM-based SMC (see section 5.3.2). Since DPWM-based SMC is implemented in

full digital form, it is feasible to design a software observer or a mathematic function for

to eliminate the need for hardware measurement. However the issues such as delay, accuracy

and complexity should be carefully taken into account for the observer design. More efforts

should be paid to obtain a satisfying observer for output voltage derivation.

outVi

7.2.3 Application in DCM and Other Type SMPS

Occasionally, DCM (discontinuous current mode) operation in SMPS is very necessary in

industrial application, and especially, it is urgently needed in some special electronics devices

for the stand-by operation. In DCM operation the SMPS transfer function is different from

that of CCM (continuous current mode), which requires another modelling for SMPS. In this

work all the proposed digital controllers are implemented in CCM, thus it is very interesting

to apply these digital controllers in DCM operation.

125

Besides buck converter, DC-DC SMPS also includes other types of converters, such as

Boost, Buck-Boost, Cuk and Sepic converters. Similarly it is worthwhile to investigate if their

practical implementations are as simple as that of the buck converter. The further

investigation into DCM and other types of SMPS would be valuable.

7.2.4 ASIC Implementation and A/D Converter Design

As the preliminary research work for the project, the experiment here is only dedicated to

validate the functional performance of digital controller in FPGA. But the design of the digital

controller is implemented in fully synthesizable in RTL code and ready for IC design.

Unfortunately the IC fabrication is not available in time of this work. However the ASIC

implementation of the proposed digital controller is a necessary procedure. There are several

reasons to address this point. Firstly ASIC chip enables the much higher switching frequency

operations that are impractical for discrete test bench (such as 20MHz). Secondly ASIC

implementation offers the vehicle for energy consumption measurement and comparison

between the simulation of power consumption and experimental measurement. In fact this

work has already started lately in a subsequent project, and some information about the digital

controller IC design is given in Appendix K.

As a complete digital controller, the A/D converter is indispensable. The window-A/D

technique detailed in section 2.2 probably will be employed to optimize the power

consumption. The A/D design includes not only digital CMOS technology but also analog

CMOS counterpart, which remains an effort-consuming task in the case of ASIC

implementation. Whatever the ASIC implementation is the only reasonable technology to

quantify the energy performance of digital control and lead to conclusive comments with

respects to analog-control.

126

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look-up tables for control of high-frequency DC-DC converters, IEEE, Computers in Power

Electronics, 2002, Proceedings, pp.18-22.

A2.A.Prodic2002-2 A. Prodic, D. Maksimovic, Mixed-Signal Simulation of Digitally

Controlled Switching Converters, Computers in Power Electronics, 2002. Proceedings, 2002

IEEE Workshop on, pp. 100-105.

A3.A.Prodic2001 A. Prodic, D. Maksimovis, R.W. Ericson, Design and Implementation of

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Curriculum Vita M. GUO SHUIBAO, PhD student in Power Electronics February 2009

Personal data Birth: October 1981, China Email: [email protected] Phone: 00-33-620380563 Fax: 00-33-472438530 Zip code: 69621 Address: Ampère, CNRS UMR 5005, INSA Lyon, 20 Avenue Albert Einstein, Villeurbanne, France

Education July 2006 – present: PhD in Power Electronics (Co-supervision under INSA-Lyon www.insa-lyon.fr and ShanghaiUniversity www.shu.edu.cn) Institut National des Sciences Appliquées de Lyon (INSA), Lyon, France (July 2006 – February 2007) Shanghai University, Shanghai, China (March 2007 – February 2008) Institut National des Sciences Appliquées de Lyon (INSA), Lyon, France (March 2008 – April 2009) Thesis: High Performance Digital Controller for High-Frequency Low-Power Integrated DC/DC SMPS Supervisors: Prof. ALLARD Bruno ([email protected]) and Prof. RUAN Yi ([email protected]) September 2003 – May 2006: Master in Power Electronics Shanghai University, Shanghai, China Thesis: Parameters Identification and Validation for Electronic Device IGBT Supervisor: Associate Prof. GAO Yanxia ([email protected]) September 1999 – July 2003: Bachelor in Electrical Automation Engineering Anhui University of Science and Technology (www.aust.edu.cn), Anhui, China Thesis: Intel C51+K196 Microchips Implementation in Process Control

Papers related to the doctoral project Published/and Accepted papers:

[1] S. Guo, Y. Gao, N. Li, X. Lin-Shi, B. Allard, “Study on Modeling and Simulation of Ultra-Low-Power and High-Frequency Digitally Controlled Buck Converter”, Proceedings of the International Conference on Life System Modeling and Simulation (LSMS2007), 14-17 September 2007, Shanghai, China, pp. 712-716. [2] X. Lin-Shi, F. Morel, B. Allard, D. Tournier, J.M. Rétif, S. Guo, Y. Gao, “A Digital-Controller Parameter-Tuning Approach, Application to a Switch-Mode Power Supply”, The 2007 IEEE International Symposium on Industrial Electronics, Spain, 2007, pp. 3356-3361. [3] Y. Gao, S. Guo, X. Lin-Shi, B. Allard, “Design and simulation of a digital control DC-DC switching power converter”, Journal of Shanghai University (English Edition), Vol.13, No.4, 2008. [4] X. Lin-Shi, B. Allard, S. Guo, Y. Gao, “Low-cost digital control for SMPS integration”, 5th international Conference on Integration of Power Electronics Systems, 11-13 March 2008, Germany. [5] Y. Gao, S. Guo, Y. Xu, X. Lin-Shi, B. Allard, “FPGA-Based DPWM for Digitally Controlled DC-DC High-freauency Switching Mode Power Supply”, has been accepted and to appear on The Third International Conference on Power Electronics Systems and Applications, May 2009, Hong Kong. [6] S. Guo, Y. Gao, Y. Xu, X. Lin-Shi, B. Allard, “Digital PWM Controller for High-Frequency Low-power DC-DC Switching Power Converter”, has been accepted and to appear on The IEEE 6th International Power Electronics and Motion Control Conference – (ECCE Asia), May 2009, China. [7] S. Guo, X. Lin-Shi, B. Allard, Y. Gao, “High-Resolution Digital PWM Controller for High-Frequency Low-Power SMPS”, has been accepted and to appear on The 13th International European Power Electronics Conference and Exhibition (EPE2009).

135

http://www.insa-lyon.fr/

http://www.shu.edu.cn/

http://www.aust.edu.cn/

Submitted papers:

[8] S. Guo, X. Lin-Shi, B. Allard, Y. Gao, Bo LI, “Digital PWM-Based Sliding-Mode Controller For High-Frequency Low-Power SMPS”, submitted to The IEEE 1st Energy Conversion Congress and Exposition (ECCE2009).

Project Experience present

↑ 2006

Project: High Performance Digital Controller for High-Frequency Low-Power Integrated DC/DC SMPS (PhD Thesis) Principal investigator, Lab. Ampère at INSA-Lyon, supported by STMicroelectronics. A new digital controller, which consists of high-speed high-resolution digital-PWM (DPWM) and high-performance digital algorithm, has been proposed for high-frequency low-power integrated DC-DC converters applied in portable device. Two efficient 11-bit DPWM architectures Hybrid dither and Hybrid MASH ∆-Σ are proposed to increase PWM resolution and reduce power consumption simultaneously. To improve the dynamic performance and reduce the energy consumption, a Tri-mode Controller which addresses transient, steady-state and stand-by mode operations for SMPS is proposed. To achieve the best possible transient performance, a digital DPWM-based Sliding Mode Controller is developed for the sake of the nonlinear characteristic in nature of SMPS system. All the new digital blocks have been successfully implemented up to 4MHz in a FPGA-based discrete test bench, and the ASIC implementation of the digital design is under process.

2006 ↑

2004

Project: Parameters Identification and Validation for Electronic Device IGBT (Master Thesis) Co-principal investigator, Lab. IECE at SHU, supported by Shanghai Leading Academic Discipline. A platform which includes digital oscilloscope, GPIB bus, PCI-9112 card, driver and protecting circuits for IGBT, was built to test the static and dynamic characteristics waves of IGBT. All these tests were performed via interface by C++. The driver and protecting circuits were operated by microchip ST89C52. The parameters of IGBT were identified and validated on this platform, which has significant guidance for IGBT modeling, simulation and selection of usage.

2006 ↑

2005

Project: Keyboard Design for Vector-Controlled Power Inverter (http://great.seari.com.cn/) Principal investigator as a trainee, Shanghai Great Power electric CO. ,LTD. The user’s interface keyboard of the power inverter was designed on ST19C516 microchip. The keyboard connects with DSP (TI28x) using 232-bus communication to send user’s instruction and receiving real-time data of power inverter. The design was carried out on MCU µC-51 and DSP2812 platforms.

2004 ↑

2003

Project: An Efficient Digital Controller for LED Lampion (http://shcanaan.cn.alibaba.com/) Principal investigator as a trainee, Shanghai Canaan Plastic Co.,Ltd. An efficient digital controller for LED lampion was designed to replace the analong counterpart. The digital controller is implemented by Intel 89C51 microchip with a digital interface and keyboard, which improved system reliability and extend decorative lighting modes.

Awards and Scholarships 2006-2009: French Government Scholarship, Granted by The Scientific Service of the Embassy of France in China (No. K06D20) 2007 : Excellent Student, granted by Environmental & Education Foundation of Delta Electronics Inc 2004 : Excellent Student, granted by Environmental & Education Foundation of Delta Electronics Inc

136

http://great.seari.com.cn/

http://shcanaan.cn.alibaba.com/

I

Appendix

Appendix A: Modulus Margin ∆M and Delay Margin ∆τ

Fig. A-1 shows the relation modulus margin M and phase margin ∆τ. the modulus

margin M is defined as the radius of the circle centered in 1, 0j and tangent to the

Nyquist plot of the system open-loop transfer function yyL , i.e. the minimum distance of

yyL with respect to the critical locus (-1) in the Nyquist plan. From the definition, it results

that

min 1 j

yyM L e (A.1)

Substituting equation (4.3) into (A.1),

1 1 1min

max

j

yy jyyyy

M S eSS e

(A.2)

As a consequence, the reduction (or minimization) of max

j

yyS e will imply the increase (or

maximization) of the modulus margin M .

-1 1

M Re H

Im H

Crossover

frequency

cr

Fig. A-1 Modulus, gain, and phase margin

From equation (A.2), it can be seen that the modulus margin M is equal to the inverse of

the maximum of the modulus of the output sensitivity function 1

yyS z , i.e. the inverse of the

H norm of 1

yyS z . The modulus margin is very important because [I2, I3, I4]:

• It defines the maximum admissible value for the modulus of the output sensitivity

function yyS .

• It gives a bound for the characteristics of the nonlinear and time-varying elements tolerated

in the closed-loop system (it corresponds to the circle criterion for the stability of nonlinear

systems).

II

The delay margin is the additional delay which will make the closed-loop system

unstable. It is deduced from the phase margin and can be computed as follows:

cr

(A.3)

where cr is the crossover frequency (see Fig. A-1 where the Nyquist plot intersects the unit

circle).

If the Nyquist plot intersects the unit circle at several frequencies, i

cr , characterized by the

corresponding phase margin i , then the delay margin is defined by the minimum value:

min i

i

cr

(A.4)

This situation appears systematically for systems with multiple vibration modes or with pure

time delays.

In order to ensure robustness, the modulus margin M is kept higher than 0.5 and the delay

margin must be higher than the switching period sT (to ensure that the delay induced by

controller computing time does not lead to unstable operation). Generally the typical values of

these robustness margins for a “robust” controller design are [I2, I3, I4]:

• Modulus margin: 0.5M .

• Delay margin: sT .

III

Appendix B: Small Signal and State-Space Averaging

A general method for describing a circuit which changes over a switching period is called

state-space averaging. The technique requires two sets of state equations which describe the

circuit: one set for the closed switch and another one set for the open switch. These state

equations are then averaged over the switching period. A state variable description of a

system is of the form:

T

x Ax Bv

y C x (B.1)

The state equations for a switched circuit with two resulting topologies are as follows (with

the assumption of continuous current mode):

1 1 2 2

1 2

T T

Closed Switch Open Switch

x A x B u x A x B u

y C x y C x

(B.2)

For the closed switch for the time dT and open for 1 d T , the previous equations have a

weighted average of

1 2 1 2

1 2

1 1

1T T

x A d A d x B d B d u

y C d C d x

(B.3)

Therefore, an averaged state-variable description of the system is described as in the general

form of Equation (B.1) with

1 2

1 2

1 2

1

1

1T T T

A A d A d

B B d B d

C C d C d

(B.4)

Small signal and steady-state analyses of the system are separated by assuming that the

variables are perturbed around the steady-state operating point. Namely,

x X x

d D d

u U u

(B.5)

where X, D, and U represent steady-state values, x , d and u represent small signal values.

For the steady state, 0x and the small signal values are zero. Equation (B.1) becomes 1

10

T

X A BUAX BU or

Y C A BU (B.6)

where the matrices are the weighted averages of Eq. (B.4).

IV

The small signal analysis starts by recognizing that the derivative of the steady-state

component is zero:

0x X x x x (B.7)

Substituting steady-state and small signal quantities into Eq. (B.3),

1 2 1 21 1x A D d A D d B D d B D d U u (B.8)

If the products of small signal terms x d can be neglected, and if the input is assumed to be

constant,u U , i.e. 0u , then the small signal output values

1 2 1 2 1 2

1 2 1 2

1

1T T T T

x A D A D x A A X B B U d

y C D C D x C C X d

(B.9)

V

Appendix C: State-Space Averaging for Buck Converter

State-space averaging is useful for developing transfer functions for switched circuits such

as DC-DC converters. The buck converter is used in this work. State equations for the closed

switch are developed from Fig. C-l (a), and state equations for the open switch are from Fig.

C-l (b).

Vin

LRL

R

outV

LiRiCi

CVC

CR

+

-

LRL

R

outV

LiRiCi

CVC

CR

+

-

(a) (b) Fig. C-1 Circuits for developing the state equations for the buck converter:

(a) Closed switch, (b) Open switch

Closed Switch: First the state equations for the buck converter (also for the forward converter)

are determined for the closed switch. The outermost loop of the circuit in Fig. C-l (a) has the

Kirchhoff's voltage law equation:

LL L L in

diL i R i r V

dt (C.1)

Kirchhoff's current law gives

CR L C L

dVi i i i C

dt (C.2)

Kirchhoff's voltage law around the left inner loop gives

LC C C in

diL i r V V

dt (C.3)

which gives the relation

1C CC in C

C

dV dVi C V L V

dt r dt (C.4)

Combining Equation (C.1) through (C.4) gives the state equation

1L CLL C in

C C

R r rdi Ri V V

dt R r L R r L L (C.5)

Kirchhoff's voltage law around the right inner loop gives

0C C C RV i r i R (C.6)

Combining the previous equation with Equation (C.2) gives the state equation

1CL C

C C

dV Ri V

dt C R r C R r (C.7)

Restating Equation (C.5) and (C.7) in state-variable form,

1 1 inx A x BV (C.8)

where

VI

1 1

1

, , 1

0

L C

L C C

C

C C

R r r R

i R r L R r Lx A B L

RV

C R r C R r

(C.9)

Open Switch: The filter is the same for the closed switch as for the open switch. The input to

the filter is zero when the switch is open and the low-side Mosfet is conducting. State

equation (C.1) is modified accordingly, resulting that Equation (D.5) changes as

0L CL

L C

C C

R r rdi Ri V

dt R r L R r L (C.10)

The Kirchhoff's voltage law around the right inner loop maintains the same in Eq. (C.7)

1CL C

C C

dV Ri V

dt C R r C R r (C.11)

Therefore, the matrix 2A and 2B during the “open” period are respectively:

2 1 2 , 0A A B (C.12)

Weighting the state variables over one switching period gives

1 1

2 21 1 1

in

in

x d A xd BV d

x d A x d B V d

(C.13)

Adding the previous equations and using 2 1A A and 2 0B ,

1 1 inx A x BV d (C.14)

In detailed form,

1

10

L C

L C C L

in

CC

C C

R r r R

i R r L R r L ix VL

VRV

C R r C R r

(C.15)

Equation (C.15) gives the averaged state-space description of the output filter and load of the

buck converter.

The output voltage outV , is determined from

out Cout R L C L

C

V VV Ri R i i R i

r (C.16)

Rearranging to solve for outV ,

Cout L C

C C

Rr RV i V

R r R r (C.17)

The previous output equation (C.17) is valid for both closed and open switch positions in

CCM, resulting in 1 2

T T TC C C . In state-variable form, T

outV C x (C.18)

where

LT C

CC C

iRr RC and x

VR r R r (C.19)

The steady-state output is found from Eq. (A.6)

VII

1T

out inV C A BV (C.20)

where 1 2A A A , 1B B D , and 1 2

T T TC C C . The final result of this computation results

in a steady-state output of

out inV V D (C.21)

The small signal transfer characteristic is developed from Eq. (A.9), which in the case of the

buck converter results in

inx A x BV d (C.22)

Taking the Laplace transform,

ins x s A x s BV d s (C.23)

Grouping x s ,

insI A x s BV d s (C.24)

where I is the identity matrix. Solving for x s ,

1

inx s sI A BV d s (C.25)

Expressing outV in term of x s ,

1T T

out inV s C x s C sI A BV d s (C.26)

Finally, the transfer function of output to variations in the duty ratio is expressed as

1out T

in

V sC sI A BV

d s

(C.27)

Upon substituting for the matrices in the previous equation, a lengthy evaluation process

results in the transfer function

2

ˆ ( 1)

ˆ (1 ) ( ) 1

out C in

C L C L C L

V s sR C V

s R R LC s R C R C R R C R L R R Rd s (C.28)

VIII

Appendix D: Schematic Circuit of Buck Converter

Fig. D-1 Schematic Circuit of Prototype Buck Converter

Appendix E: Schematic Circuit of A/D Converter

Fig. E-1 Schematic Circuit of Prototype A/D Converter

IX

Appendix F: Top-Level VHDL Code for Digital Controller

Three full digital controllers, PID, RST and SMC, are respectively applied in this work.

Except the algorithm part, all other parts (such as voltage reference slope function, system

multiplex clocks, digital filter of A/D values, interface button input function, dynamic load

switch, external LEDs monitoring, etc) are the same for each digital controller, i.e., these

digital controllers are very similar in VHDL architecture design.

Due to page limit, here we just take the Top-level Architecture (Components Mapping) of

Sliding-Mode Controller for an instance. The detailed HDL codes and schematic files of each

component are not illustrated here.

Top-level Architecture for Sliding-mode Controller:

---------------------------------------------------------------------------------------------------------------------------------

-- Company: AMPERE-INSA-LYON

-- Author: Shuibao GUO

-- Create Date: 17:12:51 19/03/2008

-- Design Name: Sliding_Mode_Control_4MHz

-- Module Name: Top_Level_Sliding_Mode

-- Project Name: ADC10bit_DPWM11bit_Sliding_Mode_Control_4MHz

-- Target Devices: XC2VP30 Xilinx

-- Tool versions: ISE9.2i

-- Description: Digital control for high frequency SMPS

-- Revision: V1.0

-- Revision 0.01 - File Created

-- Additional Comments:

---------------------------------------------------------------------------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

--Uncomment the following library declaration if instantiating

--any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

------------------------------------------------------------------------------

Entity test_Sliding_Mode_ADC10bit_PWM11bit is

Port ( REST_system : in STD_LOGIC; -- %system input rest

clk_32M : in STD_LOGIC; -- %system input clock

button_start : in STD_LOGIC; -- %system button „start‟

button_stop : in STD_LOGIC; -- %system button „stop‟

button_SW1 : in STD_LOGIC; -- %load change button 1 => (5Ohm to 3.3Ohm)

button_SW2 : in STD_LOGIC; -- %load change button 2 => (3.3Ohm to 2.5Ohm)

button_CANCEL : in STD_LOGIC; -- %system button „pause‟

data_AD : in STD_LOGIC_VECTOR (9 DOWNTO 0); --%ADC 10-bit

pwm1 : out STD_LOGIC; -- %Nmos

pwm2 : out STD_LOGIC;-- %Pmos

Switch1 : out STD_LOGIC;-- %load variation 1

Switch2 : out STD_LOGIC; -- %load variation 2

clk_AD : out STD_LOGIC; -- %AD sampling clock (16MHz)

LED_clk_ready : out STD_LOGIC;-- %LED indicator for DCM clock

LED_system_on : out STD_LOGIC; -- %LED indicator for power supply

LED_vref_slope : out STD_LOGIC; -- %LED indicator for Vref slope action

LED_power_charge: out STD_LOGIC -- %LED indicator for charge and discharge in buck converter

);

X

end test_ Slidng_Mode _ADC10bit_PWM11bit;

------------------------------------------------------------------------------

architecture Behavioral of test_Sliding_ADC10bit_PWM11bit is

------------------

SIGNAL REST : STD_LOGIC; --% reset

SIGNAL DCM1_RST : STD_LOGIC; --% DCM1 reset

SIGNAL DCM2_RST_TEMP : STD_LOGIC; --% DCM2 temporary reset

SIGNAL DCM2_RST : STD_LOGIC; --% DCM2 reset

SIGNAL DCM3_RST : STD_LOGIC; --% DCM3 temporary reset

SIGNAL DCM3_RST_TEMP : STD_LOGIC; --% DCM3 reset

SIGNAL DCM4_RST : STD_LOGIC; --% DCM4 temporary reset

SIGNAL DCM4_RST_TEMP : STD_LOGIC; --% DCM4 reset

SIGNAL LOCKED_OUT1 : STD_LOGIC; --% DCM1 output locked




SIGNAL clk_16M : STD_LOGIC; --%16MHz




SIGNAL CLK0_temp : STD_LOGIC; --%CLK 0 degree




SIGNAL Clk_16M_Sys : STD_LOGIC; --%System CLK 16MHz




SIGNAL High_Volage : STD_LOGIC; --%VCC=3.3V

SIGNAL Low_Volage : STD_LOGIC; --%GND=0V

SIGNAL sc_select : STD_LOGIC; --%sc from DCM

SIGNAL system_on : STD_LOGIC; --%system „on‟ indicator

SIGNAL power_on : STD_LOGIC; --%charge „on‟ indicator for buck converter

SIGNAL operate_pwm : STD_LOGIC; --% open-loop or closed-loop test flag

SIGNAL pwm_inc : STD_LOGIC; --% increase pwm duty ratio in open-loop

SIGNAL pwm_dec : STD_LOGIC; --% descrease pwm duty ratio in open-loop

SIGNAL vref_flag : STD_LOGIC; --% flag in slope function for Vref

SIGNAL power_flag : STD_LOGIC; --% LED „on‟ when charge

SIGNAL Vref_voltage : STD_LOGIC_vector(9 downto 0);--%Vref in 10-bit

SIGNAL pwm_duty : STD_LOGIC_vector(10 downto 0); --%DPWM duty in 11-bit

SIGNAL pwm_core_duty : STD_LOGIC_vector(5 downto 0); --%DPWM hardware duty in 6-bit

SIGNAL pwm_count : STD_LOGIC_vector(1 downto 0); --%2-bit counter comparator in DPWM

SIGNAL pwm_seg_dcm : STD_LOGIC_vector(3 downto 0);-- %4-bit segmented DCM in DPWM

SIGNAL load_switch : std_logic;--%flag for transient load

SIGNAL data_average : STD_LOGIC_vector(9 downto 0);-- filter of ADC data

------------------

component DPWM128M_Application is --%generate system clocks 16M, 32M, 64M and 128M

port(clk_IN_32M : in std_logic;

REST_in : in std_logic;

LOCKED : out std_logic;

clk_AD_16M : out std_logic;

CLK_SYS_16M : out std_logic



sc : out std_logic CLK_SYS_128M : out std_logic

);

XI

end component;

------------------

component CLK_ACCOUNT is --%PWM 2-bit counter

Port ( clk : in STD_LOGIC;

rest : in STD_LOGIC;

sc : in STD_LOGIC;

E : in STD_LOGIC;

clk_account: out STD_LOGIC_vector(1 downto 0)

);

end component;

------------------

COMPONENT Scan_key_START_STOP is --% system button deal

Port ( rest : in STD_LOGIC;

C lk : in STD_LOGIC;

button_stop : in STD_LOGIC;

button_start : in STD_LOGIC;

system_status : out STD_LOGIC

);

end COMPONENT;

------------------

COMPONENT PWM_out_without_dead_time is --% output DPWM

Port ( rest: in STD_LOGIC;

clk : in STD_LOGIC;

E : in STD_LOGIC;

clk_account : in STD_LOGIC_VECTOR(1 downto 0);

pwm_value : in STD_LOGIC_VECTOR(1 downto 0);

power_flag : out STD_LOGIC;

pwm1 : out STD_LOGIC;

pwm2 : out STD_LOGIC;

power_on : out STD_LOGIC

);

end COMPONENT;

------------------

COMPONENT Vref_Slope_Function is --%slope function for Vref


clk : in STD_LOGIC;

E : in STD_LOGIC;

Vref_flag : out STD_LOGIC;

Vref : out STD_LOGIC_VECTOR (9 downto 0));

end COMPONENT;

------------------

COMPONENT Algorithm_sliding is --%Sliding Mode Control Algorithm

port( rest : in std_logic;--system Rest

--% clk : in std_logic;--clock input is 32MHz --%calculation clock can be changed one of three

--% clk : in std_logic;--clock input is 64MHz

clk : in std_logic;--clock input is 128MHz

E : in std_logic;--system on

load_change : in std_logic;--transient load

clk_account : in std_logic_vector(4 downto 0);

Vref_given : in std_logic_vector(9 downto 0);

din : in std_logic_vector(9 downto 0);

pwm_value : out STD_LOGIC_VECTOR(4 downto 0)

);

end COMPONENT;

------------------ COMPONENT Output_LED is --% LED indicators


XII

clk : in STD_LOGIC;

E : in STD_LOGIC;

power_on : in STD_LOGIC;

clk_LOCKED : in STD_LOGIC;

slope_flag : in STD_LOGIC;

LED_clk_ready : out STD_LOGIC;

LED_system_on : out STD_LOGIC;

LED_vref_slope : out STD_LOGIC;

LED_power_charge : out STD_LOGIC

);

end COMPONENT;

------------------

COMPONENT Deal_key_Switch is --% system buttons deal


clk : in STD_LOGIC;

E : in STD_LOGIC;

button_SW1 : in STD_LOGIC;

button_SW2 : in STD_LOGIC;

button_CANCEL : in STD_LOGIC;

load_transient : out std_logic;--transient load

SW1 : out STD_LOGIC;

SW2 : out STD_LOGIC

);

end COMPONENT ;

------------------

COMPONENT AD_Filter is --%ADC filter

Port ( clk : in STD_LOGIC;

rest : in STD_LOGIC;

data_in : in STD_LOGIC_VECTOR (9 downto 0);

data_out : out STD_LOGIC_VECTOR (9 downto 0)

);

end COMPONENT ;

--====================================================================

begin

---------------------------------------

High_Volage<='1';

Low_Volage<='0';

-----------------------------------------

Inst_Clocking:DPWM128M_Application PORT MAP( --%inst DCM block

clk_IN_32M => clk_32M,

REST_in=> REST_system,

clk_AD_16M=>clk_AD,

sc=>sc_select,

LOCKED=>LOCKED_OUT3,

clk_SYS_128M=>clk_128M_Sys,

clk_SYS_64M=>clk_64M_Sys

clk_SYS_32M=>clk_32M_Sys,

clk_SYS_16M=>clk_16M_Sys

);

-----------------------------------------

Inst_clk_count: CLK_ACCOUNT PORT MAP(--%inst counter comparator

clk => clk_128M_Sys,

rest =>REST_system,

E => system_on,

sc=>sc_select, clk_account => pwm_count

);

XIII

------------------------------------------%Scan Up and Down key to Start or Close system

Inst_System_ON_OFF: Scan_key_START_STOP Port MAP(


rest =>REST_system,

button_stop => button_stop,

button_start => button_start,

system_status => system_on

);

-----------------------------------------%set the vref slope function

Inst_Slope_Function: Vref_Slope_Function Port MAP(


rest =>REST_system,

E => system_on,

Vref_flag => vref_flag,

Vref => Vref_voltage

);

---------------------------------------

Inst_Algorithm_sliding: Algorithm_sliding Port MAP( --% inst SMC algorithm

clk => clk_128M_Sys, --%select one clock of three

--% clk => clk_64M_Sys,

--% clk => clk_32M_Sys,

rest =>REST_system,

E => system_on,

load_change=>load_switch,

clk_account => pwm_count,

Vref_given => Vref_voltage,

din => data_average, --for 10bit, AD_Filter is selected

--din => data_AD(9 downto 0), --for 10bit, AD_Filter is not selected

pwm_value => pwm_value

);

------------------------------------------%Output PWM

Inst_Output_PWM: PWM_out_without_dead_time port MAP(


rest =>REST_system,

E => system_on,

clk_account=>pwm_count,

pwm_value => pwm_seg_dcm, -- use control law

--pwm_value =>"100000", -- for open loop test in hardware DPWM

power_flag =>power_flag,

pwm1 =>pwm1,

pwm2 =>pwm2,

power_on =>power_on

);

------------------------------------------%Output relative LED

Inst_Output_LED: Output_LED Port MAP(


rest =>REST_system,

E =>system_on,

power_on =>power_on,

slope_flag =>vref_flag,

clk_LOCKED =>LOCKED_OUT3,

LED_clk_ready =>LED_clk_ready,

LED_system_on =>LED_system_on,

LED_vref_slope =>LED_vref_slope,

LED_power_charge =>LED_power_charge );

---------------------------------------------------------------------

XIV

Inst_Road_Switch: Deal_key_Switch Port MAP(--%load variation button deal


rest =>REST_system,

E =>system_on,

button_SW1 => button_SW1,

button_SW2 => button_SW2,

button_CANCEL => button_cancel,

load_transient => load_switch,--transient load

SW1 => Switch1,

SW2 => Switch2

);

---------------------------------------------------------------------

Inst_AD_Filter: AD_Filter Port MAP(--%ADC data filter


rest =>REST_system,

data_in =>data_AD,

data_out =>data_average

);

--====================================================================

end Behavioral;

XV

Appendix G: Test of PID and RST at Switching Frequency 1MHz

Parameters of RST controller at 1MHz:

0 1 1 2 2 3 3

0 1 1 2 2

1 1 2 2

-

-

u k T w k T w k T w k T w k

R y k R y k R y k

S u k S u k

where

2

2

3 2

( ) 27.0362 48.3568 21.8616

( ) 1.05040 0.05050

( ) 48.6219 116.4903 93.1598 24.7504

R z z z

S z z z

T z z z z

Parameters of PID controller at 1MHz:

0 1 1 2 2 1 1 2 2d k R e k R e k R e k S d k S d k

where

2

2

( ) 40.2481 78.5639 38.5882

( ) 1.1647 0.1647

R z z z

S z z z

101

102

-40

-35

-30

-25

-20

-15

-10

-5

0

5

f [KHz]

S [

dB

]

PID Syy

RST Syy

-10dB

Fig. G-1 Syy sensibility function for RST and PID controllers at 1MHz

XVI

Fig. G-2 Mosfet driver signal of PID Control Fig. G-3 Mosfet driver signal of RST Control

Fig. G-4 High-side Mosfet driver signal and Vout Fig. G-5 High-side Mosfet driver signal and Vout

of PID controller of RST Control

Fig. G-6 transient Vout of PID when load Fig. G-7 transient Vout of RST when load

goes from 0.3A to 0.46A (R: 5Ω→3.3Ω) goes from 0.3A to 0.46A (R: 5Ω→3.3Ω)

XVII

Appendix H: Test of PID and RST at Switching Frequency 2MHz

Parameters of RST controller at 2MHz:

0 1 1 2 2 3 3

0 1 1 2 2

1 1 2 2

-

-

u k T w k T w k T w k T w k

R y k R y k R y k

S u k S u k

where

2

2

3 2 1

( ) 48.8953 90.9579 42.3798

( ) 1.3755 0.3756

( ) 126.5058 327.7569 283.0460 81.4776

R z z z

S z z z

T z z z z

Parameters of PID controller at 2MHz:

0 1 1 2 2 1 1 2 2d k R e k R e k R e k S d k S d k

where

2

2

( ) 56.2966 111.3238 55.1235

( ) 1.5610 0.5610

R z z z

S z z z

101

102

-45

-40

-35

-30

-25

-20

-15

-10

-5

0

f [KHz]

S [

dB

]

PID Syy

RST Syy

-15dB

Fig. H-1 Syy sensibility function for RST and PID controllers at 2MHz

XVIII

Fig. H-2 Mosfet driver signal of PID Control Fig. H-3 Mosfet driver signal of RST Control

Fig. H-4 High-side Mosfet driver signal and Vout Fig. H-5 High-side Mosfet driver signal and Vout

of PID controller of RST Control

Fig. H-6 transient Vout of PID when load Fig. H-7 transient Vout of RST when load

goes from 0.3A to 0.46A (R: 5Ω→3.3Ω) goes from 0.3A to 0.46A (R: 5Ω→3.3Ω)

XIX

Appendix I: Test of Tri-Mode at 1MHz and Switching Frequency 2MHz

Fig. I-1 transient Vout of Tri-Mode Control at 1MHz when load goes from 0.3Ato 0.46A (R: 5Ω→3.3Ω)

Fig. I-2 transient Vout of Tri-Mode Control at 2MHz when load goes from 0.3Ato 0.46A (R: 5Ω→3.3Ω)

XX

Appendix J: Test of Sliding-Mode at Switching Frequency 1MHz and 2MHz

Fig. J-1 Mosfet driver signal of SMC Fig. J-2 Mosfet driver signal of SMC

operating at 1MHz operating at 2MHz

Fig. J-3 High-side Mosfet driver signal and Vout Fig. J-4 High-side Mosfet driver signal and Vout

of SMC operating at 1MHz of SMC operating at 2MHz

Fig. J-5 transient Vout of SMC operating at 1MHz Fig. J-6 transient Vout of SMC operating at 2MHz

when load goes from 0.3A to 0.46A (R: 5Ω→3.3Ω) when load goes from 0.3A to 0.46A (R: 5Ω→3.3Ω)

XXI

Appendix K: Information about IC Design of the Digital Controller

As the preliminary research work, the proposed digital controllers only have been

implemented in FPGA to validate the design functionality, and the subsequent project to

implement the digital controller on a 0.35µm CMOS ASIC has started lately. The IC layouts

of PID and RST controller have been accomplished, and the implementation of SMC is

under process. The prepared layouts have been delivered to IC fabrication, and the chips will

be available after April 2009. Here are some information about the digital controller IC

design.

The IC design follows the top-down design flow in the digital integrated-circuit. The

design procedure and verification task involves the flowing tools:

1. Modesim ver5.8c (Mentor)

2. Buildgates ver05.17 (Cadence)

3. Encounter ver6.2 (Cadence)

4. IC ver5.1.41 (Cadence)

5. Assura ver5.1.41 (Cadence)

The design flow is figured in Fig. K-1, where it includes the layout and the verification

implementation. Due to the lake of DMC module at present, the Hybrid ∆-Σ DPWM is

implemented as 6-bit ∆-Σ modulator and a 5-bit counter comparator. The layout of the RST,

PID and DPWM is shown in Fig. K-2, and the Pins location of the IC are detailed in Fig. K-3.

The characteristics of the IC are summarized in Table K-1. It is clear that the RST controller

consumes larger area than PID, which validates the description in Chapter3. From the

characteristics table, it can be seen that the proposed digital controller allows operation at

very-high switching frequencies and has very low power consumption. The precise energy

evaluation of the IC can be obtained only by the test on the final IC.

Table K-1 Parameters of chip-implementation for proposed digital controller

Module On-Chip Area Frequency range Power Current cons.

RST

PID

DPWM

2478476.00 µm2

1064081.18 µm2

98880.60 µm2

up to 21.92 MHz

up to 51.23 MHz

up to 98.04 MHz

2.3893 mW

0.7618 mW

0.0545 mW

33.03 µA/MHz

4.51 µA/MHz

0.17 µA/MHz

XXII

RTL Simulation

(ModelSim)

Logic Synthesis

(Buildgates)

Contraints

Technology File

Other reports Timing Contraints Gate Level Netlist

Standard Cell Place and Route

(Encounter)

SDF Timing Data

VHDL Testbench Editing

(vi, nedit, emacs)

VHDL Source Code Editing

(vi, nedit, emacs)

Technology File

IO Constraint files

Gate Level Netlist

SDF Timing Data Layout file GDSII

Other reports

Post Process

(IC5.1.41) Stream In Out Map

Design Verification

(Assura) Design Rule

Parasitic Parameter Extraction

(Assura)

Post-layout Simulation

(Spectre)

Layout

Implementation

Layout

Verification

Fig. K-1 IC design flow of the digital controller

Fig. K-2 Layout of PID, RST and DPWM in a 0.35µm process

XXIII

RST/ alpha6[BU12P]

RST/alpha4[BU12P]

RST/alpha0[BU12P]

RST/VDD[VDD3IP]

RST/REST[ICP]

RST/E[ICP]

RST/Vref_flag[BU12P]

PAD/VDD[VDD3OP]

RST/din1[ICP]

RST/din4[ICP]

RST/din6[ICP]

RST/din2[ICP]

RST/din7[ICP]

RST/din5[ICP]

RST/GND[GND3IP]

DPWM/alpha5[ICP]

DPWM/alpha10[ICP]

DPWM/alpha8[ICP]

DPWM/alpha0[ICP]

DPWM/alpha7[ICP]

DPWM/alpha6[ICP]

PAD/GND[GND3OP]

DPWM/alpha9[ICP]

DPWM/alpha4[ICP]

DPWM/E[ICP]

DPWM/PWM2[BU12P]

DPWM/CLK[ICCK12P]

DPWM/rest[ICP]

RS

T/a

lph

a2

[BU

12

P]

RS

T/a

lph

a1

[BU

12

P]

RS

T/a

lph

a10

[BU

12

P]

RS

T/a

lph

a7

[BU

12

P]

RS

T/a

lph

a3

[BU

12

P]

RS

T/a

lph

a9

[BU

12

P]

RS

T/a

lph

a5

[BU

12

P]

RS

T/a

lph

a8

[BU

12

P]

RS

T/C

LK

[IC

CK

16

P]

PID

/VD

D[V

DD

3IP

]

RS

T/d

in0[I

CP

]

PA

D/V

DD

[VD

D3

OP

]

PID

/CL

K[I

CC

K1

6P

]

PID

/E[I

CP

]

PID

/PW

M1

[BU

12

P]

PID

/po

wer_

on

[BU

12

P]

PID

/PW

M2

[BU

12

P]

DP

WM

/alp

ha2

[IC

P]

DP

WM

/alp

ha1

[IC

P]

DP

WM

/VD

D[V

DD

3R

P]

DP

WM

/alp

ha3

[IC

P]

RS

T/d

in 3

[ICP

]

RS

T/d

in 8

[ICP

]

RS

T/d

in 9

[ICP

]

PID

/din

2[IC

P]

PID

/ref_

sho

w[B

U1

2P

]

PID

/din

1[IC

P]

PID

/din

3[IC

P]

PID

/din

9[IC

P]

PID

/din

4[IC

P]

PA

D/V

DD

[VD

D3

OP

]

PID

/rest[IC

P]

PID

/ din

6[IC

P]

PID

/din

8[IC

P]

PID

/din

5[IC

P]

PID

/din

7[IC

P]

PID

/ GN

D[G

ND

3IP

]

PID

/din

0[IC

P]

DP

WM

/po

wer_

on

[BU

12

P]

DP

WM

/po

wer_

flag

[BU

12

P]

DP

WM

/GN

D[G

ND

3R

P]

DP

WM

/ pw

m1

[BU

12

P]

Fig. K-3 Pins distribution of the digital controller IC

High Performance Digital Controller for High-Frequency Low...

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