High- κ /Metal Gate Science and Technology

ANRV380-MR39-08 ARI 27 May 2009 14:50

High-κ/Metal Gate Scienceand TechnologySupratik Guha∗ and Vijay NarayananIBM T.J. Watson Research Center, Yorktown Heights, New York 10598;email: [email protected], [email protected]

Annu. Rev. Mater. Res. 2009. 39:181–202

First published online as a Review in Advance onApril 28, 2009

The Annual Review of Materials Research is online atmatsci.annualreviews.org

This article’s doi:10.1146/annurev-matsci-082908-145320

Copyright c© 2009 by Annual Reviews.All rights reserved

1531-7331/09/0804-0181$20.00

∗Corresponding author

Key Words

metal gates, mobility, capping layers, hafnium oxide, oxygen vacancies

AbstractHigh-κ/metal gate technology is on the verge of replacing conven-tional oxynitride dielectrics in state-of-the-art transistors for both high-performance and low-power applications. In this review we discuss someof the key materials issues that complicated the introduction of high-κ di-electrics, including reduced electron mobility, oxygen-based thermal insta-bilities, and the absence of thermally stable dual-metal electrodes. We showthat through a combination of materials innovations and engineering inge-nuity these issues were successfully overcome, thereby paving the way forhigh-κ/metal gate implementation.

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1. INTRODUCTION

The advent of the information technology boom has spurred enormous growth in Si microelec-tronics over the past two decades. Advanced microprocessors are tailored for high performance(e.g., CPUs, gaming chips, servers) and low power (e.g., handheld mobile phones), with metaloxide semiconductor field effect transistors (MOSFETs) as the key solid-state element within.MOSFETs can have either electrons (nFETs) or holes (pFETs) as the majority carriers, andthese combine to form the basis for CMOS (complementary MOS) logic. At the core of theMOSFET is the gate oxide [currently a Si oxynitride compound, also denoted as SiO(N)],the thickness and quality of which play a critical role in device performance and scaling (1).

As the MOSFET dimensions have shrunk over the past decades for increased speed at constantpower density, the gate oxide thickness has historically reduced in step, per the rules of devicescaling (1). This scaling, however, has ceased over the last two generations of logic devices, startingwith the 90-nm node, because at its current thickness of ∼1.2 nm, the parasitic gate leakage currentdue to tunneling and gate oxide breakdown is already quite high (1), discouraging further reductionin thickness. Therefore, replacing the conventional SiO(N) gate oxide with dielectric materialswith a higher permittivity (so-called high-κ dielectrics) has emerged as a topic of intense researchwithin the academic and industrial research and development communities (2–4) over the pastdecade. For the sake of clarity, we define here a few terms used within this review.

Gate leakage denotes the tunneling current that flows vertically between the gate electrode,gate dielectric, and channel in a MOSFET. In the ultrathin regime, gate dielectric is exponentiallyrelated to the dielectric thickness: J ∼ e−ad , where J is the leakage current density and d is thephysical dielectric thickness.

With regard to electron and hole mobility, the effective mobility of carriers in a channeldirectly impacts the performance of a CMOS device, with higher carrier mobilities correspondingto higher performance. In conventional SiON/poly-Si devices, electron mobility is approximatelythree times the hole mobility, owing to the higher effective mass of electrons.

Equivalent oxide thickness (EOT) represents the equivalent electrical thickness of a high-κ-dielectric layer, were it to have the same permittivity as SiO2. EOT is derived from the gatecapacitance per unit area in accumulation (Cacc) of a MOSFET in the following way. First, thecapacitance equivalent thickness (CET) is calculated using the equation, CET = κε0/Cacc, whereκ = 3.9 (dielectric constant of SiO2) and ε0 is the vacuum permittivity. A quantum mechanicalcorrection (QMcorr) is then performed to subtract the capacitance arising within the Si channel(5) such that EOT = CET − QMcorr (usually approximately 0.3–0.4 nm).

The parameter Tinv is derived directly from the capacitance in inversion of a MOSFET usingthe equation Tinv = κAε0/Cinv, where κ = 3.9 (dielectric constant of SiO2), A is the area of thedevice, ε0 is the permittivity of free space, and Cinv is the inversion capacitance of the MOSFET.For the case of MOSFETs with metal gates, EOT = Tinv − 0.4 nm. EOT and Tinv have been usedinterchangeably to describe electrical thickness of gate stacks, at times resulting in some confusionin the literature.

Polycrystalline(poly) depletion is the additional parasitic capacitance (see Figure 1) arisingfrom depletion in the doped poly-Si gate when the Si channel is in inversion. Poly depletionreduces the total capacitance of stack and increases the Tinv of the device. Poly depletion is usuallyof the order of 0.3–0.4 nm, and use of a metal gate eliminates it.

Threshold voltage (Vt) is the voltage applied to the gate of a MOSFET at the onset of theformation of an inversion layer (called the channel) in the silicon that is adjacent to its interfacewith the dielectric. The formation of this channel allows carriers to flow between the sourceand the drain of the MOSFET. Low-threshold-voltage CMOS devices (∼0.2 V) are essential for

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Poly-Si

Source Channel Si

Metal gateHigh κ

SiOx SiDrain

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1/Cinv = 1/Cpoly + 1/Cox + 1/Csi

Use metalgate

Aggressive scaling

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Figure 1(a) Schematics of high-κ/poly-Si stacks and high-κ/metal/poly-Si stacks. (b) Transmission electronmicroscopy (TEM) images of representative SiON/HfO2/poly-Si and SiON/HfO2/W stacks that illustratethe deleterious impact of poly depletion and the benefits of metal gates. C refers to capacitance of thedifferent elements in the stack.

high-performance applications and are conventionally achieved by doping the poly-Si electrodesto be n-type for nFETs and p-type for pFETs.

Flatband voltage (Vfb) is the voltage (applied to the gate electrode) of a MOS device, at whichthe accumulation layer in the semiconductor disappears. It is characteristic of the effective workfunction of the electrode, is estimated from capacitance voltage (CV) measurements, and is usedto identify appropriate gate materials for CMOS applications.

Owing to the higher permittivities, high-κ dielectrics provide two primary advantages overconventional SiO(N) dielectrics. First, high-κ dielectrics can be grown physically thicker whilemaintaining a similar EOT as SiON, thus offering significant gate leakage reduction (2–4) andmaking these materials attractive for low-power applications. Second, high-κ dielectrics have thepotential to provide significantly lower EOT values than is possible with conventional SiONdielectrics, thereby re-enabling transistor scaling and the use of lower gate voltages. Starting inthe late 1990s, there was a concerted worldwide effort to find an appropriate high-κ dielectric forintegration into CMOS technology. Although Hf-based high-κ materials emerged as the dielectricof choice in 2001–2002 (6–11), many incompatibilities with conventional CMOS processes delayedtheir introduction. However, recent materials innovations paved the way for this technology toemerge as a product reality, evidenced by the high-performance 45-nm (12, 13) and low-power32-nm (14) high-κ/metal gate technology results.

In this article we describe the understanding of the fundamental materials aspects of high-κ/metal gate stacks. To facilitate this, we have organized the paper as follows. In Sections 2 and3, we focus on the basic requirements of high-κ/metal gate stacks and the evolution of gatedielectric materials, respectively. A comparison of different gate electrodes in conjunction withhigh-κ dielectrics is reviewed in Section 4, whereas Section 5 outlines the role of oxygen and its

www.annualreviews.org • High-κ/Metal Gate Science and Technology 183

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interaction with the defect chemistry of high-κ dielectrics and its impact on the Vt, Vfb, and EOTof the high-κ/metal gate stacks. In Section 6, we show that materials innovations have significantlymitigated the initial deleterious mobility impact of these stacks. Achieving appropriate Vt withhigh-κ/metal gate stacks, a significant hurdle to overcome, occurred by the incorporation ofnanoscale dielectric capping layers, as discussed in detail in Section 7. In Section 8, we discuss howthe understanding described in the preceding six sections was used to integrate the appropriatematerials into a CMOS device. Finally, in Section 9, we explore the device benefits of a high-κ/metal gate device in a fully integrated CMOS device.

2. BASIC REQUIREMENTS FOR HIGH-κ MATERIALS

The search for materials exhibiting a higher dielectric constant (κ) of approximately 15–30 (com-pared with ∼3.9 for SiO2), to maintain a higher gate capacitance while retaining an oxide thicknesshigh enough to suppress quantum mechanical tunneling, led to the seeking of insulators with highionic and electronic polarizabilities. Although many metal oxides satisfy these criteria, a few ad-ditional requirements result in a significant culling of the list of possible candidates.

A second requirement is that the dielectric oxide provide a conduction and valence band offsetto Si that is at least 1.5 eV or larger, to avoid leakage into the Si. For example, the compoundTiO2 has a high dielectric constant but is nonetheless unusable because of a small conductionband offset and high electron leakage currents (15). In general, the alternate dielectric materialshould have a band gap of at least ∼5 eV or higher to avoid excessive gate leakage issues.

From a materials compatibility perspective, the oxide layer should not react with Si at thedevice processing temperatures. In a pioneering paper, Hubbard & Schlom (16) investigated thethermodynamic stability of various metal oxides with Si via the silicidation and reduction reactionsMxOy + Si → MzSi + O2 and MxOy + Si → M + SiO2 by estimating the standard free-energychange for the reactions (�G◦) at 1000 K from available data. Compounds with �G◦ < 0—forexample, Ta2O5, which is susceptible to silicidation—were considered unstable and therefore ruledout as potential candidates.

The above criterion is a necessary but not sufficient condition for thermodynamic stability ofthe dielectric layer. Stemmer (17) pointed out that this criterion may be insufficient for the case ofa nonstoichiometric, oxygen-deficient oxide containing oxygen vacancies. Here the energy gainedfrom the annihilation of an oxygen vacancy in the metal oxide can lead to metal silicide formationeven though the stoichiometric oxide itself may be thermodynamically stable against reduction bySi. As an example, for the case of ZrO2, the silicidation reaction ZrO2+2V ··

O+4e + Si = ZrSi + OxO

occurs by the annihilation of two oxygen vacancies per molecule of ZrSi formed. Here V ··O is a

doubly positively charged oxygen vacancy, OxO is a neutral oxygen atom on the oxygen sublattice,

and e refers to the electron. Stemmer indicated that oxides containing an oxygen vacancy concen-tration that is beyond a critical value (estimated at ∼6% for the case of ZrO2) would be susceptibleto silicidation.

Small amounts of the metal from a metal oxide may also dissolve into the near-interfacial Si,rather than gross dissociation of the oxide. Such dissolution is favorable thermodynamically andarises from entropy of mixing considerations (18). Al2O3 is an example in which small amounts ofAl (an n-type dopant in Si) can diffuse into subsurface Si via the reaction Al2O3 + Si = SiO2 +Al (dissolved in Si), resulting in mobility degradation (18).

By a similar argument, the metal oxide and the metal electrode should also be stable againstreaction or interdiffusion to maintain a stable gate stack. This is typically more of an issue in casesin which the gate dielectric and the metal electrode are deposited prior to, rather than after, thetypical high-temperature (∼1000◦C) steps in the device processing.


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3. EVOLUTION OF HIGH-κ GATE DIELECTRIC MATERIALS

Early work toward replacing the SiON gate dielectric started in the late 1990s. A variety of materi-als were examined, with an emphasis toward demonstrating reduced leakage currents and materialswith low interface and bulk trap densities, as determined by capacitance-voltage (CV) measure-ments. Some of the materials studied in this early phase were Al2O3, ZrO2 (19), La2O3 and Y2O3

(20, 21). These films were deposited in the polycrystalline or amorphous phase by use of physicalvapor deposition (PVD), atomic layer deposition (ALD), or chemical vapor deposition (CVD)methods. Importantly, using Al2O3 as a candidate dielectric, researchers early on successfullydemonstrated operational high-κ MOSFETs fabricated in a standard 200 mm CMOS processingline (22). Al2O3, however, was soon found to have three drawbacks. First, its κ (∼9) was inade-quate. Second, at the high processing temperatures of ∼1000◦C, the mobility of the transistorswere degraded owing to Al diffusion into the channel (18). Finally, p-MOSFETs did not functionbecause of B diffusion through the Al2O3 layer and into the Si. ZrO2 was a second compoundthat was heavily studied during the early period because its dielectric constant (κ ∼ 20) was high.However, at high processing temperatures, ZrO2 was unstable with Si (17, 19). La2O3 was alsoone of the earlier high-κ oxides studied. Although La2O3 was well behaved, with the capability forlow EOT stacks, the presence of an intrinsic dipole within the film resulted in capacitor structureswith large negative Vfb shifts that were unacceptable (20). As discussed below, this property ofthe material can be used advantageously to adjust threshold voltages of devices. A second line ofinvestigation pursued epitaxial dielectric films of SrTiO3 grown on Si(100) (23). Although therewere early promising reports, reproducibility was an issue, and no significant benefit arising fromthe epitaxial nature of the films was consistently observed.

It was in the early 2000s that much basic understanding of the behavior of high-κ oxides on Sibegan to be elucidated. Importantly, it was found that the presence of a high-κ oxide catalyticallyresults in the growth of an interfacial Si oxide layer in the presence of oxygen (24, 25). The highlypolarizable nature of the high-κ oxides also results in the easier formation of charge defects thatcould potentially degrade the performance and stability of the device (26).

It was only in approximately 2001–2002 that Hf oxide and nitrided Hf silicate came to bemore or less unanimously regarded as the leading choices for a high-κ dielectric, and this class ofHf-based materials forms the basis of the high-κ technologies of both Intel and the IBM Alliancetoday. Hf oxide has a κ ∼ 20, whereas nitrided Hf silicate has a κ ∼ 16. Both materials are refrac-tory enough to withstand typical Si processing conditions and do not react with the substrate Sior the electrode material above it. Using Hf-based high-κ materials in conjunction with conven-tional polycrystalline-Si electrodes was initially considered a simple solution, but there were manydevice incompatibilities resulting in Vt instabilities, degraded mobility, and unacceptable EOTs.These incompatibilities were significantly mitigated by use of deposited metal gate electrodes, asdescribed in the next section.

4. SELECTION OF GATE ELECTRODES

In conventional SiON/poly-Si devices, appropriate threshold voltages are obtained by dopingthe poly-Si device n-type (using As or P as dopants) for nFETs or p-type (using B or BF2) forpFETs. Activation of these dopants typically requires anneals at approximately 1000◦C for about5 s. The introduction of high-κ dielectrics in place of SiON required the high-κ dielectrics to bestable in contact with poly-Si electrodes at these temperatures. This was a major reason leadingto the selection of Hf-based materials. Unfortunately, in conjunction with poly-Si electrodes,Hf-based materials still had a number of significant challenges (27): (a) the difficulty in scaling


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Tinv for high-performance applications, (b) reduced carrier mobility, and (c) anomalously highpFET Vt.

As shown in Figure 1, owing to poly depletion high-κ/poly-Si stacks inherently do not scale Tinv

to the same degree as do high-κ/metal stacks. In addition, nucleation of either ALD or MOCVD(metal organic chemical vapor deposition) Hf-based dielectrics usually requires the presence of a0.8–1-nm low-κ SiO2 or SiON template for high-κ growth (27, 28), further reducing the abilityto scale. HfO2/poly-Si gate stacks also suffered from significant electron mobility degradation.Mobility degradation is attributed to a combination of two scattering mechanisms: remote phononscattering (RPS) due to coupling of low-energy phonons in the high-κ material with electrons inthe channel (29) and remote Coulomb scattering (RCS) due to charges in the gate dielectric or thegate dielectric/SiON interface that scatter electrons in the channel (30). RPS could fundamentallylimit the performance of HfO2 dielectrics and other future higher-κ devices independently of gateelectrode choice because soft optical phonon coupling is expected to become stronger as the κ

value increases (29). A possible solution is based upon the incorporation of Si into the HfO2, withthe expectation that soft phonon modes would be reduced in intensity (27). These predictions wereexperimentally supported by experiments on Hf silicates (31). The mobility advantage comes atthe expense of a reduced dielectric constant (κ ∼ 10–15 for HfSiO). Nitrogen can be incorporatedinto HfSiO dielectrics to help boost the κ of the dielectric while preventing phase separationof HfSiO (32) and resulting in an amorphous gate dielectric. However, N incorporation intothe dielectric can result in additional mobility degradation owing to RCS (N can act as fixedcharge that scatters electrons in the channel). Experimental studies indicate that mobility impactis greatest if nitridation conditions allow N to permeate the entire HfSiO film, whereas near-surface nitridation preserves mobility (32). This indicates that N in or close to the interfacial layer(IL) has a significant mobility impact.

Although the mobility improvements were a big achievement, the threshold voltages of poly-Sigated high-κ nFETs and pFETs deviate substantially from those of corresponding SiON devices,especially for pFETs in which the Vt is ∼600 mV (33, 34) greater than for SiON/poly-Si. Mea-surement of Vfb/Vt immediately after key gate stack processes showed that Vfb/Vt are largely setduring poly-Si deposition and remain virtually unchanged during gate implantation and thermalactivation (35). The mechanism for these shifts has been attributed to Fermi-level pinning, causedby a high density of states at the metal/semiconductor interface, whose occupation changes asthe gate voltage is swept from the accumulation to the inversion condition (36). The interfacestates partially screen the electric field from the gate electrode, preventing the electric field fromreaching the channel (27). The extent of gate-induced tuning of the channel carrier occupancy isthus greatly reduced. Using careful studies of the HfO2/poly-Si interfaces, including depositionof a monolayer of HfO2 and then poly-Si, which resulted in significantly large shifts, researchersargued that Fermi-level pinning just below the Si conduction band is caused by Hf-Si bonds at thehigh-κ/poly-Si interface (33, 34). Alternatively, the O vacancy formation in HfO2 may also explainsuch results (37–39); this possibility is examined in detail in a section below. Similar Vt/Vfb shiftswere also observed with high-work-function metal gates (40), and these results lend credence toa more general effect rather than one related specifically to Si bonding–related defects. Selectiveintroduction of scaled Al2O3 (41) and aluminum nitride (AlN) capping layers (42) sandwichedbetween the high-κ and p-doped poly-Si gate stacks can reduce the pFET Vt shift by ∼300 mV,but the resulting Vt and EOT are not competitive with or better than SiON/poly-Si for mosthigh-performance applications.

A metal gate solution for CMOS applications, although attractive from an EOT scaling per-spective, would still be very challenging to integrate into a CMOS flow. An attractive alternativeapproach to fabricate metallic gates is to fully silicide conventional poly-Si gates (also called FUSI


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gates), which, after silicidation transformation, are in direct contact with the dielectric film. FUSIof conventional poly-Si gates had been explored in the past with SiON dielectrics, and an encour-aging effect of reduced Tinv for the same physical structure and thickness of the dielectric stackhad been observed (43, 44). A typical FUSI flow follows a poly-Si CMOS flow, but to preventpartial silicidation of the gate during source/drain silicidation, an oxide/nitride mask is maintainedon top of the gate (27). After silicidation, an oxide overlayer is deposited, followed by chemicalmechanical planarization (CMP), removal of the cap layer on top of the poly-Si gate, and finallymetal deposition at a thickness sufficient to fully silicide the poly-Si gate after moderate annealingat 400–500◦C.

Ni-based silicide materials emerged as a leading candidate for FUSI gates for several reasons:These materials have a low resistivity of ∼15–25 μ� cm and a low volume expansion of lessthan 20% and have already been introduced for source/drain silicides in Si Front End Of the Line(FEOL) processing for sub-90-nm technology nodes. In terms of electrical properties, FUSI gatesshow a metallic behavior (owing to complete silicidation) with no signature of poly-Si depletion foreither high-κ or SiO2 gate dielectrics, as shown in Figure 2a. Similar to high-κ/poly-Si devices,achieving band-edge work functions for FUSI-based devices remains a key issue. Undoped NiSigates show a mid-gap work function (Figure 2a), and several techniques have been used to adjustthe work function of FUSI gates toward band edges in conjunction with Hf-based high κ (27).Such techniques include predoping of poly-Si gates with n+ and p+ dopants before gate silicidation(45); changing the composition of FUSI gates, in particular alloying Ni with other elements suchas Pt or Ge for pFET shifts and Al for nFETs; using different silicide phases; and employingultrathin cap materials between the gate dielectric and FUSI gate (46, 47), Among these options,it appears that the largest Vt tuning is achieved by alloying Ni silicides with low- and high-work-function elements. The mechanism of this Vt modulation is not fully understood at this moment,

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FUSI

n + poly-Si control

Dielectric:HfO2/SiO2

Tqm gain~1.5 A

Tinv gain~5 A

~0.55 V

100 × 100 nFET

Figure 2(a) Capacitance voltage (CV) curves showing the Tinv benefit of FUSI gates in comparison to poly-Si gates.Reproduced with permission from Gusev et al. (27). (b) Accumulation and inversion split CV curves showingthat the choice of metal gates can result in significantly different Tinv even when one uses nominally identicaldielectric stacks with the equivalent oxide thicknesses (EOTs) of W stacks > TaN stacks > TiN stacks. ALD,atomic layer deposition; CVD, chemical vapor deposition; PVD, physical vapor deposition. Adapted withpermission from Narayanan (82).


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although it is believed to be related to the segregation of the alloying element at the FUSI/dielectricinterface (27). Regarding scaling issues of high-κ/FUSI gates, one could expect similar concernswith regrowth and reactions at temperatures as high as those for high κ/poly-Si, although theelimination of poly-Si depletion can result in Tinv as low as 1.6 nm (46). Most companies havediscontinued work on FUSI, largely because of (a) concerns of uniform silicidation across differentgate lengths and device pitches, (b) the absence of truly band-edge pFET devices, and (c) continuedconcerns of scalability at Tinv of less than 1.6 nm, which is needed for the 32-nm node and beyond.

We have discussed the merits and demerits of poly-Si and FUSI electrodes and have shownthat both approaches suffer fundamentally from the ability to continue to scale Tinv to the require-ments for the 32-nm node and beyond. For deposited metal gates, initial results were limited toscaling close to Tinv = 1.6 nm (11), or Tinv scaling was achieved with significant electron mobilitydegradation (48). Recently, a number of different groups (49–51) have achieved Tinv of 1.4 nm (asshown in Figure 2b) by using thin TiN or TaN gate electrodes inserted between Hf-based high-κand poly-Si electrodes. The poly-Si stacks provide very good protection against the processingambient and, with the use of optimized metal alloys, result in an electron mobility competitivewith SiON/poly-Si.

Thermally stable dual-metal electrodes are required for compatibility with conventionalCMOS high-temperature processing. Most of the low-work-function elemental metal gates (4.1to 4.3 eV) are reactive and do not withstand conventional CMOS annealing temperatures (52).The exceptions are TaN, TaSiN, and TaC (11, 53), which were reported to have low nFET workfunctions and to remain stable to high temperatures. In contrast, most of the mid-gap (includingTiN) and high-work-function metal gates remain structurally stable to high temperatures (800–1000◦C). However, these high-work-function electrodes suffer from anomalously high Vt/Vfb

when in contact with Hf-based dielectrics (similar to p-doped poly-Si) at elevated temperatures.Described simply, the Vt/Vfb predicted using the metal work functions (54) are accurate for low-temperature-processed devices, but high-temperature processing results in large Vt/Vfb shiftstoward a mid-gap effective work function (especially for pFET electrodes). Similar to Fermi-levelpinning observations of poly-Si, the Vfb modulation is thought to be related to the oxygen va-cancy concentration in the Hf-based dielectric near the metal contact; this is discussed in detail inSection 5.

To conclude this section, even with many challenges, deposited metal gate electrodes exhibitthe most promise for continued dielectric scaling and have been chosen industry wide as theelectrode of choice for next-generation CMOS applications.

5. MATERIALS ISSUES IN GATE STACKS

The proximity, distinctly different properties, and nanometer-scale thicknesses of the layers con-stituting the gate stack (i.e., Si/IL/high-κ/metal) ensure a high possibility for inter-reactions whenheated up to standard Si processing temperatures in different ambients. The most significant ofthese interactions is caused by oxygen, which can be present in trace amounts in industrial inertgases. Oxygen can diffuse rapidly through the high-κ-dielectric layer and will transport to theregion where its chemical potential is the lowest. As a result, in the presence of oxygen, Si oxideformation with thicknesses of a few nanometers at the Si/high-κ interface can take place evenat temperatures of ∼500–600◦C and in ambients containing trace amounts of oxygen. This wasshown by use of careful medium-energy ion-scattering (MEIS) experiments of very thin layersof Al2O3 grown on Si and annealed in vacuum in the presence of small amounts of oxygen (25).The interfacial oxide thickness, measured by MEIS, increased at higher partial pressures of oxy-gen. Narayanan et al. (24), using defect-free, lattice-matched lanthanum yttrium oxide (LaYO)


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Ge

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Si

a b

Figure 3Cross-sectional transmission electron microscopy (TEM) images showing Si/epitaxial LaYO/Ge cap layers.For the sample in panel a, the LaYO layer was quenched and capped immediately after epitaxial growth withGe. In contrast, in panel b the sample was exposed to the oxygen beam for ∼10 min at ∼750◦C (the growthtemperature), prior to quenching and capping with Ge. Note the growth of interfacial oxide at the Si/LaYOinterface in panel b and the absence of this layer in panel a, pointing to oxygen incorporation and diffusionthrough the LaYO layer. Adapted with permission from Narayanan et al. (24).

structures grown by molecular beam epitaxy on Si, showed that the interfacial oxidation is causedby the diffusion of oxygen from the ambient and through the high-κ oxide layer into the Si/high-κinterface. An example is shown in Figure 3. The conclusions were drawn by comparing the resultsfrom LaYO/Si samples that were capped with Ge or Si (good diffusion barriers for oxygen) di-rectly after LaYO growth, and capped after a postgrowth exposure at 750◦C to a 10−5 torr oxygenambient for ∼10 min. The TEM analysis showed that the postgrowth-exposed samples had acatalytic growth of ∼3 nm of interfacial Si oxide (Figure 3b), whereas the control samples had nodetectable formation of interfacial oxide

Such oxygen diffusion and interfacial oxide growth have been observed for other relevanthigh-κ oxides (55). The work of Narayanan et al. (24) also showed that the oxidation can beprevented by capping the oxide layer with an oxygen barrier layer such as Si or Ge (Figure 3a).However, attempts at using elemental metals such as W as metal electrodes and caps to preventsuch oxidation were unsuccessful and brought to the fore the observation that very small amountsof oxygen solubility in the metal electrodes result in the diffusion of oxygen from the metal andinto the Si/high-κ interface, leading to interfacial oxidation. This was shown by Preisler et al. (56)for the case of W electrodes used in fabricating HfO2/Si MOSFETs. Using careful MEIS andelectrical measurements of stack capacitance, these researchers also showed that a Si/HfO2/W gatestack (grown without breaking vacuum in an ultrahigh vacuum deposition chamber) increases inthickness upon annealing owing to the formation of a SiO2 layer at the Si/HfO2 interface. Furtheranalysis showed that the oxygen for this growth must have arrived from dissolved oxygen in themetal electrode (Figure 4a). Because the dielectric layer thickness is fewer than a few tens ofatomic hops, the entire gate stack and the variation of the oxygen chemical potential across thisstack need to be taken into consideration. The dissolved oxygen in the metal electrode thus “sees”the Si/HfO2 interface at moderate anneal temperatures and diffuses to form interfacial SiO2. Theinterfacial oxides are often thicker than what would be expected for the oxidation of a bare Sisurface under similar oxygen ambients. Therefore, similar to the case of LaYO, it is stronglysuspected that there is a catalytic effect rendered by the high-κ oxide and that interfacial SiO2

regrowth occurs likely due to atomic rather than molecular oxidation of the Si surface. Many of


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a

78 80 82 84 86 92 94 96 98 1000

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Figure 4(a) (i) Medium-energy ion-scattering (MEIS) data of the oxygen profile from a Si/SiO2/HfO2 stack showing the penetration of theoxygen profile in the case of a sample annealed in ultrahigh vacuum (blue line) compared with an unannealed sample (purple line). Theprofile indicates the formation of an interfacial Si oxide layer. (ii) The MEIS-measured Hf profile shows no relative motion of Hf in thetwo cases. (b) Mobility characteristics as a function of inversion charge density (Qinv) for untreated and rapid thermal-annealed (RTA)samples. The mobility increase in the annealed samples is due to the formation of the interfacial Si oxide. Redrawn with permissionfrom Preisler et al. (56).

the gate electrodes, including Pt, W, and Re, are thus incapable of providing devices with verylow electrical thicknesses as a result of this dissolved oxygen (27).

However, electrodes that have an oxygen-scavenging effect due to a high solubility for oxygencan help preserve the thickness of the gate stack and prevent interfacial Si oxidation; examples ofsuch electrode materials are TiN and, to some extent, TaN and TaC. Indeed, this is the reasonfor the extensive use of these electrodes in p- or n-channel high-κ-based MOSFETs today, eventhough they have nonideal band lineups and therefore require further adaptations to the structure(discussed below). Kim et al. (57) elegantly demonstrated this oxygen-scavenging effect. Using aZrO2/Si structure, they showed that when a Ti electrode was used, the interfacial Si oxide layerat the ZrO2/Si interface could be nearly eliminated by annealing at 300◦C owing to a getteringaction of the Ti, whereas this interfacial oxide was retained when an Al electrode was used.

A mysterious, and technologically critical, observation made early on in the development ofpFETs was that when a high-vacuum work-function (>∼4.5 eV) metal was used as an electrodefor the Si/HfO2 structure, there was unexplained band bending in the Si layer that resulted ina negative shift in Vt/Vfb of the device (40, 58). Moreover, this shift changed, depending uponanneals in oxygen-containing environments (40). The direction of band bending observed couldbe explained by the generation of positive charges in the dielectric layer, and Shiraishi et al. (37)and Cartier et al. (40) attributed this shift to the generation of positively charged oxygen vacanciesin the dielectric. They postulated that when the Fermi level of the metal electrode lies belowthe energy level corresponding to the neutral oxygen vacancy level (39), electron transfer occursfrom the neutral vacancy into the metal, resulting in the formation of a positively charged oxygenvacancy in the dielectric layer (Figure 5), per the reaction Ox

O=V ··O+2e + OM. Here Ox

O refers toan oxygen atom on the oxygen sublattice, V ··

O is a doubly positively charged oxygen vacancy, e isan electron, and OM refers to an oxygen atom either dissolved in the electrode or released intothe ambient as a molecule.


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ba

Ec

Ev

V0

φm

Ef

Oxide Metal

V0++ Re electrode

φm

Ef

Ec

Ev

φ0

O2 (g)

OM

Oxo

½O2 (g) = OM

V xo + OM = Ox

o

Oxo = V x

o + SiOx

Vo

SiOx

HfO2

Si

Figure 5(a) Schematic showing the transfer of charge from an oxygen vacancy level into the metal electrode when themetal Fermi level lies below the energy level corresponding to the oxygen vacancy. This results in thedielectric layer acquiring a net positive charge and a voltage drop across the dielectric. (b) Mechanism foroxygen introduction into the HfO2 layer from the metal electrode. Vacancy annihilation at the topHfO2/metal interface results in oxygen injection, followed by vacancy generation at the bottom HfO2/SiO2interface due to the formation of SiO2. The notation (g) in the reaction indicates oxygen in the gas phase.Adapted with permission from Guha & Narayanan (59).

Guha & Narayanan (59) subsequently developed a model for the kinetics of oxygen vacancyformation in electrode–high-κ oxide–semiconductor heterostructures. For a given arrival rate ofoxygen atoms on the top surface, which is determined by the oxygen partial pressure or the activity,oxygen vacancies in the high-κ oxide are annihilated at the top interface by dissolved oxygen in themetal gate and created by interfacial oxidation of the Si at the bottom interface. They estimatedboth (a) the concentration of oxygen vacancies formed in the high-κ oxide film and (b) the growthrate of the interfacial Si oxide at the Si/high-κ oxide interface as a function of the oxygen partialpressure during thermal treatments. The oxygen vacancy concentration was, in turn, correlatedto an expected potential drop across the high-κ layer via a solution of Poisson’s equation. Themodel predicted that the voltage drop in the dielectric layer (�φ) was related to the oxygenpartial pressure as (59) ln(�φ) = K1 − K2 p−1/2

O2(under transient conditions) and �φ = K3 p−1/2

O2

(under steady-state conditions) and that the voltage shift was simply related to the interfacial oxidethickness as �φ = K3�SiO2 + K4.

Using CV measurements to estimate both (a) the voltage drop across the high-κ oxide and(b) the interfacial Si oxide layer thickness on a set of Si/HfO2/Re capacitors annealed at differenttemperatures under specific oxygen partial pressures, Guha & Narayanan (59) were able to showvery good agreement with the above predictions, thereby providing clear evidence for the relevanceof oxygen vacancies as the dominant defect in HfO2. The above model also uniquely tied togetherthe observations of interfacial oxide growth and band bending changes in the Si as a function ofannealing in oxygen ambients. In essence, oxygen is introduced into the HfO2 through the topHfO2/metal interface by injection from the metal and the annihilation of oxygen vacancies. Theoxygen atoms migrate to the bottom interface, where they react with Si to form SiO2, therebygenerating oxygen vacancies at the bottom HfO2 interface. There is thus a generation-annihilationprocess for oxygen vacancies that continues at the top and the bottom of the HfO2 layer, resultingin bottom interfacial oxide growth. A schematic of the process is shown in Figure 5b.

The charged oxygen vacancy in the dielectric oxide is the case of a native donor defect whoseconcentration depends upon the oxygen environment. Using a thermochemical approach, Guha& Solomon (60) obtained the same 1/p1/2 dependency on the oxygen vacancy concentration in the


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steady-state approximation arrived at earlier by Guha & Narayanan (59) using the kinetic approachdescribed above. The thermochemical approach, however, allowed for interpretation of the resultsin terms of the oxygen vacancy formation energy, DG, and comparison with data indicated that thevacancy formation energy was low, at ∼3 eV, and an oxygen concentration of ∼0.3% was neededto explain the 0.5-V drops observed across the dielectric layer. This is in contrast to theoreticalestimates that place the oxygen vacancy formation energies significantly higher, at ∼9 eV (61).

6. MATERIALS INNOVATIONS FOR HIGH MOBILITYWITH HIGH-κ/METAL GATES

Scaled metal-gated high-κ stacks exhibited significantly reduced electron mobility as comparedwith SiON/poly-Si (11, 48), a significant roadblock for successful implementation of these newgate stacks. Fischetti et al. (29) theoretically studied electron mobility degradation by the scat-tering of channel electrons in nMOSFETs with the soft optical phonons in HfO2 gate dielectrics(RPS). Besides the prediction of strong coupling between the channel electrons and the soft HfO2

phonons, these researchers also demonstrated that the presence of IL SiO(N) can significantlydampen soft optical phonon scattering, leading to substantially improved mobilities, albeit at theexpense of gate capacitance. The RCS model (30), wherein the charges at the Si/IL or IL/HfO2 orthose within the bulk of the HfO2 scatter the electrons within the channel, have also been shownto play a strong role in the reduction of electron mobility, although opinion is still clearly dividedas to which scattering component is dominant.

Interfacial SiO2 regrowth during high-temperature (1000◦C, 5-s) processing can substantiallyenhance mobility in the case of SiO2/HfO2/metal stacks, whereas for identical stacks processedat low temperatures (<600◦C), electron mobility is significantly degraded (62, 63). However, itis not clear as to whether this improvement was due solely to regrowth of the SiO2-like layer orwhether concurrent structural/electronic changes occurring within the stacks improved mobility.High electron mobility competitive with the electron mobility of SiON/poly-Si can be attainedwithout IL growth (for Tinv < 1.4 nm) by careful optimization of a conventional, self-alignedCMOS process by choosing appropriate metals (TiN) and poly-Si capping layers (49, 51). This isillustrated in Figures 2b and 6a, which show that high mobilities were obtained with TiN and TaNgates while maintaining aggressive Tinv; thus, IL regrowth is not required for high mobilities. Thissame study (49) showed that for Si-capped SiON/HfO2/TaSiN/stacks and SiON/TaSiN stacks,high mobility was observed only for stacks that had seen a 1000◦C, 5-s anneal (Figure 6b). Thisimprovement was attributed partly to the relaxation of growth stresses in SiON stacks (64) andmostly to structural modification at high temperatures that reduced compensated charge at theIL/HfO2 interface (49).

The origin of this structural modification has been polemical. The Hf may intermix with anon-N IL to form a higher-κ Hf/silicate IL (62), which results in higher mobility than HfO2

because of weaker coupling of the SO phonons compared with HfO2. However, a number ofresearch groups have chemically analyzed the IL, using low-loss electron energy loss spectroscopy(65) and MEIS (66), and show no evidence for Hf silicate, although there is evidence within the ILof the presence of Hf atoms (67). The electrical data also show that this transformation does notchange the Vt or Tinv of the device, suggesting that the electronic signature of this transformation,if it has a coulombic component, would require the elimination of compensated charge. Thus, theorigin of the structural change remains unresolved.

Additionally, different research groups (68, 69) have recently shown that high mobilities canbe achieved in a gate-last process using SiO2 ILs without a high-temperature annealing step.To resolve these conflicting mobility results, mobility evaluations of stacks with non-nitrided


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0 5 10 150

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EOT (nm)2.11.61.10.6

W (Tinv = 2.05 nm)

TiN (Tinv = 1.4 nm)

TaN (Tinv = 1.7 nm)

Dielectric: HfO2/SiO2

After 1000 °C, 5 s RTA

SiO2/HfO2/TiN/Si, 1000 °C

SiO2/HfO2/TiN/Si, 600 °C

SiON/HfO2/TaSiN/Si, 600 °C

SiON/HfO2/TaSiN/Si, 1000 °CPoly/SiON control sample

At 1 MV cm–1

SiON/HfO2/TaSiNNa ~ 1×1017

cm3

SiO2/HfO2/TiN

a b

Figure 6(a) Electron mobility curves of self-aligned nFETs with SiO2/HfO2/metal gate stacks after a 1000◦C, 5-sanneal. (b) Mobility versus Tinv comparison of self-aligned SiO2/HfO2/TiN and SiON/HfO2/TaSiN stacks.EOT, equivalent oxide thickness; RTA, rapid thermal annealed. Adapted with permission from Narayanan (82).

interfaces and TiN electrodes were conducted, and the results are shown in Figure 6b. Themain differences from the previous studies (49) are (a) the use of SiO2 ILs versus SiON ILs and(b) the use of optimized TiN as opposed to TaSiN. Figure 6b makes clear that with non-nitridedinterfaces and optimized TiN processes, high electron mobility can be obtained at low Tinv for lowprocessing temperatures. This suggests that either (a) SiON ILs need high temperatures (unlikeSiO2 ILs) or (b) TaSiN inherently introduces some remote charges into the gate stacks near theIL/HfO2 interface that need to be annealed away at high temperatures.

High mobility for optimized high-κ/metal gate stacks has also been attributed to so-calledmetal gate screening effects, whereby the strong coupling that is observed between the soft op-tical phonons in the HfO2 and the electrons in the channel is “screened” by the presence of ametal gate on top of the HfO2 (50). Figure 7 shows that by using non-nitrided interfaces andHfO2/TiN stacks in a gate-first approach, one can approach the theoretical RPS-limited mobilityin the presence of a thin SiO2 like the IL (70). This mobility is similar to typical SiON/poly-Simobilities observed in state-of-the-art CMOS devices, suggesting that even with RPS-limited mo-bilities, the presence of a thin IL and optimized HfO2/TiN stacks can help achieve <1-nm EOTstacks with competitive electron mobilities. When these stacks are compared with HfO2/TiNlow-temperature stacks from Casse et al. (71), it is clear that the mobilities of the former are muchlower. This phenomenon is attributed to unoptimized HfO2/TiN processes that suffer from sig-nificant RCS, which dominates their data. Figure 7b shows temperature exponents comparinglow-temperature (60–120 K) mobility measurements of optimized SiO2/HfO2/TiN stacks withSiO2/poly-Si and SiO2/HfO2/poly-Si. A careful comparison of the HfO2/TiN temperature expo-nent with the theoretical HfO2/poly-Si curve clearly shows that they are similar. Thus, if the metalgates screen the soft optical phonon modes in HfO2, as claimed by Chau et al. (50), the tempera-ture exponent for the HfO2/metal curve should be more like the theoretical SiO2/poly-Si curve,which has a stronger temperature dependency, than the HfO2/poly-Si case. Thus, in conclusion,


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100

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At Ninv = 5 × 1012 cm–2

T–1.5

T–0.85

HfO2/TiN (comparison)

SiON/poly-Si

With IIS

RPS, theory

HfO2/TiN

Ninv = 3 × 1012 cm–2

NA = 1 × 1017 cm–3

TiN/HfO2 experiment (Tinv = 1.4 nm)

Poly/HfO2

Poly/SiO2 experimentSiO2 theory

a b

Figure 7(a) Comparison of experimental mobility values with theoretical mobility values [using remote phonon scattering (RPS) theory] as afunction of interfacial oxide thickness. Data from Casse et al. (71) have been included for comparison. (b) Comparison of temperatureexponents for the aggressively scaled HfO2/TiN nFETs with theoretical (and experimental) temperature exponents for HfO2/poly-SinFETs and SiO2/poly-Si nFETs. Adapted with permission from Maitra et al. (70).

there is no direct experimental evidence of metal gate screening of soft optical phonon modes inHfO2 gate dielectrics, even in aggressively scaled (EOT = 1 nm) high-mobility HfO2/TiN-basednFETs. A thin IL (0.5–0.8 nm) and careful process optimization to eliminate/reduce the knownsources of Coulomb scattering in the HfO2 gate stack lead to high mobilities in the optimizedhigh-κ/metal gate nFETs.

7. Vt TUNING USING NANOSCALE CAPPING LAYERS

Metal electrodes such as TiN or TaN are essential for MOSFETs owing to the high affinity of suchelectrodes for oxygen, which prevents thickening of the interfacial Si oxide. However, the workfunctions of these metals are inappropriate for use as nFETs, resulting in band bending in the Siand unacceptably high Vt for the MOSFETs. To adjust the Vt, a new metal oxide or nitride (calleda cap layer) has to be introduced on top of the HfO2 layer. The cap layer creates a voltage dropacross the dielectric stack, thus effecting a negative shift in the transistor Vt to bring it to withinacceptable limits. An IBM group (72–74) first demonstrated this successfully without significantcompromise in mobility or the EOT of the stack by using La-containing dielectric cap layers, asshown in Figure 8.

The reason behind the voltage shifts due to the cap layers is unclear, although the shiftsare speculated to be related to the formation of dipoles (73, 74). It was argued that the cationelectropositivity in the cap layer tends to determine the effected shift in threshold voltage (73, 74).Cations that are strongly electropositive (relative to Hf), such as group IIIB elements Sc, La, and Eror group IIA elements Mg, Ba, and Sr, will shift the threshold voltage toward negative voltages (73),whereas a more electropositive cation such as Al will shift the Vt in a positive direction (75). Oneproblem with this conjecture is that the elemental electronegativity is essentially identical for Mgand Hf and cannot explain the relative Vt shifts that are observed. To explain the shifts observed, onehas to invoke the differences in group electronegativity (using the Sanderson criterion) between thecapping and high-κ layers (76). The effective work function of the SiO2/HfO2 stack is determinedby the charge neutrality level in the system. Therefore, the insertion and subsequent mixing of


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1

22

3

Gate voltage (V) Effective Efield (MV cm–1)0 0.2 0.4 0.6 0.8 1.0 1.20 0.5 1.0–1.0 –0.5

HfO2/TiNTinv = 1.35 nm, Vt = +0.38 V µ = 212 cm2 V–1 s–1

HfO2/La2O3/TiNTinv =1.40 nm, Vt = 0.0V

µ = 203 cm2 V–1 s–1

HfO2/TiNVfb = 0.2 VHfO2/La2O3/TiNVfb = –0.1 V

HfO2/LaN/TiNVfb = –0.2 V

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2 V

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0

Ca

pit

an

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en

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(μ

F c

m–2

)

Figure 8(a) Capacitance voltage (CV) curve showing the shift in the Vfb created by the use of La2O3 or LaN caplayers. (b) Electron mobility versus perpendicular electric field for capping layers. Adapted with permissionfrom Guha et al. (74).

the capping layers with underlying SiO(N)/HfO2 dielectrics result in the formation of a dipolebecause of the differences in group electronegativity (77). As a consequence, a dielectric cappinglayer with a higher group electronegativity than HfO2 would result in a capping layer–inducedshift that is positive with respect to HfO2, while a negative shift would be induced for a dielectriccapping layer with a group electronegativity smaller than HfO2.

There has been extensive physical characterization of rare-earth oxides in the literature. Guhaet al. (74) have shown that the shifts are caused by asymmetric distribution in the rare-earth (inthis case La) diffusion profile within the dielectric stack, and Kamimuta et al. (78) have shownthat the presence of the La closer to the IL/HfO2 interface results in stronger shifts. A rare-earthoxide such as La2O3 is not expected to possess a spontaneous polarization (that could create adipole) because its crystal structure possesses inversion symmetry. Differences in the ionicities ofthe bonds formed at either end of a slab of dielectric containing a rare-earth element, however,can give rise to a net dipole and a corresponding voltage drop across the dielectric (Figure 9).In this case such asymmetry would have to arise from the bonding with SiO2 at one end and ametal electrode at the other. Kirsch et al. (79) have argued that a La-O-Hf bond formed at the La-containing interfacial oxide/HfO2 interface generates the observed dipole because preferentialsegregation of La in the interfacial oxide will give a net direction to the La-O-Hf dipole. Buteven single layers of rare-earth oxides such as La2O3 exhibit negative shifts in Vfb (20). A similarargument for a dipole due to Si-O-La bonds at the interfacial Si oxide/La2O3 interface would,however, generate a dipole that predicts a shift in the opposite direction.

One past argument would be the generation of positively charged oxygen vacancies due to theaddition of aliovalent cations to HfO2, following La2O3= 2La′

Hf+3OxO+V ··

O. Here a substitutionof a La ion with +3 valence onto a Hf site results in a negatively charged defect (La′

Hf) and acompensating positively charged oxygen vacancy (V ··

O) for ensuring site conservation and charge


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M MO O O

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Figure 9Simplified schematic showing how bonding with elements (A and B) of different ionicities at either end of asymmetric metal oxide (M-O) dielectric layer can give rise to a dipole.

neutrality. Spatial separation of these two defect types could lead to a net dipole and a correspondingnegative Vfb shift. However, this possibility appears unlikely because bulk La2O3 films, in whichthere are no such aliovalent substitutions, also result in negative flatband voltage shifts. Similarobservations for positive shifts in the absence of HfO2 are present for SiO2/Al2O3 stacks (80),strongly suggesting that the SiO2/Al2O3 and SiO2/La2O3 interfaces are responsible for the dipole-inducing shifts. In summary, although the shifts are almost certainly related to the electropositivenature of the cations (as described by group electronegativity) and the dipoles formed as a result,the details of the process remain unclear.

8. INTEGRATION OF HIGH-κ/METAL GATE STACKS

Conventional SiON/poly-Si gate stacks always undergo a high-temperature anneal step(∼1000◦C) to ensure activation of n+ and p+ dopants in the MOSFET device for desired de-vice properties. As highlighted in Sections 1–7, high-κ/metal gate stacks suffer from many high-temperature instabilities. As a result of these temperature instabilities, some companies have pur-sued a low-temperature integration scheme.

Championed by Intel (12, 81), the gate-last scheme, also known as the replacement gate scheme,is a low-temperature process flow because the work-function metals for nFET and pFET gateelectrodes are not exposed to high-temperature activation processes and thereby circumvent thetemperature instabilities described above. The typical process flow for the gate stack includesthe growth of the SiOx IL, the deposition of the high-κ gate stack film, and a sacrificial poly-Si layer(81). The high-κ dielectric and dummy poly-Si stack then undergo standard high-temperatureCMOS processes. After deposition of spacer layers, an interlayer dielectric film is deposited,followed by a CMP step that exposes the poly-Si gates. The poly-Si layer is then removed fromboth nFET and pFET areas. Subsequently, metals with work functions appropriate for nFETsand pFETs are deposited and patterned by use of standard techniques. A final gate fill metal isused to completely fill the gate trenches, followed by a CMP step for planarization. Figure 10a

shows an example of this gate-last process.In comparison to the gate-last process, in the more conventional gate-first integration approach

(Figure 10b), both the high-κ electrode and the metal gate electrode are exposed to a high-temperature activation process and is the integration flow that is being pursued by the IBM Alliancefor the 32-nm node and beyond (14). In this high-temperature-compatible flow, a thin metalelectrode (<20 nm) is inserted between the poly-Si and the high-κ layer, ensuring compatibility


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50 nm

33 nm

a b

Figure 10(a) Transmission electron microscopy (TEM) micrograph of a 45-nm high-κ/metal gate pFET fabricated bya gate-last process. Reproduced with permission from Mistry et al. (12); copyright 2007, IEEE. (b) TEMimage of a high-κ/metal gate nFET at a 33-nm L gate, fabricated by use of a conventional gate-firsthigh-temperature process. Adapted with permission from Chudzik et al. (13); copyright 2007, IEEE.

with standard CMOS transistor fabrication. Following gate stack deposition, standard CMOSfabrication techniques such as lithographic patterning, etch, implantation, and high-temperaturesource/drain annealing are performed.

The advantages of the gate-first process over the gate-last process are the elimination of CMPsteps, the retention of channel strain in both nFETs and pFETs, and the potential of obtainingconventional gate-length scaling for future technology nodes. The disadvantage of gate-first in-tegration approach is that, owing to the requirements of high-temperature compatibility, thereare restrictions on the choice of electrode and gate dielectric materials that can be used, whereasmore materials flexibility is available for the gate-last scheme.

9. DEVICE BENEFITS OF HIGH-κ/METAL GATES

Drive current benefits of short-channel transistors fabricated by use of an optimized FET processhave been realized in both gate-first (13, 14) and gate-last flows (12) compared with drive currentsobtained from traditional SiON/poly-Si transistors. The drive current improvement has largelybeen enabled by Tinv scaling from 1.9 nm to ≤1.4 nm by use of high-κ/metal gates. In particular, fora gate-first flow, nFETs with high-κ/metal gate stacks show >25% improvement in drive currentcompared with the conventional SiO(N)/poly-Si baseline. In addition, because the EOT has beenscaled to <1.1 nm, it enables better electrostatic control of the channel by the gate (the so-calledshort-channel effect). The improvement in the short-channel effect enables the drive currentenhancement to be maintained at a much shorter gate length at constant transistor off currentsand overlap capacitances, thereby showing that high-κ/metal gate stacks can enable continued chipscaling (13). For a low-power 32-nm device, researchers have developed a cost-effective technologywith a single-metal/gate-first process that maintains a low gate leakage of <0.1 A cm−2 at low EOTs(14). Moreover, the strong performance offered by high-κ/metal gates allows for the eliminationof costly strain engineering, which is a common problem for standard SiON/poly-Si.

10. SUMMARY

High-κ/metal gate technology has been the focus of approximately a decade of research anddevelopment to identify and then put into practice replacements for the SiON dielectric and


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the poly-Si electrode. The initial work was centered around identifying high-κ dielectrics thatdid not react with Si and that could offer low leakage currents at low EOT values. A number ofhigh-κ oxides were investigated, with a consensus developing around Hf-based dielectrics in 2001–2002. New observations emerged about the role of oxygen in high-κ oxides: (a) the unanticipatedformation of interfacial Si oxide at the Si/high-κ interface in the case of excess oxygen and (b) theformation of charged oxygen vacancies that result in shifts in the device threshold voltages. Thereplacement of poly-Si with metal gates received an added impetus because the use of poly-Si withHfO2 resulted in MOSFETs with degraded performance. High-temperature-compatible TiN-and TaN-(or carbide-) based metal electrodes were found to be appropriate, primarily becauseof their ability to getter oxygen and prevent oxidation of the Si at the Si/high-κ interface, thusenabling low EOT values of ∼1 nm. These electrodes, however, result in threshold voltages thatare high, owing to their mid-gap-like work function. An important development was the use ofultrathin cap layers based on oxides of highly electropositive metals to shift the threshold voltagesto acceptable limits, an effect believed to be caused by the formation of charge dipoles due to thesecap layers. There are two developed technologies that use high-κ dielectrics and metal gates. Thefirst, developed by IBM and its Alliance partners, is called a gate-first technology and involvesa process in which the entire gate stack withstands the conventional high-temperature CMOSprocess flow. The second, developed by Intel, is called a gate-last technology, in which the processis modified so that the high-κ/metal stack sees a significantly lower temperature. With the adventof high-κ/metal gate technology, future innovations in silicon technology will continue in thearea of new, non-planar Si device architectures such as FINFET, TRIGATE, and Si nanowires.These will be evaluated in conjunction with high-κ/metal stacks for their superior electrostaticscompared to planar Si devices. The goal within high-κ/metal gate research itself will focus onmodified oxides with higher dielectric constants, and better control of the interfacial oxide layer.Additionally, for superior drive current and performance alternate channel materials such as III-Vmaterials for nFETs and Ge for pFETs are being investigated for their inherently higher electronand hole mobilities, respectively. These are difficult challenges and only time will tell as to whetherthese new device and materials innovations make it into high-volume manufacturing or not.

DISCLOSURE STATEMENT

The authors are not aware of any biases that might be perceived as affecting the objectivity of thisreview.

ACKNOWLEDGMENTS

We gratefully acknowledge our many colleagues and collaborators, who through their many ideasand experiments have made high-κ/metal gates a market reality. We especially thank N. Bojarczuk,S.L. Brown, D. Buchanan, C. Cabral Jr., A. Callegari, E. Cartier, T.C. Chen, M.P. Chudzik, M.Copel, B. Doris, M.M. Frank, M. Gribelyuk, E.P. Gusev, H. Jagannathan, P. Jamison, R. Jammy,Y.H. Kim, M. Khare, B.P. Linder, F.R. McFeely, V.K. Paruchuri, J. Schaeffer, Y. Wang, and S. Zafar.

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Annual Review ofMaterials Research

Volume 39, 2009 Contents

Materials Advances for Next-Generation Microelectronics

Molecular ElectronicsJames R. Heath � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � 1

Phase Change MaterialsSimone Raoux � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � �25

Porous pSiCOH Ultralow-k Dielectrics for Chip InterconnectsPrepared by PECVDAlfred Grill � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � �49

Thin-Film Organic Electronic DevicesHoward E. Katz and Jia Huang � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � �71

Immersion Lithography: Photomask and Wafer-Level MaterialsRoger H. French and Hoang V. Tran � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � �93

Materials for Optical Lithography Tool ApplicationHarry Sewell and Jan Mulkens � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � 127

Nanoimprint Lithography Materials Development for SemiconductorDevice FabricationElizabeth A. Costner, Michael W. Lin, Wei-Lun Jen, and C. Grant Willson � � � � � � � � � � � 155

High-κ/Metal Gate Science and TechnologySupratik Guha and Vijay Narayanan � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � 181

Strain: A Solution for Higher Carrier Mobility in NanoscaleMOSFETsMin Chu, Yongke Sun, Umamaheswari Aghoram, and Scott E. Thompson � � � � � � � � � � � � � 203

Size-Dependent Resistivity in Nanoscale InterconnectsDaniel Josell, Sywert H. Brongersma, and Zsolt T´okei � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � 231

Carbon Nanotube InterconnectsAzad Naeemi and James D. Meindl � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � 255

Materials for Magnetoresistive Random Access MemoryJ.M. Slaughter � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � 277

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Current Interest

Chameleon Coatings: Adaptive Surfaces to Reduce Friction and Wearin Extreme EnvironmentsC. Muratore and A.A. Voevodin � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � 297

Doped Oxides for High-Temperature Luminescence and LifetimeThermometryM.D. Chambers and D.R. Clarke � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � 325

Plasticity of Micrometer-Scale Single Crystals in CompressionMichael D. Uchic, Paul A. Shade, and Dennis M. Dimiduk � � � � � � � � � � � � � � � � � � � � � � � � � � � � � 361

Recent Progress in the Study of Inorganic Nanotubes andFullerene-Like StructuresR. Tenne and G. Seifert � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � 387

Recent Progress in Theoretical Prediction, Preparation, andCharacterization of Layered Ternary Transition-Metal CarbidesJingyang Wang and Yanchun Zhou � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � 415

Shape Memory Polymer ResearchPatrick T. Mather, Xiaofan Luo, and Ingrid A. Rousseau � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � 445

Solid-Surface Characterization by WettingAbraham Marmur � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � 473

Index

Cumulative Index of Contributing Authors, Volumes 35–39 � � � � � � � � � � � � � � � � � � � � � � � � � � � 491

Errata

An online log of corrections to Annual Review of Materials Research articles may befound at http://matsci.annualreviews.org/errata.shtml

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High- κ /Metal Gate Science and Technology

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