Full time job in Analog/ Mixed-Signal/ RF IC Design ∆Σ ......... Graduate Electrical Engineering...
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Mansoorali Companywala 615 S Hardy Dr, #216, Tempe, AZ-85281. [email protected] / 602-810-7450 Summary: Graduate Electrical Engineering student seeking an Full time job in Analog/ Mixed-Signal/ RF IC Design. Experienced in transistor level design & layout of Analog & RF IC such as PLL, ∆Σ ADC, Pipeline ADC, Cyclic ADC, VCO, RF Power Amplifiers, LNA, Mixer, Op-Amps, OTA, Bandgap Reference, LDO Regulators & Switched Capacitor Analog Filters. Education: Master of Science in Electrical Engineering August’13 – May ‘15 Arizona State University, Tempe, AZ GPA: 4.0/4.0 Bachelor of Technology in Electronics Engineering July ’08 – May ‘12 Mumbai University, Veermata Jijabai Technological Institute GPA: 8.7/10 Work Experience: Cambridge Silicon Radio (CSR) - Analog/RF IC Design Intern Jan '15 - May '15 • RF Power Amplifier for Bluetooth 5.0 • Verilog AMS modeling of phase noise in PLL for Bluetooth 5.0. • High Speed Dynamic Comparator design in 40nm CMOS process: 3Gsps, (1σ) offset & 24uW power at 1.2V. ON Semiconductor - Analog Design Engineer Intern June '14 – Aug '14 • Fabricated 92dB 1GHz Gain Boosted Amplifier in 0.18um CMOS ONC18 process. - UGBW: 1GHz, DC Gain: 92dB, Phase Margin: 60deg, Power: 5.4mW. Output Swing: 0.6V to 1.5V. Vdd: 1.8V. - Layout in deep n-well process with isolated n-well for clocks, amplifier and switch capacitor circuit. • Pipeline ADC: 11bit ENOB 80Msps 66.6dB SNDR in 0.18um ONC18 process - Montecarlo simulation with process & mismatch shows 3σ variation of ENOB equal to 0.6bits. Fs: 80Msps. Power 50mW. - Utilized above designed 92dB 1GHz Gain Boosted Telescopic Cascode OTA for MDAC stage of ADC. • Cyclic ADC: 8.7bit ENOB 13.33Msps 2 stage in 0.18um ONC18 process. - Montecarlo simulation with process & mismatch shows ENOB 3 sigma variation of 0.8 bits. • Analog bench validation of load current Amplifier and RF receive chain consisting of Common Gate LNA, Mixer, and Differential LC ladder simulated Gm-C Bandpass filter. Cypress Semiconductor - Applications Engineer June’ 12 – June’ 13 • Developed and debugged systems based on USB 3.0 controllers, CapSense Controllers, PowerPSoC and PLC Controllers. • Failure Analysis of Capacitive touch sensing based controller chips and observed the cause of failure as RTN’s (Random Telegraphy Noise). Projects: Sept ’13 –Dec‘14 • RF Power Amplifier design in ADS: Class A-B & Class F with load pull Characterization. • 3-10 GHz Ultra-wide band LNA employing 3-section Chebyshev Bandpass filter for wideband input matching. Noise Figure<5dB, IIP3 >-5dBm, Vdd: 1.8V, Supply Current: 13mA, S21: 16dB, S11 and S22 < -10dB. • 2.4GHz Gilbert Cell Mixer using 0.18um IBM7RF Technology. IIP3: 5dBm, NF: 10dB, Conversion Gain: 10dB, Power: 10mW, S11: -30dB. • 80MHz - 1.6GHz Adaptive Phase Locked Loop. Freq: 80MHz - 1.6GHz, Power: 6mW, Period Jitter: 10ps, Absolute Jitter: 35ps, Cycle-to-Cycle Jitter: 2ps with 50mV square wave supply noise at 1MHz. Layout Area: 0.1mm 2 • Low Drop-out Voltage Regulator: 1.5A 1.25V- 2.5V Design & Post Layout Verification. I(load):0-1.5A, PSRR: 50dB at 10KHz, Vdo: 400mV, CL:1uF, I(Quiescent): 400uA. Loop Gain (Iout: 1.5A): 50dB. Loop Phase Margin: 60 o . Process Corners: SS, FF, TT. Temperature: -40 o C-125 o C. Power down current: 230nA. • Delta Sigma ADC: 92dB /15 bits 100KHz BW 13.5mW in 0.18um CMOS Technology SNDR: 92dB, SFDR: 74dB, Power: 13.5mW, Sampling Frequency: 100MHz, Vdd: 1.8. • Switched Capacitor 6 th order Band pass filter with carrier frequency rejection. Filter attenuation: -50dB at 32.99 KHz, Pass band (2K-20KHz) ripple: +/- 2dB, Low frequency (<1K) roll-off:-40dB/decade, Input impedance: 10M, Power: 13.2mW. • Low Noise Folded Cascode Op-amp with Class AB output stage. DC Gain: 90dB, UGB: 60MHz, PM: 60 o , CMRR: 85dB, PSRR: 85dB, HD3 of -50dB, Input Referred Noise: 6nV/sqHz. • Bandgap Reference. PSRR: 86dB at 0.5 KHz, Vdd: 2.5+/-0.25V, Temperature: -40 o C to 170 o C, Process Corners: SS, FF, TT. • Macro-modeling: Active R-C, Continuous time current mode and Gm-C based Fifth Order Butterworth filter.
Transcript of Full time job in Analog/ Mixed-Signal/ RF IC Design ∆Σ ......... Graduate Electrical Engineering...
Mansoorali Companywala 615 S Hardy Dr, #216, Tempe, AZ-85281. [email protected] / 602-810-7450
Summary: Graduate Electrical Engineering student seeking an Full time job in Analog/ Mixed-Signal/ RF IC Design. Experienced
in transistor level design & layout of Analog & RF IC such as PLL, ∆Σ ADC, Pipeline ADC, Cyclic ADC, VCO, RF Power
Amplifiers, LNA, Mixer, Op-Amps, OTA, Bandgap Reference, LDO Regulators & Switched Capacitor Analog Filters.
Education:
Master of Science in Electrical Engineering August’13 – May ‘15
Arizona State University, Tempe, AZ GPA: 4.0/4.0
Bachelor of Technology in Electronics Engineering July ’08 – May ‘12
Mumbai University, Veermata Jijabai Technological Institute GPA: 8.7/10
Work Experience:
Cambridge Silicon Radio (CSR) - Analog/RF IC Design Intern Jan '15 - May '15
• RF Power Amplifier for Bluetooth 5.0
• Verilog AMS modeling of phase noise in PLL for Bluetooth 5.0.
• High Speed Dynamic Comparator design in 40nm CMOS process: 3Gsps, (1σ) offset & 24uW power at 1.2V.
ON Semiconductor - Analog Design Engineer Intern June '14 – Aug '14
• Fabricated 92dB 1GHz Gain Boosted Amplifier in 0.18um CMOS ONC18 process.
- UGBW: 1GHz, DC Gain: 92dB, Phase Margin: 60deg, Power: 5.4mW. Output Swing: 0.6V to 1.5V. Vdd: 1.8V.
- Layout in deep n-well process with isolated n-well for clocks, amplifier and switch capacitor circuit.
• Pipeline ADC: 11bit ENOB 80Msps 66.6dB SNDR in 0.18um ONC18 process - Montecarlo simulation with process & mismatch shows 3σ variation of ENOB equal to 0.6bits. Fs: 80Msps. Power 50mW.
- Utilized above designed 92dB 1GHz Gain Boosted Telescopic Cascode OTA for MDAC stage of ADC.
• Cyclic ADC: 8.7bit ENOB 13.33Msps 2 stage in 0.18um ONC18 process. - Montecarlo simulation with process & mismatch shows ENOB 3 sigma variation of 0.8 bits.
• Analog bench validation of load current Amplifier and RF receive chain consisting of Common Gate LNA, Mixer, and
Differential LC ladder simulated Gm-C Bandpass filter.
Cypress Semiconductor - Applications Engineer June’ 12 – June’ 13
• Developed and debugged systems based on USB 3.0 controllers, CapSense Controllers, PowerPSoC and PLC Controllers.
• Failure Analysis of Capacitive touch sensing based controller chips and observed the cause of failure as RTN’s (Random
Telegraphy Noise).
Projects: Sept ’13 –Dec‘14
• RF Power Amplifier design in ADS: Class A-B & Class F with load pull Characterization.
• 3-10 GHz Ultra-wide band LNA employing 3-section Chebyshev Bandpass filter for wideband input matching.
Noise Figure<5dB, IIP3 >-5dBm, Vdd: 1.8V, Supply Current: 13mA, S21: 16dB, S11 and S22 < -10dB.
• 2.4GHz Gilbert Cell Mixer using 0.18um IBM7RF Technology.
IIP3: 5dBm, NF: 10dB, Conversion Gain: 10dB, Power: 10mW, S11: -30dB.
• 80MHz - 1.6GHz Adaptive Phase Locked Loop.
Freq: 80MHz - 1.6GHz, Power: 6mW, Period Jitter: 10ps, Absolute Jitter: 35ps, Cycle-to-Cycle Jitter: 2ps with 50mV square
wave supply noise at 1MHz. Layout Area: 0.1mm2
• Low Drop-out Voltage Regulator: 1.5A 1.25V- 2.5V Design & Post Layout Verification.
I(load):0-1.5A, PSRR: 50dB at 10KHz, Vdo: 400mV, CL:1uF, I(Quiescent): 400uA. Loop Gain (Iout: 1.5A): 50dB. Loop Phase
Margin: 60o. Process Corners: SS, FF, TT. Temperature: -40
oC-125
oC. Power down current: 230nA.
• Delta Sigma ADC: 92dB /15 bits 100KHz BW 13.5mW in 0.18um CMOS Technology
SNDR: 92dB, SFDR: 74dB, Power: 13.5mW, Sampling Frequency: 100MHz, Vdd: 1.8.
• Switched Capacitor 6th
order Band pass filter with carrier frequency rejection.
Filter attenuation: -50dB at 32.99 KHz, Pass band (2K-20KHz) ripple: +/- 2dB, Low frequency (<1K) roll-off:-40dB/decade,
Input impedance: 10M, Power: 13.2mW.
• Low Noise Folded Cascode Op-amp with Class AB output stage. DC Gain: 90dB, UGB: 60MHz, PM: 60
o, CMRR: 85dB, PSRR: 85dB, HD3 of -50dB, Input Referred Noise: 6nV/sqHz.
• Bandgap Reference.
PSRR: 86dB at 0.5 KHz, Vdd: 2.5+/-0.25V, Temperature: -40o C to 170
o C, Process Corners: SS, FF, TT.
• Macro-modeling: Active R-C, Continuous time current mode and Gm-C based Fifth Order Butterworth filter.
