FTP02N60C FTA02N60C A Data Sheet ... Semiconductor Co., Ltd (I PS) reserves the right to make...

Features:

Applications:

N-Channel MOSFET

FTP02N60C/FTA10N60C REV. A. Oct. 2007 ©2007 InPower Semiconductor Co., Ltd.

FTP02N60CFTA02N60C

of 9

• Adaptor• TV Main Power• SMPS Power Supply• LCD Panel Power

• RoHS Compliant• Low ON Resistance• Low Gate Charge• Peak Current vs Pulse Width Curve

Lead Free Package and Finish

VDSS RDS(ON) (Max.) ID600 V 4.4Ω 2 A

Ordering Information

PART NUMBER PACKAGE BRAND

FTP02N60C TO-220 FTP02N60C

FTA02N60C TO-220F FTA02N60C

Absolute Maximum Ratings TC=25 oC unless otherwise specified

Symbol Parameter FTP02N60C FTA02N60C Units

VDSS Drain-to-Source Voltage (NOTE *1) 600 V

ID Continuous Drain Current 2.0 2.0*

AID@ 100 oC Continuous Drain Current Figure 3

IDM Pulsed Drain Current, VGS@ 10V (NOTE *2) Figure 6

PDPower Dissipation 70 22 W

Derating Factor above 25 oC 0.37 0.19 W/ oC

VGS Gate-to-Source Voltage ± 30 V

EASSingle Pulse Avalanche EngergyL=10 mH, ID=2.67 Amps

23 mJ

IAS Pulsed Avalanche Rating Figure 8 A

dv/dt Peak Diode Recovery dv/dt (NOTE *3) 3.0 V/ns

TLTPKG

Maximum Temperature for Soldering Leads at 0.063 in (1.6 mm) from Case for 10 seconds Package Body for 10 seconds

300260 oC

TJ and TSTGOperating Junction and StorageTemperature Range

-55 to 150

Thermal Resistance

Symbol Parameter FTP02N60C FTA02N60C Units Test Conditions

RθJC Junction-to-Case 1.78 5.6oC/W

Drain lead soldered to water cooled heatsink, PD ad-justed for a peak junction temperature of +150 oC.

RθJA Junction-to-Ambient 62 100 1 cubic foot chamber, free air.

* Drain Current Limited by Maximum Junction TemperatureCaution: Stresses greater than those listed in the “Absolute Maximum Ratings” Table may cause permanent damage to the device.

Pb

PackagesNot to Scale

SD

GSD

GTO-220 TO-220F

S

G

D

of 9 ©2007 InPower Semiconductor Co., Ltd. FTP02N60C/FTA10N60C REV. A. Oct. 2007

ON Characteristics TJ=25 oC unless otherwise specified

Symbol Parameter Min. Typ. Max. Units Test Conditions

RDS(ON)Static Drain-to-Source On-ResistanceFigure 9 and 10.

-- 3.8 4.4 Ω VGS=10V, ID=1.2A

(NOTE *4)

VGS(TH) Gate Threshold Voltage, Figure 12. 2.0 -- 4.0 V VDS=VGS, ID=250μA

gfs Forward Transconductance -- 1.63 -- SVDS=15V, ID=2A

(NOTE *4)

OFF Characteristics TJ=25 oC unless otherwise specified


BVDSS Drain-to-Source Breakdown Voltage 600 -- -- V VGS=0V, ID=250µA

ΔBVDSS/Δ TJBreakdownVoltage TemperatureCoefficient, Figure 11. -- 0.631 -- V/ oC

Reference to 25 oC, ID=250µA

IDSS Drain-to-Source Leakage Current

-- -- 25

µAVDS=600V, VGS=0V

-- -- 25VDS=480V, VGS=0V

TJ=125 oC

IGSSGate-to-Source Forward Leakage -- -- 100

nAVGS=+30V

Gate-to-Source Reverse Leakage -- -- -100 VGS= -30V

Resistive Switching Characteristics Essentially independent of operating temperature


td(ON) Turn-on Delay Time -- 10 --

ns

VDD=300V

trise Rise Time -- 15 -- ID=2A

td(OFF) Turn-Off Delay Time -- 21 -- VGS=10V

tfall

Fall Time -- 17 -- RG=9.1Ω

Dynamic Characteristics Essentially independent of operating temperature


Ciss Input Capacitance -- 298 --

pF

VGS=0V

Coss Output Capacitance -- 20 -- VDS=25V

Crss Reverse Transfer Capacitance -- 4.8 --f =1.0MHzFigure 14

Qg Total Gate Charge -- 7.8 --

nCVDD=300V

Qgs Gate-to-Source Charge -- 2.0 -- ID=2A

Qgd Gate-to-Drain (“Miller”) Charge -- 5.3 -- Figure 15


Source-Drain Diode Characteristics Tc=25 oC unless otherwise specified


IS Continuous Source Current (Body Diode) -- -- 2 A Integral pn-diode

ISM Maximum Pulsed Current (Body Diode) -- -- 8 A in MOSFET

VSD Diode Forward Voltage -- -- 1.5 V IS=2A, VGS=0V

trr Reverse Recovery Time -- 131 198 ns VGS=0V

Qrr Reverse Recovery Charge -- 454 680 nC IF=2A, di/dt=100 A/µs

Notes:

*1. TJ = +25 oC to +150 oC.

*2. Repetitive rating; pulse width limited by maximum junction temperature.*3. ISD= 2 A, di/dt < 100 A/µs, VDD < BVDSS, TJ=+150 oC.*4. Pulse width < 380µs; duty cycle < 2%.


tp, Rectangular Pulse Duration (s)

TC, Case Temperature (oC)

PD

, Pow

er D

issi

patio

n ( W

)

TC, Case Temperature (oC)

VDS, Drain-to-Source Voltage (V)

0

I D, D

rain

Cur

rent

(A

)

I D, D

rain

Cur

rent

(A

)

RD

S(O

N),

Dra

in-t

o-S

ourc

eO

N R

esis

tanc

e (Ω

)

VGS, Gate-to-Source Voltage (V)

Figure 4. Typical Output Characteristics

1.0

0

1.000

0.100

0.010

0

Maximum Power Dissipationvs Case Temperature

25 5075 100 125 150 2550 75 100 125 150

10E-6 100E-6 1E-3 10E-3 1E+0

NOTES:DUTY FACTOR: D=t1/t2PEAK TJ=PDM x ZθJC x RθJC+TC

20%

10%

5%

2%

single pulse

1%PDM

t1

t2

PULSE DURATION = 250 µS DUTY FACTOR = 0.5%

MAX, TC = 25 oC

Figure 1. Maximum Effective Thermal Impedance, Junction-to-Case

VGS = 5.0V

4.5

4

ID = 4AID = 2AID = 1AID = 0.5A

ZθJ

C, T

herm

al Im

peda

nce

(Nor

mal

ized

)

PULSE DURATION = 10 µSDUTY FACTOR = 0.5% MAXTC = 25 oC

50%

0.001

5.5

4.0

2

1

Figure 2.

0 10 20

4

10 12

1.5

3

30

60

30

6 8 14

VGS = 5.5V

VGS = 6.0V

VGS = 7.0V

VGS = 15V

Duty Factor

1E-60.0001

10E+0100E-3

2.0

2.5

VGS = 6.5V5.0

15

45

75

Figure 3. Maximum Continuous Drain Current vs Case Temperature

Typical Drain-to-Source ON Resistancevs Gate Voltage and Drain Current

Figure 5.

0.5

5 15 25


tp, Pulse Width (s)

I DM

, Pea

k C

urre

nt (

A)

10

VGS, Gate-to-Source Voltage (V)

I D, D

rain

-to-

Sou

rce

Cur

rent

(A

)

tAV, Time in Avalanche (s)

I AS

, Ava

lanc

he C

urre

nt (

A)

10

0.1

ID, Drain Current (A) TJ, Junction Temperature (oC)

RD

S(O

N),

Dra

in-t

o-S

ourc

e

Res

ista

nce

(Nor

mal

ized

)

5.90

3.90

1.90

RD

S(O

N),

Dra

in-t

o-S

ourc

e

ON

Res

ista

nce

(Ω)

4

3

2

0

Figure 7. Typical Transfer Characteristics

100E-6 1E-3 10E-31E-6 10E-6

-75 -50 -25 0 25 50 75 100 125 1500 2 4

3 4

100E-6 1E-3 10E-3 100E-3 1E+0 10E+0

PULSE DURATION = 380 µsDUTY CYCLE = 0.5% MAXVDS = 30 V

STARTING TJ = 25 oC

STARTING TJ = 150 oC

PULSE DURATION = 10 µsDUTY CYCLE = 0.5% MAXVGS = 10V, ID = 2.0A

11.9

9.90

PULSE DURATION = 10 µsDUTY CYCLE = 0.5% MAXTC=25°C

If R= 0: tAV= (L×IAS)/(1.3BVDSS-VDD)

If R≠ 0: tAV= (L/R) ln[IAS×R)/(1.3BVDSS-VDD)+1]

R equals total Series resistance of Drain circuit

1

5 6

1.5

TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION

Figure 6. Maximum Peak Current Capability

+150 oC+25 oC-55 oC

VGS = 10V

4.5

Unclamped InductiveSwitching Capability

Figure 8.

Typical Drain-to-Source ON Resistancevs Junction Temperature

Typical Drain-to-Source ONResistance vs Drain Current

Figure 9.

Figure 10.

3

1

1

6.0

3.0

100

7

7.5

100

VGS

= 10V

FOR TEMPERATURES

ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS:

5

10E-6

5

7.90

I I25150 TC–

125----------------------=

1

6

9.0

10.5


I SD

, Rev

erse

Dra

in C

urre

nt (

A)

C, C

apac

itanc

e (p

F)

I D, D

rain

Cur

rent

(A

)

VG

S(T

H),

Thr

esho

ld V

olta

ge

(Nor

mal

ized

)

TJ, Junction Temperature (oC)

VDS, Drain-to-Source Voltage (V)

VSD, Source-to-Drain Voltage (V)QG , Total Gate Charge (nC)

TJ, Junction Temperature (oC)

1.1

1.0

10

1.0

0.1

12

8

2

0

1.15

1.05

1.00

0.95

0.90

0.7

10

-75 -50 -25 0 25 50 75 100 125 150 -75 -50 -25 50 10075 125 150250

1 10 100 0.1 1 10 100

0 0.2 0.4 0.6 0.8652

4

6

10

VGS = 0V

ID = 250 µA

VGS = VDS

ID = 250 µA

OPERATION IN THIS AREA MAY BE LIMITED BY R

DS(ON)

10µs

Coss

Crss

Ciss

VGS = 0V, f = 1MHz

Ciss = Cgs + CgdCoss ≅ Cds + CgdCrss = Cgd

ID = 2.0A

+150 oC

+25 oC

0

1000 1000

100

1000

VDS, Drain Voltage (V)

0.6

15

VDS = 150V

VDS = 300V

VDS = 450V

BV

DS

S, D

rain

-to-

Sou

rce

Bre

akdo

wn

Vol

tage

(N

orm

aliz

ed)

VG

S, G

ate-

to-S

ourc

e V

olta

ge (

V)

Typical Breakdown Voltage vsJunction Temperature

Typical Threshold Voltage vsJunction Temperature

Figure 11.

Figure 12.

Maximum Forward Bias SafeOperating Area

Figure 13.

Figure 14.

Typical Gate Chargevs Gate-to-Source Voltage

Typical Body Diode TransferCharacteristics

Figure 15.

Figure 16.

1

1 3 4 1.0 1.2

0.9

0.8

1.2

7

25

30

1.10

10.0

Typical Capacitance vs Drain-to-Source Voltage

100µ

1ms

10ms

8 9 1.4

TJ = MAX RATED

TC = 25 oC

VGS = 0V

0.5

100.0 10000

5

20

10


Figure 17. Gate Charge Test Circuit Figure 18. Gate Charge Waveform

Figure 19. Resistive Switching Test Circuit Figure 20. Resistive Switching Waveforms

Test Circuits and Waveforms

VDS

VGS

td(ON) td(OFF)trise tfall

90%

10%

VGS(TH)

Qgs Qgd

VGS

VDSID

Qg

MillerRegion

VDD

VDS

ID

VGS

1 mA

D.U.T.

VDD

VDS

RL

VGS

D.U.T.RG


Figure 21. Diode Reverse Recovery Test Circuit Figure 22. Diode Reverse Recovery Waveform

Figure 23. Unclamped Inductive Switching Test Circuit Figure 24. Unclamped Inductive Switching Waveforms

Test Circuits and Waveforms

ID

Qrr

trr

BVDSS

VGS

IAS

VDD

tp

tAV

2

2LIE AS

AS =

0

VDD

Double Pulse

ID

L

di/dt adj.

D.U.T.

CurrentPump

VDDD.U.T.

BVDSS

IAS

VGS

L

50Ω

Series Switch(MOSFET)

CommutatingDiode

di/dt = 100A/µA


Disclaimers:

InPower Semiconductor Co., Ltd (IPS) reserves the right to make changes without notice in order to improve reliability, functionor design and to discontinue any product or service without notice. Customers should obtain the latest relevant information beforeorders and should verify that such information is current and complete. All products are sold subject to IPS’s terms and conditionssupplied at the time of order acknowledgement.

InPower Semiconductor Co., Ltd warrants performance of its hardware products to the specifications at the time of sale, Testing,reliability and quality control are used to the extent IPS deems necessary to support this warrantee. Except where agreed uponby contractual agreement, testing of all parameters of each product is not necessarily performed.

InPower Semiconductor Co., Ltd does not assume any liability arising from the use of any product or circuit designs describedherein. Customers are responsible for their products and applications using IPS’s components. To minimize risk, customers mustprovide adequate design and operating safeguards.

InPower Semiconductor Co., Ltd does not warrant or convey any license either expressed or implied under its patent rights, northe rights of others. Reproduction of information in IPS’s data sheets or data books is permissible only if reproduction is withoutmodification or alteration. Reproduction of this information with any alteration is an unfair and deceptive business practice.InPower Semiconductor Co., Ltd is not responsible or liable for such altered documentation.

Resale of IPS’s products with statements different from or beyond the parameters stated by InPower Semiconductor Co., Ltdfor that product or service voids all express or implied warrantees for the associated IPS’s product or service and is unfair anddeceptive business practice. InPower Semiconductor Co., Ltd is not responsible or liable for any such statements.

The device is electrostatic sensitive. Proper electrostatic discharge (ESD) protection shall be implemented to avoid damagingthe device.

Life Support Policy:

InPower Semiconductor Co., Ltd’s products are not authorized for use as critical components in life support devices or systems without the expressed written approval of InPower Semiconductor Co., Ltd.

As used herein: 1. Life support devices or systems are devices or systems which: a. are intended for surgical implant into the human body, b. support or sustain life, c. whose failure to perform when properly used in accordance with instructions for used provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

FTP02N60C FTA02N60C A Data Sheet ... Semiconductor Co., Ltd (I PS) reserves the right to make...

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