1

LT1226

Gain of 25 Stable 1GHz Gain Bandwidth 400V/µs Slew Rate 2.6nV/√Hz Input Noise Voltage 50V/mV Minimum DC Gain, RL = 500Ω 1mV Maximum Input Offset Voltage ±12V Minimum Output Swing into 500Ω Wide Supply Range ±2.5V to ±15V 7mA Supply Current 100ns Settling Time to 0.1%, 10V Step Drives All Capacitive Loads

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ESCRIPTIOSFEATUREThe LT1226 is a low noise, very high speed operationalamplifier with excellent DC performance. The LT1226features low input offset voltage and high DC gain. Thecircuit is a single gain stage with outstanding settlingcharacteristics. The fast settling time makes the circuit anideal choice for data acquisition systems. The output iscapable of driving a 500Ω load to ±12V with ±15V suppliesand a 150Ω load to ±3V on ±5V supplies. The circuit is alsocapable of driving large capacitive loads which makes ituseful in buffer or cable driver applications.

The LT1226 is a member of a family of fast, high per-formance amplifiers that employ Linear TechnologyCorporation’s advanced bipolar complementaryprocessing.

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PPLICATI Wideband Amplifiers Buffers Active Filters Video and RF Amplification Cable Drivers Data Acquisition Systems

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PPLICATITYPICAL

Photodiode Preamplifier, AV = 5.1kΩ, BW = 15MHz Gain of +25 Pulse Response

Low Noise Very High SpeedOperational Amplifier

5.1k

LT1226 TA01

–

+LT1226

51Ω

51Ω

V+

LT1226 TA02

LT1226

2

Total Supply Voltage (V+ to V–) ............................... 36VDifferential Input Voltage ......................................... ±6VInput Voltage ............................................................±VSOutput Short Circuit Duration (Note 1) ............ IndefiniteOperating Temperature Range

LT1226C................................................ 0°C to 70°CMaximum Junction Temperature

Plastic Package .............................................. 150°CStorage Temperature Range ................. – 65°C to 150°CLead Temperature (Soldering, 10 sec.)................. 300°C

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PACKAGE/ORDER I FOR ATIO

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VOS Input Offset Voltage (Note 2) 0.3 1.0 mV

IOS Input Offset Current 100 400 nA

IB Input Bias Current 4 8 µA

en Input Noise Voltage f = 10kHz 2.6 nV/√Hz

in Input Noise Current f = 10kHz 1.5 pA/√Hz

RIN Input Resistance VCM = ±12V 24 40 MΩDifferential 15 kΩ

CIN Input Capacitance 2 pF

Input Voltage Range + 12 14 V

Input Voltage Range – –13 –12 V

CMRR Common-Mode Rejection Ratio VCM = ±12V 94 103 dB

PSRR Power Supply Rejection Ratio VS = ±5V to ±15V 94 110 dB

AVOL Large Signal Voltage Gain VOUT = ±10V, RL = 500Ω 50 150 V/mV

VOUT Output Swing RL = 500Ω 12.0 13.3 ±V

IOUT Output Current VOUT = ±12V 24 40 mA

SR Slew Rate (Note 3) 250 400 V/µs

Full Power Bandwidth 10V Peak, (Note 4) 6.4 MHz

GBW Gain Bandwidth f = 1MHz 1 GHz

tr, tf Rise Time, Fall Time AVCL = + 25,10% to 90%, 0.1V 5.5 ns

Overshoot AVCL = +25, 0.1V 35 %

Propagation Delay 50% VIN to 50% VOUT 5.5 ns

ts Settling Time 10V Step, 0.1%, AV = –25 100 ns

Differential Gain f = 3.58MHz, AV = +25, RL = 150Ω 0.7 %

Differential Phase f = 3.58MHz, AV = +25, RL = 150Ω 0.6 Deg

RO Output Resistance AVCL = +25, f = 1MHz 3.1 ΩIS Supply Current 7 9 mA

ELECTRICAL C CHARA TERISTICS VS = ±15V, TA = 25°C, VCM = 0V unless otherwise noted.

1

2

3

4 5

6

7

8

TOP VIEW

NULL

V+

NULL

–IN

OUT

NC

+IN

V–

S8 PACKAGE 8-LEAD PLASTIC SOIC

N8 PACKAGE 8-LEAD PLASTIC DIP

LT1226 PO01

ORDER PARTNUMBER

S8 PART MARKING

1226

LT1226CN8LT1226CS8

3

LT1226

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VOS Input Offset Voltage VS = ±15V, (Note 2) 0.3 1.3 mVVS = ± 5V, (Note 2) 1.0 1.8 mV

Input VOS Drift 6 µV/°C

IOS Input Offset Current VS = ±15V and VS = ±5V 100 600 nA

IB Input Bias Current VS = ±15V and VS = ±5V 4 9 µA

CMRR Common-Mode Rejection Ratio VS = ±15V, VCM = ±12V and VS = ±5V, VCM = ±2.5V 92 103 dB

PSRR Power Supply Rejection Ratio VS = ±5V to ±15V 92 110 dB

AVOL Large Signal Voltage Gain VS = ±15V, VOUT = ±10V, RL = 500Ω 35 150 V/mVVS = ±5V, VOUT = ±2.5V, RL = 500Ω 35 100 V/mV

VOUT Output Swing VS = ±15V, RL = 500Ω 12.0 13.3 ±VVS = ±5V, RL = 500Ω or 150Ω 3.0 3.3 ±V

IOUT Output Current VS = ±15V, VOUT = ±12V 24 40 mAVS = ±5V, VOUT = ±3V 20 40 mA

SR Slew Rate VS = ±15V, (Note 3) 250 400 V/µs

IS Supply Current VS = ±15V and VS = ±5V 7 10.5 mA

VS = ±5V, TA = 25°C, VCM = 0V unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VOS Input Offset Voltage (Note 2) 1.0 1.4 mV

IOS Input Offset Current 100 400 nA

IB Input Bias Current 4 8 µA

Input Voltage Range + 2.5 4 V

Input Voltage Range – –3 –2.5 V

CMRR Common-Mode Rejection Ratio VCM = ±2.5V 94 103 dB

AVOL Large Signal Voltage Gain VOUT = ±2.5V, RL = 500Ω 50 100 V/mVVOUT = ±2.5V, RL = 150Ω 75 V/mV

VOUT Output Voltage RL = 500Ω 3.0 3.7 ±VRL = 150Ω 3.0 3.3 ±V

IOUT Output Current VOUT = ±3V 20 40 mA

SR Slew Rate (Note 3) 250 V/µs

Full Power Bandwidth 3V Peak, (Note 4) 13.3 MHz

GBW Gain Bandwidth f = 1MHz 700 MHz

tr, tf Rise Time, Fall Time AVCL = +25, 10% to 90%, 0.1V 8 ns

Overshoot AVCL = +25, 0.1V 25 %

Propagation Delay 50% VIN to 50% VOUT 8 ns

ts Settling Time – 2.5V to 2.5V, 0.1%, AV = –24 60 ns

IS Supply Current 7 9 mA

ELECTRICAL C CHARA TERISTICS

ELECTRICAL C CHARA TERISTICS

Note 3: Slew rate is measured between ±10V on an output swing of ±12Von ±15V supplies, and ±2V on an output swing of ±3.5V on ±5V supplies.Note 4: Full power bandwidth is calculated from the slew ratemeasurement: FPBW = SR/2πVp.

Note 1: A heat sink may be required to keep the junction temperaturebelow absolute maximum when the output is shorted indefinitely.Note 2: Input offset voltage is tested with automated test equipmentin <1 second.

0°C ≤ TA ≤ 70°C, VCM = 0V unless otherwise noted.

LT1226

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C CHARA TERISTICS

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ATYPICAL PERFOR CE

Output Short Circuit Current vsSupply Current vs Temperature Input Bias Current vs Temperature Temperature

Output Voltage Swing vs Input Bias Current vs Input Open Loop Gain vsResistive Load Common Mode Voltage Resistive Load

Input Common Mode Range vs Output Voltage Swing vsSupply Voltage Supply Current vs Supply Voltage Supply Voltage

SUPPLY VOLTAGE (±V)

00

MAG

NITU

DE O

F IN

PUT

VOLT

AGE

(V)

5

10

15

20

5 10 15 20

LT1226 TPC01

TA = 25°C ∆VOS < 1mV

+VCM –VCM

SUPPLY VOLTAGE (±V)

06.0

SUPP

LY C

URRE

NT (m

A)

6.5

7.0

7.5

8.0

5 10 15 20

LT1226 TPC02

TA = 25°C

SUPPLY VOLTAGE (±V)

00

OUTP

UT V

OLTA

GE S

WIN

G (V

)

5

10

15

20

5 10 15 20

LT1226 TPC03

TA = 25°C RL = 500Ω ∆VOS = 30mV

+VSW

–VSW

LOAD RESISTANCE (Ω)

100

OUTP

UT V

OLTA

GE S

WIN

G (V

p-p)

10

20

25

30

100 1k 10k

LT1226 TPC04

15

5

TA = 25°C ∆VOS = 30mV

VS = ±15V

VS = ±5V

INPUT COMMON MODE VOLTAGE (V)

–153.0

INPU

T BI

AS C

URRE

NT (µ

A)

3.5

4.0

4.5

5.0

–10 0 10 15

LT1226 TPC05

–5 5

VS = ±15V TA = 25°C IB+ + IB– 2IB =

LOAD RESISTANCE (Ω)

1070

OPEN

LOO

P GA

IN (d

B)100

110

120

100 1k 10k

LT1226 TPC06

90

80

TA = 25°C

VS = ±15V

VS = ±5V

TEMPERATURE (°C)

–504

SUPP

LY C

URRE

NT (m

A)

6

7

9

10

–25 25 75 125

LT1226 TPC07

VS = ±15V

100500

5

8

TEMPERATURE (°C)

–5025

OUTP

UT S

HORT

CIR

CUIT

CUR

RENT

(mA)

35

40

50

55

–25 25 75 125

LT1226 TPC09

100500

30

45

VS = ±5V

SINKSOURCE

TEMPERATURE (°C)

–503.5

INPU

T BI

AS C

URRE

NT (µ

A)

4.0

4.25

4.75

5.0

–25 25 75 125

LT1226 TPC08

100500

3.75

4.5

VS = ±15V IB+ + IB– 2IB =

5

LT1226

C CHARA TERISTICS

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ATYPICAL PERFOR CE

Closed Loop Output Impedance vsFrequency Gain Bandwidth vs Temperature Slew Rate vs Temperature

Voltage Gain and Phase vs Frequency Response vsFrequency Output Swing vs Settling Time Capacitive Load

Power Supply Rejection Ratio vs Common Mode Rejection Ratio vsInput Noise Spectral Density Frequency Frequency

FREQUENCY (Hz)1k

0

COM

MON

MOD

E RE

JECT

ION

RATI

O (d

B)

20

40

60

80

100

120

10k 100k 1M 10M

LT1226 TPC12

100M

VS = ±15V TA = 25°C

TEMPERATURE (˚C)–50

GAIN

BAN

DWID

TH (M

Hz)

1.05

1.10

1.15

25 75

LT1226 TPC17

1.0

0.95

–25 0 50 100 125

0.90

0.85

VS = ±15V

FREQUENCY (Hz)100

10

VOLT

AGE

GAIN

(dB)

30

50

70

90

110

1k 10k 100k 1M

LT1226 TPC13

10M 100M0

20

40

60

80

100

PHASE MARGIN (DEGREES)

VS = ±15V

VS = ±5V

TA = 25°C

VS = ±5V

VS = ±15V

TEMPERATURE (˚C)–50

SLEW

RAT

E (V

/µs) 400

450

500

25 75

LT1226 TPC18

350

300

–25 0 50 100 125

250

200

–SR

+SR

VS = ±15V AV = –25

FREQUENCY (Hz)10k

OUTP

UT IM

PEDA

NCE

(Ω)

1

10

100M

LT1226 TPC16

0.1

0.01100k 1M 10M

100VS = ±15V TA = 25°C AV = +25

FREQUENCY (Hz)

INPU

T VO

LTAG

E NO

ISE

(nV/

√Hz)

1

100

10 1k 10k 100k

LT1226 TPC10

100

1000

10

VS = ±15V TA = 25°C AV = +101 RS = 100kΩin

en

0.01

1.0

10

0.1

INPUT VOLTAGE NOISE (nV/√Hz)

FREQUENCY (Hz)100

0

POW

ER S

UPPL

Y RE

JECT

ION

RATI

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B)

40

60

80

100

120

1k 10k 100k 1M

LT1226 TPC11

10M 100M

VS = ±15V TA = 25°C

+PSRR–PSRR

SETTLING TIME (ns)0

OUTP

UT S

WIN

G (V

)

2

6

10

80

–2

–6

–1020 40 60 100 120

LTC1226 TPC14

0

4

8

–4

–8

VS = ±15 TA = 25°C 10mV SETTLING

AV = +25AV = –25

AV = –25

AV = +25

FREQUENCY (HZ)1M

18

VOLT

AGE

MAG

NITU

DE (d

B)

22

26

30

34

38

10M 100M

C = 100pF

C = 0pF

C = 50pF

LT1226 TPC15

20

24

28

32

36 VS = ±15V TA = 25°C AV = –25

C = 1000pF C = 500pF

LT1226

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The LT1226 may be inserted directly into HA2541, HA2544,AD847, EL2020 and LM6361 applications, provided thatthe amplifier configuration is a noise gain of 25 or greater,and the nulling circuitry is removed. The suggested nullingcircuit for the LT1226 is shown below.

Offset Nulling

Layout and Passive Components

As with any high speed operational amplifier, care must betaken in board layout in order to obtain maximum perfor-mance. Key layout issues include: use of a ground plane,minimization of stray capacitance at the input pins, shortlead lengths, RF-quality bypass capacitors located closeto the device (typically 0.01µF to 0.1µF), and use of lowESR bypass capacitors for high drive current applications(typically 1µF to 10µF tantalum). Sockets should beavoided when maximum frequency performance isrequired, although low profile sockets can providereasonable performance up to 50MHz. For more detailssee Design Note 50. Feedback resistors greater than 5kΩare not recommended because a pole is formed with theinput capacitance which can cause peaking. If feedbackresistors greater than 5kΩ are used, a parallelcapacitor of 5pF to 10pF should be used to cancel the inputpole and optimize dynamic performance.

Transient Response

The LT1226 gain bandwidth is 1GHz when measured at1MHz. The actual frequency response in a gain of +25 isconsiderably higher than 40MHz due to peaking caused bya second pole beyond the gain of 25 crossover point. Thisis reflected in the small signal transient response. Highernoise gain configurations exhibit less overshoot as seen inthe inverting gain of 25 response.

Small Signal, AV = +25 Small Signal, AV = – 25

The large signal response in both inverting and noninvert-ing gain shows symmetrical slewing characteristics. Nor-mally the noninverting response has a much faster risingedge due to the rapid change in input common modevoltage which affects the tail current of the input differen-tial pair. Slew enhancement circuitry has been added tothe LT1226 so that the falling edge slew rate is enhancedwhich balances the noninverting slew rate response.

Large Signal, AV = +25 Large Signal, AV = – 25

Input Considerations

Resistors in series with the inputs are recommended forthe LT1226 in applications where the differential inputvoltage exceeds ±6V continuously or on a transient basis.An example would be in noninverting configurations withhigh input slew rates or when driving heavy capacitiveloads. The use of balanced source resistance at each inputis recommended for applications where DC accuracymust be maximized.

Capacitive Loading

The LT1226 is stable with all capacitive loads. This isaccomplished by sensing the load induced output poleand adding compensation at the amplifier gain node. Asthe capacitive load increases, both the bandwidth andphase margin decrease so there will be peaking in the

LT1226 AI03

LT1226 AI02

–

+3

2

18

5k 0.1µF

76

4

0.1µF

V+

V –

LT1226

LT1226 AI01

7

LT1226

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Compensation for Lower Closed-Loop Gains

frequency domain and in the transient response. Thephoto of the small signal response with 1000pF loadshows 55% peaking. The large signal response with a10,000pF load shows the output slew rate being limited bythe short circuit current.

AV = –25, CL = 1000pF AV = +25, CL = 10,000pF

Lag Compensation

VOS Null Loop

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The LT1226 can drive coaxial cable directly, but for bestpulse fidelity the cable should be doubly terminated witha resistor in series with the output.

Compensation

The LT1226 has a typical gain bandwidth product of 1GHzwhich allows it to have wide bandwidth in high gain

configurations (i.e., in a gain of 1000 it will have abandwidth of about 1MHz). The amplifier is stable in anoise gain of 25 so the ratio of the output signal to theinverting input must be 1/25 or less. Straightforward gainconfigurations of +25 or –24 are stable, but there are a fewconfigurations that allow the amplifier to be stable forlower signal gains (the noise gain, however, remains 25 ormore). One example is the inverting amplifier shown in thetypical applications sections below. The input signal has again of –RF/RIN to the output, but it is easily seen that thisconfiguration is equivalent to a gain of –24 as far as theamplifier is concerned. Lag compensation can also beused to give a low frequency gain less than 25 with a highfrequency gain of 25 or greater. The example below has aDC gain of 6, but an AC gain of +31. The break frequencyof the RC combination across the amplifier inputs shouldbe at least a factor of 10 less than the gain bandwidth of theamplifier divided by the high frequency gain (in this case1/10 of 1GHz/31 or 3MHz).

Cable Driving

–

+

200ΩLT1226

330pF

VIN

VOUT

5k

LT1226 TA03

AV = +6, f < 2MHz1k

LT1226 TA04

R2 50Ω

INV

OUTV

R1 1.2k

R3 75 Ω

R4 75Ω

75 CABLEΩLT1226

+

–

–

+RC

LT1226

VIN

VOUT

LT1226 TA05

RIN

RF

RF RIN

AV = – ; RF ≥ 24 × (RIN || RC)

VIN

VOUT

LT1226 TA06

–

+LT1226

300k 300k1

8

10k 10k

25k

25Ω

100pF

100pF

LT1097

–

+AV = 1001

LT1226 AI04

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-tation that the interconnection of circuits as described herein will not infringe on existing patent rights.

LT1226

8 Linear Technology Corporation1630 McCarthy Blvd., Milpitas, CA 95035-7487(408) 432-1900 FAX: (408) 434-0507 TELEX: 499-3977 LINEAR TECHNOLOGY CORPORATION 1992

LT/GP 0692 10K REV 0

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PACKAGE DESCRIPTION8 Package

8-Lead Plastic DIP

TJ MAX θJA

150°C 220°C/W

Dimensions in inches (millimeters) unless otherwise noted.

S8 Package8-Lead Plastic SOIC

1 2 3 4

0.150 – 0.157 (3.810 – 3.988)

8 7 6 5

0.189 – 0.197 (4.801 – 5.004)

0.228 – 0.244 (5.791 – 6.198)

0.010 – 0.020 (0.254 – 0.508)

0.016 – 0.050 0.406 – 1.270

× 45°

0°– 8° TYP

0.008 – 0.010 (0.203 – 0.254)

S8 1291

0.053 – 0.069 (1.346 – 1.753)

0.014 – 0.019 (0.356 – 0.483)

0.004 – 0.010 (0.102 – 0.254)

0.050 (1.270)

BSC

1 2 3 4

8 7 6 5

0.250 ± 0.010 (6.350 ± 0.254)

0.400 (10.160)

MAX

N8 1291

0.009 - 0.015 (0.229 - 0.381)

0.300 – 0.320 (7.620 – 8.128)

0.325+0.025 –0.015+0.635 –0.3818.255( )

0.045 ± 0.015 (1.143 ± 0.381)

0.100 ± 0.010 (2.540 ± 0.254)

0.065 (1.651)

TYP

0.045 – 0.065 (1.143 – 1.651)

0.130 ± 0.005 (3.302 ± 0.127)

0.020 (0.508)

MIN

0.018 ± 0.003 (0.457 ± 0.076)

0.125 (3.175)

MIN

LT1226 SS

1 8NULL

BIAS 1

3 2 –IN+IN BIAS 2

4V–

7V+

6 OUT

TJ MAX θJA

150°C 130°C/W