EVAL-AD7177-2SDZ User Guide - Analog Devices · 2018. 8. 7. · EVAL-AD7177-2SDZ User Guide UG-849...

EVAL-AD7177-2SDZ User GuideUG-849

One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com

Evaluating the AD7177-2 32-Bit, 10 kSPS, Sigma-Delta ADC with

100 μs Settling and Integrated Analog Input Buffers

PLEASE SEE THE LAST PAGE FOR AN IMPORTANT WARNING AND LEGAL TERMS AND CONDITIONS. Rev. A | of 34

FEATURES Full featured evaluation board for the AD7177-2 PC control in conjunction with the system demonstration

platform (SDP), see the EVAL-SDP-CB1Z data sheet for additional information

PC software for control and data analysis (time domain) Standalone capability

EVALUATION KIT CONTENTS EVAL-AD7177-2SDZ evaluation board

AD7177-2 AD717x Eval+ evaluation software (CD) 7 V to 9 V ac-to-dc adapter Plastic screw and washer set

EQUIPMENT NEEDED DC signal source PC running Windows® XP, Windows 8, or Windows 10

GENERAL DESCRIPTION The EVAL-AD7177-2SDZ evaluation kit features the AD7177-2, a 32-bit, 10 kSPS analog-to-digital converter (ADC) with integrated rail to rail analog input buffers, on-board power supply regulation, and an external amplifier section for amplifier evaluation. A 7 V to 9 V ac-to-dc adapter is regulated to 5 V and 3.3 V that supplies the AD7177-2 and supports its components. The EVAL-AD7177-2SDZ evaluation board connects to the USB port of a PC via the EVAL-SDP-CB1Z (SDP-B) controller board.

The AD717x Eval+ software fully configures the AD7177-2 device functionality via an interactive block diagram and a user accessible register interface, and provides dc time domain analysis in the form of waveform graphs, histograms, and associated noise analysis for ADC performance evaluation.

For full specifications, see AD7177-2 data sheet, which must be consulted in conjunction with this user guide when using the evaluation board.

EVAL-AD7177-2SDZ FUNCTIONAL BLOCK DIAGRAM

POWER

STATUSLED

ADSP-BF527LE

D

USB

ON-BOARDNOISE TEST

7V TO 9VVIN

CS

SCLK

DIN

DOUT/RDY

ADP71045V LDO

ADP71185V LDO

ADP71183.3V LDO

ADR4455V VREF

TO AD7177-2REFOUT PIN

SDP-B

AIN0

AIN1

AIN3

AIN4AVSS

CROSSPOINTMULTIPLEXER

AVDD

Σ-∆ ADC

TEMPERATURESENSOR

AVSS

SERIALINTERFACE

AND CONTROL

SYNC

ERRORINPUT/OUTPUT

CONTROL

GPIO0 GPIO1

AVDD1 AVDD2

1.8VLDO

REGCAPA IOVDD

1.8VLDO

REGCAPD

DGND

BUFFEREDPRECISION

REFERENCE

REF+REF–

REFERENCEINPUT

BUFFERS

ANALOGINPUT

BUFFERS

REFOUT

XTAL1 XTAL2/CLKIO

XTAL AND INTERNALCLOCK OSCILLATOR

CIRCUITRYAD7177-2

INTREF

DIGITALFILTER

ADP7182–VE LDOADM660

–2.5VAVSS

OPTION

ADA4528-2IN-AMP

CONFIGURED

ADA4528-2OPEN

CONFIG

AD8475±10V INPUT

OPTION

AMPSURF BOARDCONNECTOR

EXTERNAL ANALOG SIGNALCONDITIONING PLAYGROUND

1328

2-00

1

FROMADP7104 LDO

Figure 1.

http://www.analog.com/

http://www.analog.com/AD7177-2?doc=EVAL-AD7177-2SDZ_UG-849.pdf


http://www.analog.com/EVAL-SDP-CB1Z?doc=EVAL-AD7177-2SDZ_UG-849.pdf

http://www.analog.com/EVAL-AD7177-2SDZ?doc=EVAL-AD7177-2SDZ_UG-849.pdf

















UG-849 EVAL-AD7177-2SDZ User Guide

Rev. A | of 34

TABLE OF CONTENTS Features .............................................................................................. 1 Evaluation Kit Contents ................................................................... 1 Equipment Needed ........................................................................... 1 General Description ......................................................................... 1 EVAL-AD7177-2SDZ Functional Block Diagram ....................... 1 Revision History ............................................................................... 2 EVAL-AD7177-2SDZ Quick Start Guide ...................................... 4

Recommended Quick Start Guide ............................................. 4 Quick Start Noise Test ................................................................. 4

Evaluation Board Hardware ............................................................ 5 Device Description ....................................................................... 5 Hardware Link Options ............................................................... 5 Sockets and Connectors .............................................................. 6 Serial Interface .............................................................................. 7 Power Supplies .............................................................................. 7 Power Supply Configurations ..................................................... 8 Analog Inputs ................................................................................ 8

Reference Options .........................................................................8 Evaluation Board Software Installation ..........................................9

Installing the AD717x Eval+ Software .......................................9 Installing the Eval+ Dependencies ........................................... 10 Setting Up the System for Data Capture ................................. 11

Evaluation Board Software Operation ......................................... 13 Overview of the Main Window ................................................ 13 Configuration Tab ...................................................................... 13 Waveform Tab ............................................................................. 16 Histogram Tab ............................................................................ 18 Modelled Performance Tab ....................................................... 19 Registers Tab ............................................................................... 22 Exiting the Software ................................................................... 22

Evaluation Board Schematics and Artwork ................................ 23 Ordering Information .................................................................... 31

Bill of Materials ........................................................................... 31

REVISION HISTORY 8/2018—Rev. 0 to Rev. A Reorganized Layout ............................................................ Universal Changes to Evaluation Kit Contents Section, Equipment Needed Section, and General Description Section ...................... 1 Changes to Table 1 ............................................................................ 4 Changes to Table 2 ............................................................................ 6 Changes to Single-Supply (Unregulated) Section, Split Supply (Regulated) Section, Split Supply (Unregulated) Section, and Analog Inputs Section ...................................................................... 7 Deleted Software Installation Section, Figure 4, and Figure 5; Renumbered Sequentially ................................................................ 9 Added Installing the AD717x Eval+ Software Section, Figure 4, and Figure 5; Renumbered Sequentially ........................................ 9 Added Figure 6, Figure 7, Installing the Eval+ Dependencies Section, Figure 8, and Figure 9 ..................................................... 10 Added Figure 10, Installing the .NET Framework 3.5 for Windows 8/Windows 10 Section, Figure 11, and Setting Up the System for Data Capture Section .................................................. 11 Added Figure 13, Figure 14, and Figure 15 ................................. 12 Changes to Launching the Software Section .............................. 12 Deleted ADC Reset Section, Functional Block Diagram Section, Pop-Up Button Section, and Channel Configuration Overview Section .............................................................................................. 13 Added Select Product/Evaluation Mode Pane Section, Tutorial Icon Section, Functional Block Diagram and Configuration Pop-Up Buttons Section, and Analog and Digital Supply Voltage Section ................................................................................ 13

Changed Software Operation Section Heading to Evaluation Board Software Operation Section .............................................. 13 Changes to Figure 16, Overview of the Main Window Section, Configuration Tab Section, and External Reference Section ...... 13 Added Register Configuration Summary Section, Reset ADC Section, Menu Bar Section, and Device Error Section .............. 14 Changes to Status Bar Section ....................................................... 14 Added Figure 17, External MCLK Frequency Section, Analog Input Voltage Section, and External SCLK Frequency Section .... 15 Deleted CRC Error Section ........................................................... 16 Added Figure 18 and Sampling Mode Section ........................... 16 Changes to Samples Section, Sample Section, Waveform Graph and Controls Section, Channel Selection Section, Noise Analysis Pane Section, and Analysis Channel Section .............................. 16 Changes to Display Units and Axis Controls Section ............... 17 Changes to Histogram Tab Section, Histogram Graph and Controls Section, and Figure 19 ................................................... 18 Added Figure 20, Modelled Performance Tab Section, Modelled Performance Analysis Channel Section, Filter Profile Graph Section, Filter Rejection Section, and Filter Performance Section .............................................................................................. 19 Added Figure 21, Filter Step Response Section, Step Response Graph Section, Step Configuration Section, Step Response Section, and Graph Units Section ................................................ 20 Added Figure 22, Timing Diagram/Power Section, Estimated Power Consumption Section, and Timing Diagram Section ... 21 Deleted Register Map Tab Section ............................................... 22 Added Registers Tab Section ......................................................... 22

EVAL-AD7177-2SDZ User Guide UG-849

Rev. A | of 34

Changes to Figure 23, Register Tree Section, Register Section, Bitfields Section, Documentation Section, Save and Load Section, and Exiting the Software Section .................................................. 22 Added Evaluation Board Schematics and Artwork Section and Figure 24 ........................................................................................... 23 Added Figure 25 .............................................................................. 24 Added Figure 26 .............................................................................. 25 Added Figure 27 .............................................................................. 26 Added Figure 28 .............................................................................. 27

Added Figure 29 and Figure 30 ..................................................... 28 Added Figure 31 and Figure 32 ..................................................... 29 Added Figure 33 and Figure 34 ..................................................... 30 Added Ordering Information Section, Bill of Materials Section, and Table 4 ....................................................................................... 31 6/2015—Revision 0: Initial Version


Rev. A | of 34

EVAL-AD7177-2SDZ QUICK START GUIDE RECOMMENDED QUICK START GUIDE To set up the evaluation board, take the following steps:

1. Disconnect the SDP-B board from the USB port of the PC.

2. Install the AD717x Eval+ software from the enclosed CD. 3. Restart the PC after installation. 4. Connect the SDP-B board to the EVAL-AD7177-2SDZ

evaluation board, as shown in Figure 2. 5. Fasten the two boards together with the enclosed plastic

screw and washer set. 6. Connect the external 9 V power supply to the J5 connector

of the evaluation board as shown in Figure 2. Set Link LK2 to Position B.

7. Connect the SDP-B board to the PC via the USB cable. For Windows® XP, search for the SDP-B drivers. If prompted by the Windows operating system, choose to automatically search for the SDP-B drivers.

8. Launch the AD717x Eval+ software from the Analog Devices subfolder in the Programs menu.

QUICK START NOISE TEST To test the noise performance, take the following steps:

1. Insert Link LK8 to Link LK12 to initiate the noise performance test mode. In this mode, the analog input channels short to the REFOUT pin.

2. Click Sample to acquire samples from the ADC (see Figure 16).

The Samples text field in the top right corner of the main window sets the number of samples collected in each batch (see Figure 16).

1328

2-00

2

Figure 2. Hardware Configuration, Setting Up the EVAL-AD7177-2SDZ Evaluation Board













Rev. A | of 34

EVALUATION BOARD HARDWARE DEVICE DESCRIPTION The AD7177-2 is a highly accurate, high resolution, multiplexed, 2-/4-channel (fully differential/single-ended) Σ-Δ ADC. The AD7177-2 has a maximum channel-to-channel scan rate of 10 kSPS (100 µs) for fully settled data. The output data rates range from 5 SPS to 10 kSPS. The device includes integrated rail-to-rail analog input and reference input buffers, an integrated precision 2.5 V reference, and an integrated oscillator.

See the AD7177-2 data sheet for complete specifications. Full details for the SDP-B board are available on the SDP-B product page on the Analog Devices website.

HARDWARE LINK OPTIONS See Table 1 for default link options. By default, the EVAL-AD7177-2SDZ is configured to operate from the supplied 9 V ac-to-dc adapter connected to the J5 connector. The 5 V supply required for the AD7177-2 comes from the ADP7118 on-board, low dropout (LDO) regulator. The ADP7118, with a 5 V output voltage, receives its input voltage from the J3 connector or the J5 connector, depending on the position of LK2, and generates a 5 V output.

Table 1. Default Link and Solder Link Options

Link Default Option Description

LK1 A Selects the voltage applied to the power supply sequencer circuit (U3); dependent on AVDD1. Place in Position A if using 5 V supply for AVDD1, or Position B if using 2.5 V supply for AVDD1.

LK2 B Selects the external power supply from Connector J3 (Position A) or Connector J5 (Position B). LK3 to LK7 Not inserted Prior to inserting SL8 to SL11, inserting these links sets up the on-board noise test to short the on-board

amplifiers, U8 and U9. In this mode, all inputs short to REFOUT. LK8 to LK12 Inserted Inserting these links sets up the on-board noise test close to the ADC analog inputs. In this mode, all inputs

short to REFOUT. SL1 A Sets the voltage applied to the AVDD2 pin. Operates using the AVDD1 supply (default). Position B sets the

AVDD2 voltage to the 3.3 V supply from the ADP7118 (3.3 V) (U10) regulator. SL2 A Selects between an external (Position B) or on-board (Position A) AVDD1 source. Supplies AVDD1 from the

ADP7118 (5 V) (U7) (default). SL3 A Selects between an external ((Position B) or on-board (Position A) AVSS source. Supplies AVSS from the ADP7182

(−2.5 V) (U4) (default). SL4 C Connects AIN4 to: A4/J6 (Position A), REFOUT pin on the AD7177-2 (Position B), or AVSS (Position C).

Position B and Position C are used to simplify the input using a single-ended input source. SL5 B Selects between an external or on-board IOVDD source. Supplies IOVDD from the ADP7118 (3.3 V) (U10)

(default). The evaluation board operates with a 3.3 V logic. SL8 A Routes A0 to: AIN0 pin on the AD7177-2 (Position A), Buffer/In-Amp U8 (Position B), Funnel Amp U9 with gain

of 0.8× (Position C), or J10-1 (Position D). SL9 A Routes A2 to: AIN2 pin on the AD7177-2 (Position A), Buffer U12 (Position B), or Funnel Amp U9 with gain of

0.4× (Position C). SL10 A Routes A3 to: AIN3 pin on the AD7177-2 (Position A), Buffer U12 (Position B), or Funnel Amp U9 with gain of

0.4× (Position C). SL11 A Routes A1 to: AIN1 pin on the AD7177-2 (Position A), Buffer/In-amp U8 (Position B), Funnel Amp U9 with gain

of 0.8× (Position C), or J10-7 (Position D). G16 Inserted Sets the on-board in-amp (U8) to a gain of 16. Insert only one of the G16, G32, G64, or G128 links at a time. G32 Not inserted Sets the on-board in-amp (U8) to a gain of 32. Insert only one of the G16, G32, G64, or G128 links at a time. G64 Not inserted Sets the on-board in-amp (U8) to a gain of 64. Insert only one of the G16, G32, G64, or G128 links at a time. G128 Not inserted Sets the on-board in-amp (U8) to a gain of 128. Insert only one of the G16, G32, G64, or G128 links at a time. R49 to R51 Inserted Connects AVSS and AGND for single-supply operation. To operate in split supply mode, remove these links.










http://www.analog.com/ADP7118?doc=EVAL-AD7177-2SDZ_UG-849.pdf












Rev. A | of 34

SOCKETS AND CONNECTORS

Table 2. Connector Details

Connector Function Connector Type Manufacturer Manufacturer Number Stock Code1

J1 Connector to the SDP-B 120-way connector, 0.6 mm pitch

Hirose FX8-120S-SV(21) FEC1324660

J2 External MCLK input Straight PCB mount SMB/SMA jack

TE Connectivity 1-1337482-0 Not applicable

J3 External bench top voltage supply for the EVAL-AD7177-2SDZ

Power socket block, 3-pin, 3.81 mm pitch

Phoenix Contact

MC 1.5/3-G-3.81 FEC3704737

J5 External ac-to-dc adapter input for the EVAL-AD7177-2SDZ, 7 V to 9 V

DC power connectors, 2 mm SMT power jack

Lumberg 161314 FEC1243245

J6 Analog input terminal block; wired connection to external source or sensor

Power socket block, 8-pin, 3.81 mm pitch

Phoenix Contact

MC 1.5/8-G-3.81 FEC3704774

J9 External bench top voltage supply option for AVDD1/AVDD2, IOVDD, and AVSS inputs on the AD7177-2

Screw terminal block, 3.81 mm pitch

Phoenix Contact

1727036 FEC3704592

J10 Optional header 7-way, 2.54 mm pin header

Samtec SSW-107-01-T-S FEC1803478

J13 Optional header 7-way, 2.54 mm socket

Samtec TLW-107-05-G-S FEC1668499

A0 to A4 Analog inputs to ADC Straight PCB mount SMB/SMA jack

TE Connectivity 1-1337482-0 Not applicable

A7 PMOD-compatible header 6-Pin single inline (SIL) header (0.1 inch pitch)

Harwin 20-9990646 FEC 1022255

1 FEC stands for Farnell Electronic Component Distributors.








Rev. A | of 34

SERIAL INTERFACE The EVAL-AD7177-2SDZ evaluation board connects to the Blackfin® ADSP-BF527 on the SDP-B via the serial peripheral interface (SPI). The SPI has four primary signals: the CS, SCLK, and DIN input signals, and the DOUT/RDY output signal.

To operate the evaluation board in standalone mode, disconnect the evaluation board from the SDP-B controller board. Use the test points to connect the signals to an alternative digital capture setup or the PMOD-compatible header (A7).

POWER SUPPLIES Power the evaluation board from the ac-to-dc adapter connected to J5, or from an external bench top supply applied to J3 or J9. Linear LDOs generate the required voltages from the applied input voltage (VIN) rail when using J3 or J5. Use J9 to bypass the on-board regulators. An ADP7118 regulator generates the 5 V (single supply) and 2.5 V (split supply) supplies for the AVDD1 and AVDD2 rails to the ADC; a second ADP7118 generates 3.3 V for the IOVDD rail. The ADP7104 supplies +5 V for the SDP-B controller board, as well as +5 V for the ADM660 voltage converter to generate −5 V to supply the ADP7182. The ADP7182 generates the −2.5 V supply for AVSS when operating in split supply mode. Each supply is decoupled where it enters the board and at each device in accordance with the schematics shown in Figure 24 to Figure 28. Table 3 shows the various power supply configurations available, including split supply operation.

Table 3. Power Supply Configurations1 Configuration Input Voltage Range Description Single Supply

(Regulated) 7 V to 9 V The 7 V to 9 V input is regulated to 5 V for AVDD1/AVDD2 and 3.3 V for IOVDD. This input

also powers the external 5 V reference. See the Single Supply (Regulated) section in the Power Supply Configurations section.

Single Supply (Unregulated)

7 V to 9 V, 5 V, and 3.3 V The input is unregulated and connects directly to AVDD1/AVDD2 and IOVDD from J5. The 7 V to 9 V input powers the external 5 V reference. See the Single Supply (Unregulated) section in the Power Supply Configurations section.

Split Supply (Regulated)

7 V to 9 V The 7 V to 9 V input is regulated to +2.5 V for AVDD1/AVDD2, −2.5 V for AVSS and +3.3 V for IOVDD. The 7 V to 9 V input powers the external 5 V reference. See the Split Supply (Regulated) section in the Power Supply Configurations section.

Split Supply (Unregulated)

+7 V to +9 V, ±2.5 V, and +3.3 V

The input is unregulated and connects directly to AVDD1/AVDD2 and IOVDD from J5. The 7 V to 9 V input powers the external 5 V reference. See the Split Supply (Unregulated) section in the Power Supply Configurations section.

1 Only one configuration can be used at a time.



http://www.analog.com/ADSP-BF527?doc=EVAL-AD7177-2SDZ_UG-849.pdf





http://www.analog.com/adp7104?doc=EVAL-AD7177-2SDZ_UG-849.pdf


http://www.analog.com/ADM660?doc=EVAL-AD7177-2SDZ_UG-849.pdf




Rev. A | of 34

POWER SUPPLY CONFIGURATIONS Single Supply (Regulated)

There are two available power supply options for the single supply (regulated) configuration.

• An ac-to-dc adapter (included) connected to J5. Set LK2 to Position B.

• A bench top power supply connected to J3. Set LK2 to Position A, and ensure that AVSS = AGND = 0 V.

Set all other links and solder links to the default settings as outlined in Table 1.

Single Supply (Unregulated)

To set up the evaluation board, use the following procedure:

1. Move SL2 to Position B and move SL5 to Position A. 2. Connect the two terminals of J9 labeled AGND and AVSS. 3. Connect 0 V (GND) to J9 at the terminal labeled AGND. 4. Connect 5 V to J9 at the terminal labeled AVDD. 5. Connect 3.3 V to J9 at the terminal labeled IOVDD. 6. Connect the 7 V to 9 V input to J5.


Split Supply (Regulated)

To set up the evaluation board, use the following procedure:

1. Remove R49 to R52. These links connect AVSS to AGND. 2. Insert a 0 Ω resistor at R67 and R85. 3. Set LK1 to Position B, which sets the input to the power

monitor circuitry to work with the lower AVDD1 supply of 2.5 V.

4. Connect a bench top power supply to J5 and set LK2 to Position B.

5. Set LK1 to Position B, which sets the input to the power monitor circuitry to work with the lower AVDD1 supply of 2.5 V.


Split Supply (Unregulated)

To set up the EVAL-AD7177-2SDZ evaluation board, use the following procedure:

1. Move SL2 and SL3 to Position B and move SL5 to Position A. 2. Remove R49 to R52. 3. Insert a 0 Ω resistor at R67 and R85. 4. Connect 0 V (GND) to J9 at the terminal labeled AGND. 5. Connect 2.5 V to J9 at the terminal labeled AVDD. 6. Connect −2.5 V to J9 at the terminal labeled AVSS. 7. Connect 3.3 V to J9 at the terminal labeled IOVDD. 8. Connect 7 V to 9 V to J5. 9. Set LK1 to Position B. This sets the input to the power

monitor circuitry to work with the lower AVDD1 supply of 2.5 V.

Set all other links and solder links set to the default settings as outlined in Table 1.

ANALOG INPUTS The primary analog inputs of the EVAL-AD7177-2SDZ evaluation board can be applied in two separate ways.

• J6 connector on the left side of the board • A0 to A4 SMB/SMA footprints on the evaluation board

The analog inputs route directly to the associated analog input pins on the AD7177-2, provided that the LK5 to LK9 links (on-board noise test) are removed. The AD717x Eval+ software is set up to analyze dc inputs to the ADC. The AD7177-2 input buffers work for dc input signals.

REFERENCE OPTIONS The EVAL-AD7177-2SDZ evaluation board includes an external 5 V reference, the ADR445. The AD7177-2 includes an internal 2.5 V reference. The default operation is to use the external reference input, which is set to accept the 5 V ADR445 on the evaluation board.









http://www.analog.com/adr445?doc=EVAL-AD7177-2SDZ_UG-849.pdf


http://www.analog.com/adr445?doc=EVAL-AD7177-2SDZ_UG-849.pdf


Rev. A | of 34

EVALUATION BOARD SOFTWARE INSTALLATION Install the AD717x Eval+ software before connecting the evaluation board and the SDP-B board to the USB port of the PC to ensure that the evaluation system is correctly recognized when connected to the PC.

There are two parts to the software installation, noted by the following:

1. AD717x Eval+ software installation 2. AD717x Eval+ Dependencies installation

a. SDP-B board drivers b. Ssrc SVG plug-in c. Microsoft .NET Framework 3.5

INSTALLING THE AD717x Eval+ SOFTWARE To install the AD717x Eval+ software, take the following steps:

1. Ensure that the SDP-B board is disconnected from the USB port of the PC and insert the CD into the CD-ROM drive.

2. Double click the setup.exe file to begin the evaluation board software installation. The default installation location for the software is C:\Program Files\Analog Devices\ AD717x Eval+\.

3. A dialogue box appears asking for permission to allow the program to make changes to the PC (See Figure 3). Click Yes.

1328

2-00

3

Figure 3. User Account Control Dialog Box

4. Select a location to install the software and click Next>>. Figure 4 shows the default locations displayed when the dialogue box opens. To select another location click Browse.

1328

2-10

4

Figure 4. Selecting the Location for Software Installation

5. A license agreement appears. Read the agreement, select I accept the License Agreement, and click Next>> (see Figure 5).

1328

2-10

5

Figure 5. Accepting the License Agreement





Rev. A | of 34

6. A summary of the installation displays. Click Next>> to continue (see Figure 6).

1328

2-10

6

Figure 6. Reviewing a Summary of the Installation

7. The message shown in Figure 7 appears when the installation is complete.

1328

2-10

7

Figure 7. Installation Complete Window

INSTALLING THE Eval+ DEPENDENCIES After the installation of the evaluation software is complete, a welcome window displays to install the Eval+ Dependencies.

1. Ensure that the SDP-B board is still disconnected from the USB port of the PC and that all other applications are closed, and then click Install (see Figure 8).

1328

2-10

8

Figure 8. Beginning the Drivers Installation

2. The Ssrc SVG plug-in installs first, then the SDP-B drivers, and finally, the .NET Framework 3.5.

3. If using Windows 8 or Windows 10, see the Installing .NET Framework 3.5 for Windows 8/Windows 10 section.

4. To complete the SDP-B drivers installation and close the installation setup wizard, click Close (see Figure 9).

1328

2-10

9

Figure 9. Completing the Drivers Setup Wizard





Rev. A | of 34

5. Before using the evaluation board, restart the PC (see Figure 10).

1328

2-11

0

Figure 10. Restarting the PC

Installing .NET Framework 3.5 for Windows 8/Windows 10

Windows 8 and Windows 10 have a built in installer for the .NET Framework 3.5. To run this installer, an internet connection is required, and administrator privileges can be required. Contact a system administrator if the following steps do not work.

1. When the Eval+ Dependencies installer reaches the .NET Framework 3.5 installation step, a window appears, as shown in Figure 11.

1328

2-11

1

Figure 11. Windows 8/Windows 10 .NET Framework 3.5 Installation

2. Follow the steps shown in the installation wizard to complete the installation.

3. If the window shown in Figure 11 does not appear, the .NET Framework 3.5 may already be installed on the PC. To confirm that the software is installed, open the Control Panel > Programs > Programs and Features, and then select Turn Windows features on or off. In the pop up window, find .NET Framework 3.5 and confirm that the software is enabled.

SETTING UP THE SYSTEM FOR DATA CAPTURE After completing the steps in the Installing the AD717x Eval+ Software section and the Installing the Eval+ Dependencies section, take the following steps to set up the system for data capture:

1. Connect the SDP-B board to the PC and allow the Found New Hardware Wizard to run. If using Windows XP, search for the SDP-B drivers and choose to automatically search for the drivers if prompted by the operating system.

2. Use the Device Manager to confirm that the board is properly connecting to the PC.

3. Access the Device Manager by completing the following steps: a) From the Start menu, right-click My Computer and

then click Manage. b) A dialog box appears asking for permission to allow

the program to make changes to the PC. Click Yes. c) The Computer Management window appears. Click

Device Manager from the list of System Tools (see Figure 12).

d) The SDP-B board appears under ADI Development Tools, indicating that the driver software has installed and the board is connecting to the PC properly.

1328

2-11

2

Figure 12. Device Manager





Rev. A | of 34

Launching the Software After completing the steps in the Setting Up the System for Data Capture section, take the following steps to launch the AD717x Eval+ software:

1. From the Start menu, click Programs > Analog Devices > AD717x EVAL+ > AD717x Eval+.

2. The dialogue box in Figure 13 appears; select AD7177-2 Evaluation Board and click the Select button. The main window of the software box displays as shown in Figure 16.

1132

82-1

13

Figure 13. AD7177-2 Evaluation Board Selection

3. If the EVAL-AD7177-2SDZ evaluation system is not connected to the USB port via the SDP-B when the software is launched, the software displays the dialog box shown in Figure 14. Connect the evaluation board to the USB port of the PC; wait a few seconds, click Refresh and the option shown in Figure 13 appears.

1267

8-11

4

Figure 14. Evaluation Board Selection, No Board Connected

4. The AD717x Eval+ software can also be used without connecting hardware. Click the Simulation button and the options shown in Figure 15 appear. This option uses a software model and allows the AD7172-2, AD7172-4, AD7173-8, AD7175-2, AD7175-8, AD7176-2, or AD7177-2 to be evaluated.

1328

2-11

5

Figure 15. Evaluation Board Selection Simulation

http://www.analog.com/EVAL-AD7175-2?doc=EVAL-AD7175-2SDZ_UG-741.pdf

http://www.analog.com/EVAL-AD7175-2?doc=EVAL-AD7175-2SDZ_UG-741.pdf










Rev. A | of 34

EVALUATION BOARD SOFTWARE OPERATION

1328

2-11

6

Figure 16. Configuration Tab of the AD717x Eval+ Software in Hardware Mode

OVERVIEW OF THE MAIN WINDOW The main window of the AD717x Eval+ software displays the significant control buttons and analysis indicators of the AD717x Eval+ software. This window is divided into five tabs: Configuration, Waveform, Histogram, Modelled Performance, and Registers.

CONFIGURATION TAB Figure 16 shows the Configuration (1) tab when Hardware mode is selected and Figure 17 shows the Configuration tab when Simulation mode is selected. The controls highlighted in Figure 17 are only available in Simulation mode.

Select Product/Evaluation Mode Pane

The Evaluation Mode (2) pane displays the evaluation mode in use. To switch between modes, click the Select Product… button, and the dialog box shown in Figure 13 appears.

Tutorial Icon

Click the tutorial icon (3) to open a tutorial and view additional information on using the AD717x Eval + software.

Functional Block Diagram and Configuration Pop-Up Buttons

The functional block diagram (4) of the ADC shows each of the separate functional blocks within the ADC. Click a configuration button (5) on any of the functional blocks to open the configuration pop-up window for the block selected. Not all blocks have a configuration button.

Analog and Digital Supply Voltage

The text fields labeled 6, 7, and 14 in Figure 16 and Figure 17 are input fields that are used to take the supply voltage levels selected for the AD7177-2. Checks are performed to ensure that the power supply voltage levels entered are within the specified limits. These power supply voltage levels are also used for the modelled performance to calculate the power dissipation.

External Reference

The Ext. REF-(V) and Ext. REF+(V) (8) text fields set the positive and negative external reference voltage values. The difference of these fields is used to calculate the results for both the Waveform and Histogram tabs. The evaluation board has an external 5 V ADR445 reference, which can be bypassed by removing R32. Change the external reference voltage value in the external reference text fields to ensure the correct calculation of results in the Waveform and Histogram tabs.


http://www.analog.com/ADR445?doc=EVAL-AD7177-2SDZ_UG-849.pdf


Rev. A | of 34

Register Configuration Summary

Click the Summary (9) button to display the selected configuration of the AD7177-2, which includes channel configuration, information on each of the individual setups, as well as, information on any error present.

Reset ADC

Click the Reset ADC (10) button to perform a software reset of the AD7177-2. The AD7177-2 does not have a hardware reset pin. To perform a hard reset, the power must be removed from the AD7177-2. The software reset has the same effect as a hard reset.

Menu Bar

The menu bar (11) has three sections: File, Edit, and Help.

File

Three options are available in the File menu: Save, Load, and Exit.

The Save option allows the user to save register configurations or waveform data. Register configurations can be saved as a JavaScript Object Notation (JSON) file or a header file. If the configuration is only used in the AD717x Eval+ software environment, it is recommended to use the JSON setting. Waveforms are saved as .csv files and the user is prompted to save the register configuration.

The Load option allows the user to load saved register configurations or waveform data. To load a header file into the AD717x Eval+ software, the file must be in the same format as the file that is saved from the AD717x Eval+ software. The header file can be used when developing firmware. When loading the waveform data, the user is prompted to load the register configuration. This step is so the software can correctly analyze the data.

Click Exit to close the AD717x Eval+ software.

Edit

There are two options available in the Edit dropdown menu, Change Product Selection and Reset ADC. The Change Product Selection option performs the same action as the

Select Product button and Reset ADC performs the same action as the Reset ADC button.

Help

The Help dropdown menu provides links to extra information about the AD7177-2, which includes links to the product page, the evaluation board user guide, the datasheet, and the No-OS Drivers.

Selecting the AD717x Eval+ Tutorial

To open this tutorial, click the tutorial icon (3). For details on the version of the software, the About option opens a dialog box displaying the current version of the software and the relevant licenses.

Status Bar

The status bar (12) displays the busy indicator and status updates, such as Analysis Completed and Reset Completed during software use.

Device Error

The Device Error (13) LED icon illuminates when a when an ADC error is detected or when a cyclic redundancy check (CRC) error occurs. The CRC functionality on the AD7177-2 is disabled by default and must be enabled for this indicator to work. More specific information on the error can be found in the Register Configuration Summary section.








Rev. A | of 34

1328

2-11

7

Figure 17. Configuration Tab of the AD717x Eval+ Software in Simulation Mode

External MCLK Frequency

The Ext. MCLK(Hz) text field (15) sets the external MCLK frequency. The Ext. MCLK(Hz) control is only visible in the Configuration tab when an external clock source is selected by the ADC. The value entered in this field is used by the functional model shown in the Modelled Performance tab.

Analog Input Voltage The input fields shown in the Simulated Input pane (16) are only available when the AD717x Eval+ software is executed in simulation mode. These simulated inputs allow the analog input voltages to be set and can be changed at any time when the device is in simulation mode.

External SCLK Frequency The SCLK(Hz) text field (17) sets the external SCLK frequency for the SPI interface. This text field is only available in simulation mode to determine if the SCLK frequency is within the permitted range.


Rev. A | of 34

1328

2-11

8

Figure 18. Waveform Tab of the AD717x Eval+ Software

WAVEFORM TAB Figure 18 shows the Waveform tab (18) of the AD717x Eval+ Software.

Sampling Mode

The Sampling Mode control (19) is unrelated to the ADC mode. This control can be set to capture a defined sample set (single capture), or continuously gather batches of samples (repeated capture). The user can also select data logging, which runs in a similar manner to the repeated capture option; however, selecting data logging posts the results to a .csv file. When saving the results, the .csv file prompts the user to save the register configuration, which is necessary to load the analysis of the data back into the software.

Samples

The Samples text field (20) sets the number of samples gathered per batch. The Single Capture option selected from the Sampling Mode dropdown list returns the number of samples entered in the Samples text field. The Repeated Capture option continues to return batches of the number entered in the Samples text field until sampling is stopped by the user.

Sample

Click the Sample button (21) to start gathering ADC results. Results appear in the waveform graph (22).

Waveform Graph and Controls

The waveform graph (22) shows each successive sample of the ADC output. Zoom in on the data using the control toolbar (23). Click the x-axis and y-axis to change the scales on the graph.

Channel Selection

The channel selection control (24) allows the user to choose which channels display on the data waveform graph. These controls only affect the display of the channels and do not have any effect on the channel settings in the ADC register map.

Noise Analysis Pane

The Noise Analysis pane (25) displays the results of the noise analysis for the selected analysis channel; this includes both noise and resolution measurements.


Rev. A | of 34

Analysis Channel

The noise analysis dropdown list (26) and histogram graph show the analysis of the channel selected.

Display Units and Axis Controls

I In the Graph Configuration pane (27), select the Units: V/mV/uV/nV dropdown menu to select the unit that the data displays in the graph. This control affects the waveform graph and the histogram graph. The axes controls can be switched between dynamic and fixed. When the dynamic control is selected, the axes automatically adjust to show the entire range of the ADC results after each batch of samples. When fixed is selected, the user can program the axes ranges. These ranges do not automatically adjust after each batch of samples.


Rev. A | of 34

HISTOGRAM TAB Figure 19 shows the Histogram tab (28) of the AD717x Eval+ software.

Histogram Graph and Controls

The histogram graph (29) shows the number of times each sample of the ADC output occurs. The control toolbar (30) in the histogram graph allows you to zoom in on the data (see Figure 19). Click the x-axis and y-axis to change the scales on the graph.

1328

2-11

9

Figure 19. Histogram Tab of the AD717x Eval+ Software


Rev. A | of 34

1328

2-12

0

Figure 20. Filter Profiles of the AD717x Eval+ Software

MODELLED PERFORMANCE TAB The Modelled Performance tab (31) shows a number of ADC performance parameters, which are calculated using the ADC functional model.

There are three main options in the Modelled Performance tab: Filter Profile, Filter Step Response, and Timing Diagram/Power. These options can be selected from the dropdown list (33). Figure 20 shows this tab when Filter Profile is selected.

Analysis Channel

The analysis channel dropdown list (32) selects the channel to be evaluated by the functional model.

Filter Profile Graph

This graph (34) shows the frequency response for the selected digital filter. The graph controls allows the user to zoom in on the data. Click the x-axis and y-axis to change the scales on the graph.

Filter Rejection

The Filter Rejection pane (35) shows the rejection/attenuation of the digital filter over the rejection bandwidth for f1 and f2 in decibels. The f1, f2, and Bandwidth values can be changed.

Filter Performance

The Filter Performance pane (36) shows timing information for the data rate of the selected output. This pane shows the ADC initial settling time (Tsettle), the first frequency notch (Fnotch), and the actual sampling frequency (fADC).


Rev. A | of 34

1328

2-12

1

Figure 21. Filter Step Response of the AD717x Eval+ Software

Filter Step Response

The Filter Step Response dropdown list (37) allows the user to switch between the three sections of the Modelled Performance tab. Figure 21 shows this tab when Filter Step Response is selected from the dropdown list.

Step Response Graph

This graph (38) shows how long the filter takes to settle when the voltage is stepped from one voltage to the next. For this analysis, it is assumed the ADC is continuously converting on only one channel.

Step Configuration

The controls in the Step Configuration pane (39) allow the user to set the voltage before and after the step, as well as the step position. The Step Position text field is set as a percentage where 0% is 1/fADC and 100% is 2/fADC.

Step Response

The controls in the Step Response pane (40) provide timing information for the data rate of the selected output. This pane shows the actual sampling frequency (fADC), the ADC initial settling time (Tsettle), and the settling time between conversions (1/fADC).

Graph Units

Use the controls in the Graph Units pane (41) to switch the step response between Percentage, Volts, and Codes.


Rev. A | of 34

1328

2-12

2

Figure 22. Timing Diagram/Power of the AD717x Eval+ Software

Timing Diagram/ Power

This dropdown list (42) allows the user to switch between the three sections of the Modelled Performance tab. Figure 22 shows the tab when Timing Diagram/Power is selected from the dropdown list.

Estimated Power Consumption

The Estimated Power Consumption pane (43) shows the total power consumption of the device in the selected configuration, as well as the current consumption on each of the power supply

rails. Note that the estimated power consumption is for continuous conversion mode, only. No other mode of operation is supported by this control.

Timing Diagram

The graph shown in the Timing Diagram pane (44) shows the digital interface timing diagram for the current configuration. The graph shows the timing for the configuration of the ADC and the subsequent data reads from the ADC.


Rev. A | of 34

1328

2-12

3

Figure 23. Registers Tab of the AD717x Eval+ Software

REGISTERS TAB Figure 23 shows the Registers tab (45).

Register Tree

This register list control (46) shows the full register map in a tree control format. Each register is shown; click the expand button next to each register to show all of the bit fields contained within that register.

Register

The Register pane (47) allows the user to change the individual bit of the register selected in the register tree by clicking the bits or by entering the register value directly into the text field on the right side of the pane.

Bitfields

The Bitfields pane (48) shows the bit fields of the register selected in the register tree. Change the values in this pane by using the Setting dropdown lists or by directly entering a value into the value text fields.

Documentation

The Documentation pane (49) contains the documentation for the register or bit field selected in the register tree.

Save and Load

The Save (50) and Load (51) buttons allow the user to save the current configuration of the AD7177-2 by saving the register map settings to a file and loading the settings from the same file. When using these buttons, the register configurations are saved and loaded as JSON files.

EXITING THE SOFTWARE To exit the software, click the close button at the top right corner of the AD717x Eval+ software.11B11B



Rev. A | of 34

EVALUATION BOARD SCHEMATICS AND ARTWORK

VOLT

AG

E R

EF

AD

C

DIG

ITA

L IN

TER

FAC

E

GPI

O R

EF T

O 5

V A

NA

LOG

PR

OVI

SIO

N F

OR

VO

LTA

GE

DIV

IDER

FO

R L

OW

VO

LTA

GES

REF

– EX

T

REF

+ EX

T

CO

NN

ECTO

R:

AD

C IN

TER

NA

L C

LOC

K O

UTP

UT

OR

AN

EXT

ERN

AL

CLO

CK

INPU

T

MC

LK

INTE

RN

AL

REF

OU

T

SOLD

ER L

INK

DEF

AU

LT A

SET

SL1

TO A

.SE

TTIN

G A

VDD

2 =

3.3.

V IS

NO

T A

LLO

WED

WH

EN A

VDD

1 =

2.5V

AN

D A

VSS

= -2

.5V.

CO

MPE

NSA

TIO

N O

PTIO

NFO

R A

DR

445

1206

PLA

CEH

OLD

ERS

AIN

0

AIN

1

AIN

2

AIN

3

AIN

4PM

OD

PIN

6 =

NO

CO

NN

ECT

C17

4.7µ

F

R29

R30

0Ω

R28

R27

0Ω

21A

IN0

22A

IN1

23A

IN2

24A

IN3

1A

IN4

2R

EF–

3R

EF+

4R

EFO

UT

14C

S

13SC

LK

11D

OU

T/R

DY

12D

IN

15SY

NC

/ER

R

19 GPI

O0

20 GPI

O1

9XT

AL1

10C

LKIO

/XTA

L2

7A

VDD

1

5R

EGC

APA

8A

VDD

2

6

AVS

S

18R

EGC

APD

16IO

VDD

17D

GN

D

U5

AD

7175

_2

R39

10Ω

R34

10Ω

R46

10Ω

R47

10Ω

R41 0Ω

C25

DN

I

C21

0.1µ

F

R13

0Ω

R12

0Ω

R11

0Ω

R10

0Ω

R9

0Ω

TSYN

C

TCS

TSC

LK

TDIN

TDO

UT

R31

SET

RC

BA

SED

ON

REF

ZIN

C16

DN

I

R40 0Ω

A6

C24 DN

I

C54

0.1µ

FC

220.

1µF

A5

R32 0Ω

REF

+

REF

–

C44

0.1µ

F

C12

0.1µ

F

C53

0.1µ

F

C56 1µFC

57 1µFC14

0.1µ

F

L2 1000

Ω

C58

0.1µ

F

J2

C10 DN

IC

11 DN

I

Y116

MH

Z

R26

C13

0.1µ

F

R33

C18

0.1µ

FR

88

DN

P

R89 0Ω

GPI

O0

GPI

O1

GN

D1

GN

D2

GN

D3

CBASL4

GN

D4

GN

D5

GN

D6

R5

10kΩ

1 2 3 4 5 6 7 8

J8

SREWTERM-8_RA

1 2 3 4 5 6 7 8

J6

GN

D

LK3

R6

10kΩ

A BSL1

C3

4.7µ

F

C15 1µF

C20

0.1µ

F

TXTA

L1

TXTA

L2

1TP

1

2+V

IN

3N

C

4G

ND

5TR

IM

6VO

UT

7N

C

8TP

8

U6

AD

R44

5BR

Z

C33

0.1µ

F

V1 V2 V3 V4

A0

A1

A2

A3

CBASL9

CBASL

10

A4

DCBA1

3 52 4

SL11 DCBA

13 52 4

SL8

C75

0.1µ

F

C76 1µF

A7-

1

A7-

2

A7-

3

A7-

4

A7-

5

A7-

6

R99

0Ω

C59

270p

F

C19

270p

F

C27

270p

F

C28

270p

F

C23

680p

F

C26

680p

F

LK12

LK4

LK5

LK6

LK7

LK8

LK9

LK10

LK11

VIN

+REF

GPI

O0

GPI

O1

SYN

C/E

RR

CS

SCLK

DIN

DO

UT

AVD

D1

3.3V

3.3V

3.3V

AG

ND

AG

ND

VCM

VCM

AVS

S

AVS

SA

VSS

AVS

S

AVS

S

AVS

S

AVS

SA

VSS

AVS

S

AVS

SA

VSS

AVS

S

AVS

S

AVS

S

AVS

SA

VSS

AVS

SA

VSS

BU

F0+

DIF

F1+

BU

F1+

DIF

F1–

DIF

F2+

DIF

F2–

BU

F2+

BU

F3+

AIN

0_SU

RF

AIN

1_SU

RF

AVS

S

AVS

S

AVS

S

AVS

S

AVS

S

AVS

S

13282-124

Figure 24. AD7177-2 Schematic



Rev. A | of 34

ATT

ENU

ATI

NG

SIN

GLE

EN

DED

TO

DIF

FER

ENTI

AL

DR

IVER

OPT

ION

AL

HEA

DER

CO

NN

ECTO

R

BY

DEF

AU

LT, R

64 A

ND

R74

AR

E D

NI (

AM

P N

OT

CO

NN

ECTE

D T

O A

DC

)PO

PULA

TE W

ITH

10Ω

RES

ISTO

RS

IF U

SIN

G T

HE

AD

8475

AM

PLIF

IER

S C

ON

NEC

TED

TO

AD

C U

SIN

G 0

Ω L

INK

S.

AM

PLIF

IER

S C

ON

NEC

TED

TO

AD

C U

SIN

G 0

Ω L

INK

S.

SELE

CTA

BLE

GA

IN IN

AM

P FI

RST

STA

GE

REC

ON

FIG

UR

AB

LE IN

PUT

STA

GE

DEF

AU

LT G

16 IN

SER

TED

ON

LY4

–V

8+V

U8-

CA

DA

4528

-2A

RM

Z C60

0.1µ

FC

681n

F

1-IN

_0.8

X

2-IN

_0.4

X

3 +VS

4 VOC

M

5+O

UT

6–O

UT

7

NC

8

–VS

9+I

N_0

.4X

10+I

N_0

.8X

U9

AD

8475

C37

0.1µ

F

4–V

8+V

U12

-CA

DA

4528

-2A

RM

Z C73

0.1µ

FC

741n

F

C87

0.1µ

F

C89

0.1µ

FC

901n

F

C91

0.1µ

F

C92

1nF

R72

DN

P

R86

C69

DN

I

C41DNI

R69

75kΩ

R63

R78

0Ω

R64

DN

P

R74

DN

P

J10-

1

J10-

2

J10-

3

J10-

4

J10-

5

J10-

6

J10-

7

J13-

1

J13-

2

J13-

3

J13-

4

J13-

5

J13-

6

J13-

7

R81

0Ω

R82

0Ω

R83

0Ω

R84

0Ω

R87

0Ω

7O

UT

5+

6–

U8-

BA

DA

4528

-2A

RM

Z

R93

0ΩR

100

DN

P

R10

2

C42

DN

I

C62DNI

R10

475

kΩ

1O

UT

3+

2–

U12

-AA

DA

4528

-2A

RM

Z

R10

70Ω

R10

8

R10

9

R11

0D

NP

R11

10Ω

R11

2

C63

DN

I

C65DNI

R11

40Ω

7O

UT

5+

6–

U12

-BA

DA

4528

-2A

RM

Z

R11

70Ω

R11

8

R11

9

R12

0D

NP

R12

10Ω

R12

2

C66

DN

I

C70DNI

R12

40Ω

R12

70Ω

R12

90Ω

R13

00Ω

1O

UT

3+

2–

U8-

AA

DA

4528

-2A

RM

Z

R13

2

R65

10kΩ

G16

G32

G64

G12

8

R68

4.75

kΩ

R79

121Ω

R92

51.1

Ω

R73

88.7

Ω

R91

2.26

kΩ

R94

1.13

kΩ

R10

10Ω

R10

30Ω

R10

50Ω

R10

60Ω

R11

3

R11

5

R12

3D

NP

AVD

D1

AVD

D1

DIF

F2+

DIF

F2–

VCM

AIN

2

AIN

3D

IFF1

+

DIF

F1–

AVD

D1

AVS

S

AVS

S

AVS

SA

IN0

BU

F0+

VCM

AVS

S

AG

ND

AG

ND

AIN

1_SU

RF

AIN

0_SU

RF

AG

ND

AG

ND

AVD

D1

AVS

SVC

M

AIN

0

AIN

1

AIN

1B

UF1

+

VCM

AVS

S

AIN

2B

UF2

+

VCM

AVS

S AVS

S

AIN

3B

UF3

+

VCM

AVS

S AVS

S

AVS

S

AVS

S

AVS

S

RG

0

RG

1

RG

1

GPI

O0

GPI

O0

GPI

O1

RG

0

AVS

S

AVS

S

13282-125

Figure 25. Amplifier Schematic


Rev. A | of 34

GR

OU

ND

STA

R P

OIN

T. P

LAC

E N

EAR

TO

V_I

N J

AC

K P

LUG

J5

POW

ER S

UPP

LY

POW

ER S

EQU

ENC

E C

ON

TRO

L

5V L

DO

TO

PO

WER

SD

PPO

WER

SU

PPLY

FO

R S

DP

BO

AR

D

LK1

A: 5

V A

VDD

1LK

1 B

: 2.5

V A

VDD

1

VIN

GN

DA

VSS

CO

NN

ECT

SDP_

GN

D A

ND

AG

ND

FO

R A

DP7

104

RET

UR

N C

UR

REN

TS

INSE

RT

FOR

±2.

5V O

PER

ATI

ON

–5V

FOR

–2.

5V L

DO

1GN

D

2VI

N1

3VI

N2

4VI

N3

5VI

N4

6PW

RG

D

7O

UT3

8O

UT2

9O

UT1

10VD

DU

3 AD

M11

85A

RM

Z

R60

2.4k

Ω

R25

30.1

kΩ

D4

GR

EEN

R23

86.6

kΩ

R42 10kΩ

R43 10kΩ

R44 10kΩ

C9

DN

I

C5

DN

I

C7

DN

I

C8

DN

IR

1810

.2kΩ

R24

10.2

kΩ

R15 10

.2kΩ

R17

10.2

kΩ

R16

69.8

kΩ

Q1

SI23

04D

DS-

T1-G

E3

R45

10kΩ

R14 39kΩ

R54

4.53

kΩ

R55

61.9

kΩ

D5

BZT

52

E

B

C

Q2

J5-1

J5-2

J5-3

J5-4

B ALK

2

R20 0Ω

R21

0Ω

R22

0ΩR190Ω

R35

0Ω

R36

0Ω

R37

0Ω R38

0Ω

C6

1µF

C4

1µF

R48

100k

Ω

R3

100k

Ω

R7

100k

Ω

1VO

UT

2SE

NSE

3G

ND

4N

/C

5EN

/UVL

O

6GN

D

7PG

8VI

N

9EPU2

AD

P710

4AR

DZ-

5.0

1 2 3J41 2 3J3

R57

30.1

kΩ

BA

LK1

C34

0.1µ

FC

3510

µF

R58

0Ω

R59

0Ω

R61

0Ω

R62

0Ω

1FC

2C

AP+

3G

ND

4C

AP–

5O

UT

6LV

7O

SC

8V+

U11

AD

M66

0AR

Z

C36

10µF

R95 0Ω

C38

0.1µ

FC

3910

µFR

700Ω

R11

60Ω

C64

10µF

C67

10µF

C79

DN

I

AVD

D1 VS

DP

AVD

D_E

N

VSD

P_EN

IOVD

D_E

N

V_5V

1_D

IOD

E

V_IN

3.3V

V_IN

V_5V

1_D

IOD

E

SDP_

GN

D

V_IN

SDP_

GN

D

V_IN

VSD

P_EN

VSD

P

$$$5

245

SDP_

GN

D

SDP_

GN

D

AVS

S

SDP_

GN

D

VSD

P

–VSD

P

VIN

+REF

SDP_

GN

D

SDP_

GN

D

SDP_

GN

D

SDP_

GN

DSD

P_G

ND

13282-126

Figure 26. Power Supply Sequencing Schematic


Rev. A | of 34

5V / 2.5V LINEAR REGULATOR

3.3V LINEAR REGULATOR

*ALTERNATIVE CONNECTIONOVERLAPPING LAYOUT

(EXT IOVDD, FOR STAND ALONE OPERATION ONLY)

5V, 3.3V AND ±2.5V REGULATORS

EXTERNAL VOLTAGE CONNNECTOR IF SEPARATE SUPPLY IS REQUIRED IN STAND ALONE CONFIGURATIONOR TO ALLOW FOR EXTERNAL SPLIT SUPPLY OPERATION ±2.5V

EXT 5V OR 2.5V

ON BOARD LDO -2.5V

SOLDER LINKDEFAULT A

AVDD

GNDAVSS

IOVDD

NOISE REDUCTION RC OPTION

EXT –2.5V

CONNECT AVSS AND AGND FOR 5V SUPPLYDISCONNECT FOR ±2.5V OPERATION

INSERT FOR ±2.5V OPERATION

INSERT R67 FOR 2.5V OUTPUT

1VOUT 2VOUT

3SENSE/ADJ

4GND

5 EN 6SS

7 VIN8 VIN

9EP(GND)

U7ADP7118ARDZ-2.5

1VOUT 2VOUT

3SENSE/ADJ

4GND

5 EN 6SS

7 VIN8 VIN

9EP(GND)

U10ADP7118ARDZ-3.3

1234

J9

1234

J7

C462.2µF

C51

DNI

C50

DNI

L3

1000Ω

C520.1µF

D6RED

R7110kΩ

D2RED

R810kΩ

C4810µF

C4910µF

BA

SL5

R90 DNI

C31

DNI

C32

10µF

R66100kΩ

R75100kΩ

C432.2µF

R53

10kΩ

C301µF R56

C29DNI

C45

2.2µFC472.2µF

BA

SL2

R961.07kΩ

R971.02kΩ

R76

C80DNI

D16RED

R7710kΩ

BA

SL3 L1

1000Ω

C72

0.1µF

R80

C78

DNI

R49 0Ω

R50 0Ω

R51 0Ω

R52 0Ω

R85

C712.2µF

C772.2µF

R67

L4

1000Ω

C40

0.1µFR98

C61DNI

C81

DNI

C82

DNI

1GND

2 VIN

3 EN 4ADJ

5VOUT

U4ADP7182AUJZ

3.3VV_IN

EXT_AVDD1EXT_IOVDD

VIO_SDP

V_IN

AVDD_EN

IOVDD_EN

AVDD1

AGND

EXT_AVSS

AVSS

AVSS

–VSDP

EXT_AVDD1

EXT_AVSS

EXT_IOVDD

SOLDER LINKDEFAULT B

1328

2-12

7

Figure 27. Regulator Schematic


Rev. A | of 34

VIO: USE TO SET IO VOLTAGE MAX DRAW 20mAVIN: USE THIS PIN TO POWER THE SDP REQUIRES 4V TO 7V 200mABMODE1: PULL UP WITH A 10kΩ RESISTOR TO SET SDP TO BOOT FROM A SPI FLASH ON THE DAUGHTER BOARD

EEPROM-SW/USB ID

SDP CONNECTOR

VIN: USE THIS PIN TO POWER THE SDP REQUIRES 5V 200mAI2C BUS 1 IS COMMON ACROSS BOTH CONNECTORS ON SDP - PULL UP RESISTORS REQUIRED(CONNECTED TO BLACKFIN GPIO - USE I2C_0 FIRST)

VIO: USE TO SET IO VOLTAGE MAX DRAW 20mA

BOARD ID EEPROM (24LC32)MUST BE ON I2C BUS 0,

BMODE1: PULL UP WITH A 10kΩ RESISTOR TO SET SDP TO BOOT FROM A SPI FLASH ON THE DAUGHTER BOARD

MAIN I2C BUS (CONNECTED BLACKFIN TWI.PULL UP RESISTORS NOT REQUIRED)

SDP CONNECTOR SCHEME, R.R. 15/04/11

CONNECTORSTANDARD

SDP

PARALLELPORT

SPORT

SPI

I2C

GENERALINPUT/OUTPUT

TIMERS

**

**

*

****

****

*NC ON BLACKFIN SDP 120NC

119NC

118GND

117GND

116VIO(+3.3V)

115GND

114PAR_D22

113PAR_D20

112PAR_D18

111PAR_D16

110PAR_D15

109GND

108PAR_D12

107PAR_D10

106PAR_D8

105PAR_D6

104GND

103PAR_D4

102PAR_D2

101PAR_D0

100PAR_WR

99PAR_INT

98GND

97PAR_A2

96PAR_A0

95PAR_FS2

94PAR_CLK

93GND

92SPORT_RSCLK

91SPORT_DR0

90SPORT_RFS

89SPORT_TFS

88SPORT_DT0

87SPORT_TSCLK

86GND

85SPI_SEL_A

84SPI_MOSI

83SPI_MISO

82SPI_CLK

81GND

80SDA_0

79SCL_0

78GPIO1

77GPIO3

76GPIO5

75GND

74GPIO7

73TMR_B

72TMR_D

71NC

70NC

69GND

68NC

67NC

66NC

65NC

64NC

63GND

62UART_TX

61BMODE160 RESET_IN59 UART_RX58 GND57 NC56 EEPROM_A055 NC54 NC53 NC52 GND51 NC50 NC49 TMR_C48 TMR_A47 GPIO646 GND45 GPIO444 GPIO243 GPIO042 SCL_141 SDA_140 GND39 SPI_SEL1/SPI_SS38 SPI_SEL_C37 SPI_SEL_B36 GND35 SPORT_INT34 SPORT_DT333 SPORT_DT232 SPORT_DT131 SPORT_DR130 SPORT_DR229 SPORT_DR328 GND27 PAR_FS126 PAR_FS325 PAR_A124 PAR_A323 GND22 PAR_CS21 PAR_RD20 PAR_D119 PAR_D318 PAR_D517 GND16 PAR_D715 PAR_D914 PAR_D1113 PAR_D1312 PAR_D1411 GND10 PAR_D179 PAR_D198 PAR_D217 PAR_D236 GND5 USB_VBUS4 GND3 GND2 NC1 VIN

J1

1 A02 A13 A24 VSS

8VCC 7WP 6SCL 5SDA

U1

24LC32

R1 DNI

R2 100kΩ

R4 100kΩ

C2

0.1µF

C1

4.7µF

VIO_SDP

SCL_0SDA_0

VIO_SDP

SYNC/ERR

SCLKDOUTDINCS

VSDP

SDP_GNDVIO_SDP

AGND

AGND AGNDAGND

AGND

SDP_GND

1328

2-12

8

Figure 28. SDP-B Connector Schematic



Rev. A | of 34

1328

2-12

9

Figure 29. Top Printed Circuit Board (PCB) Silkscreen

1328

2-13

0

Figure 30. Bottom PCB Silkscreen


Rev. A | of 34

1328

2-13

1

Figure 31. Layer 1, Component Side

1328

2-13

2

Figure 32. Layer 2, Ground Plane


Rev. A | of 34

1328

2-13

3

Figure 33. Layer 3, Power/Ground Plane

1328

2-13

4

Figure 34. Layer 4, Solder Side


Rev. A | of 34

ORDERING INFORMATION BILL OF MATERIALS

Table 4.

Qty. Reference Designator Description Manufacturer Part Number Stock Code

5 A0 to A6 Straight PCB mount SMB jack, keep hole clear of solder, do not insert

TE Connectivity 1-1337482-0 Do not insert

1 A7 6-pin SIL header, 0.1 inch pitch Harwin 20-9990646 FEC1022255 2 C1, C17 Ceramic capacitor, 6.3 V, X5R, 0603,

4.7 μF Murata GRM188R60J475K FEC173-5527

2 C2, C38 Ceramic capacitor, 50 V, X7R, 0603, 0.1 μF

Murata GRM188R71H104K FEC882-0023

1 C3 Ceramic capacitor, 10 V, X5R, 0603, 4.7 μF

KEMET C0603C475K8PACTU FEC157-2625

2 C4, C6 Capacitor, 0805, 50 V, X7R, 1 μF Murata GRM21BR71H105KA12L FEC1735541 22 C5, C7,C9, C16,

C24, C25, C29, C41, C42, C61 to C63, C65, C66, C69, C70, C78 to C82

Ceramic capacitor, 0402, do not insert Not applicable Not applicable

2 C10, C11 Ceramic capacitor, crystal, 0402, do not insert

Not applicable Not applicable

23 C12 to C14, C18, C20 to C22, C33, C34, C37, C40, C44, C52 to C54, C58, C60, C72, C73, C75, C87, C89, C91

Capacitor ceramic, 16 V, X7R, 0402 Murata GRM155R71C104K FEC881-9742

5 C15, C30, C56, C57, C76

Capacitor, 6.3 V, 0603, 1 μF Murata GRM188R70J105KA01D FEC184-5765

8 C19, C27, C28, C55, C59, C83, C85, C86

Ceramic capacitor, 50 V, C0G/NPO, 0603

AVX Corporation 06035A271JAT2A FEC1734627

4 C23, C26, C84, C88 Ceramic capacitor, 50 V, NPO, 0603 KEMET C0603C681J5GACTU FEC1414648 3 C31, C50, C51 Ceramic capacitor, 16 V, X7R, 0402, do

not insert Not applicable Not applicable

8 C32, C35, C36, C39, C48, C49, C64, C67

Capacitor, MLCC (multilayer ceramic capacitor) 10 V, X5R, 10 μF, 0603

TDK Corporation C1608X5R1A106K080AC FEC221-1164

6 C43, C45 to C47, C71, C77

Capacitor, MLCC, 10 V, X5R, 2.2 μF, 0603 Newark MC0603X225K100CT FEC232-0817

4 C68, C74, C90, C92 Capacitor, MLCC, 50 V, X7R Yageo 2238 586 15623 FEC722170 3 D2, D6, D16 LED, red, high intensity (>90 mcd),

0603 Broadcom Limited

HSMC-C191 FEC855-4528

1 D4 LED, green, SMD Osram LGQ971 FEC1226372 1 D5 Zener diode, 0.5 W, 5.1 V Vishay BZT52B5V1-V-GS08 FEC1617767 1 G16 2-pin header and shorting shunt,

2 mm pitch Harwin M22-2010205 and

M22-1920005 FEC671915 and FEC510944

3 G32, G64, G128 2-pin header, 2 mm pitch Harwin M22-2010205 FEC671915 19 GND, GND1 to GND6,

GPIO0, GPIO1, REF+, REF−, TDIN, TDOUT, TERR, TCLK, TSYNC, TXTAL1, TXTAL2, T\CS

Test point, keep hole clear of solder, do not insert

Not applicable Not applicable

1 J1 120-way connector, 0.6 mm pitch Hirose Electric Group

FX8-120S-SV(21) FEC1324660

1 J2 Straight PCB mount, SMB jack, keep hole clear of solder, do not insert

TE Connectivity 1-1337482-0

1 J3 Socket terminal block, 3.81 mm pitch Phoenix Contact MC 1.5/3-G-3.81 FEC370-4737


Rev. A | of 34


1 J4 Screw terminal block, 3.81 mm pitch, do not insert

Phoenix Contact 1727023

1 J5 DC power connectors, 2 mm pitch, SMT power jack

Lumberg 161314 FEC1243245

1 J6 8-pin terminal header, 3.81 mm pitch, vertical

Phoenix Contact MC 1.5/8-G-3.81 FEC3704774

1 J7 Connector, 3.81 mm pitch, right angle, do not insert

Phoenix Contact MC 1.5/4-G-3.81 and 180-3594

1 J8 8-pin screw terminal, 3.81 mm pitch, vertical, do not insert

Phoenix Contact 1727078

1 J9 Screw terminal block, 3.81 mm pitch Phoenix Contact 1727036 FEC370-4592 1 J10 7-way SSW, 2.54 mm vertical socket,

line up with connector on surf board Samtec SSW-107-01-T-S FEC1803478

2 J11, J14 Screw terminal block, 3.81 mm pitch, do not insert

Phoenix Contact MKDS1/4-3.81

1 J12 4-way power socket block, 3.81 mm pitch

Phoenix Contact MC1.5/4-G-3.81 FEC370-4749 and FEC370-4920

1 J13 7-way SIP, 2.54 mm through-hole header, line up with connector on surf board

Samtec TLW-107-05-G-S FEC 1668499

1 J15 4-way power socket block, 3.81 mm pitch

Phoenix Contact MC1.5/4-G-3.81 FEC370-4749 and FEC370-4920

4 L1 to L4 Ferrite bead, 0.3 Ω at dc, 1000 Ω at 100 MHz, 350 mA, 0805

TE Connectivity BMB2A1000LN2 FEC119-3421

2 LK1, LK2 3-pin (3 × 1) header and shorting block in, 0.1 inch pitch, Position A

Harwin M20-9990346 and M7566-05

FEC1022249 and FEC150-411

5 LK3 to LK7 2-pin header, 0.1 inch pitch Harwin M20-9990246 FEC1022247 5 LK8 to LK12 2-pin header and shorting shunt,

0.1 inch pitch Harwin M20-9990246 FEC1022247 and

FEC150-411 1 Q1 Diode, MOSFET, negative channel,

30 V, 3.6 A, SOT-23 Vishay SI2304DDS-T1-GE3 FEC1858939

1 Q2 Transistor, NPN, SOT-23 ON Semiconductor

MMBT3904LT1G FEC1459100

1 R1 Resistor, 0603, do not insert Not applicable Not applicable 7 R2 to R4, R7,

R48, R66, R75 Resistor, 100 kΩ, 0.063 W, 1%, 0603 Newark MC0063W06031100K FEC9330402

3 R5, R6, R77 Resistor, 10 kΩ, 0.063 W, 1%, 0402 Newark MC00625W0402110K FEC1358069 2 R8, R71 Resistor, 1%, 0402 Yageo CRCW040210K0FKEAHP FEC173-8864 31 R9 to R13, R27,

R30, R32, R41, R63, R78, R81 to R84, R87, R95, R99, R101, R103, R105, R107, R111, R114, R117, R121, R124, R128 to R131

Resistor, 0603 1%, 0R Newark MC0063W06030R FEC9331662

1 R14 Resistor, 0402, 1%, 39 kΩ Newark MC 0.0625W 0402 1% 39K FEC1358085 4 R15, R17, R18, R24 Resistor, SMD Newark MC 0.0625W 0402 1% 10K2 FEC1803137 1 R16 Resistor, 0402, 1%, 69K8 Newark MC 0.0625W 0402 1% 69K8 FEC1803735 15 R19 to R22,

R35 to R38, R40, R58, R59, R61, R62, R70, R116

Resistor, 0402 Vishay CRCW04020000Z0ED FEC146-9661

1 R23 Resistor, 0402, 1%, 86K6 Newark MC 0.0625W 0402 1% 86K6 FEC1803744 2 R25, R57 Resistor, 0402, 1%, 30k1 Newark MC 0.0625W 0402 1% 30k1 FEC1803699


Rev. A | of 34


32 R26, R28, R29, R31, R33, R56, R64, R67, R72, R74, R76, R80, R85, R86, R88, R98, R100, R102, R108 to R110, R112, R113, R115, R118 to R120, R122, R123, R125, R126, R132

Resistor, SMD, 0603, do not insert Not applicable Not applicable

4 R34, R39, R46, R47 Resistor, 10 kΩ, 0.063 W, 1%, 0603 Newark MC0063W0603110R FEC9330429 4 R42 to R45 Resistor, thick film, 10 kΩ, 62.5 mW, 5% Yageo RC0402JR-1310KL FEC179-9316 4 R49 to R52 Resistor, 1206 Newark MC 0.125W 1206 0R FEC9336974 2 R53, R65 Resistor, 10 kΩ, 0.063 W, 1%, 0603 Newark MC0063W0603110K FEC9330399 1 R54 Resistor, thick film, 4.53 kΩ, 63 mW, 1% Vishay CRCW04024K53FKED FEC1151244 1 R55 Resistor, 0402, 1%, 61R9 Newark MC 0.0625W 0402 1% 61R9 FEC1802915 1 R60 Resistor, thick film, 2.4 kΩ, 0603,

100 mW, 1% Yageo RC0603FR-072K4L FEC1799329

1 R68 Resistor, 0603, 4K75, 0.1%, 0.1 W Panasonic ERA3ARB4751V FEC209-4611 2 R69, R104 Resistor, 0603, 0.1%, 0.1 W, 75 kΩ Panasonic ERA3ARB753P FEC171-7620 1 R73 Resistor, 88R7, 0.063 W, 0.1%, 0402 TE Connectivity RN73C1E88R7B FEC173-7900 1 R79 Resistor, 121 kΩ, 0.063 W, 0.1%, 0603 TE Connectivity RN73C1J121RBTG FEC114-0465 1 R90 Resistor, 0402, do not insert Not applicable Not applicable 1 R91 Resistor, 2K26, 0.063 W, 0.1%, 0402 TE Connectivity RN73C1E2K26B FEC173-8050 1 R92 Resistor, 51R1, 0.063 W, 0.1%, 0603 TE Connectivity RN73C1J51R1BTG FEC114-0446 2 R93, R106 Resistor, 0603 Vishay CRCW06030000Z0EA FEC146-9739 1 R94 Resistor, 0603, 1K13, 0.1%, 0.1 W Panasonic ERA3ARB1131V FEC209-4485 1 R96 Resistor, 1K07, 0.063 W, 1%, 0603 Newark MC0063W060311K07 FEC1170792 1 R97 Resistor, 1K02, 0.063 W,1%, 0603 Newark MC0063W060311K02 FEC1170789 1 R127 Resistor, 0603 Vishay CRCW06030000Z0EA FEC146-9739 1 SL1 2-way resistor link option Newark MC 0.063W 0603 0R FEC9331662 2 SL2, SL3 2-way solder link, use 0R 0603 resistor,

insert link in Position A Not applicable FEC933-1662

1 SL4 3-way solder link, use 0R 0603 resistor, insert link in Position C

Not applicable FEC933-1662

1 SL5 2-way solder link, use 0R 0603 resistor, insert link in Position B


1 SL8 4-way solder link, use 0R 0603 resistor, insert link in Position A


2 SL9, SL10 3-way solder link, use 0R 0603 resistor, insert link in Position A


1 SL11 4-way solder link, use 0R 0603 resistor, insert link in Position A


1 STAR3 Ground link, copper short Not applicable Not applicable Not applicable 1 U1 Serial EEPROM, 32 kΩ, I2C Microchip 24LC32A-I/MS FEC1331330 1 U2 Linear regulator, 5 V, 20 V, 500 mA,

ultralow noise, CMOS Analog Devices, Inc.

ADP7104ARDZ-5.0 ADP7104ARDZ-5.0

1 U3 Quad voltage monitor and sequencer ADI ADM1185ARMZ-1 ADM1185ARMZ-1 1 U4 Linear regulator, 8 V, −200 mA, low

noise ADI ADP7182AUJZ ADP7182AUJZ-R7

1 U5 ADC ADI AD7172-2BRUZ AD717-2BRUZ 1 U6 Reference, 5 V, XFET ADI ADR445BRZ ADR445BRZ 1 U7 Linear regulator 2.5 V, ultralow noise,

CMOS ADI ADP7118ARDZ-2.5 ADP7118ARDZ-2.5-R7

1 U8 Dual op amp, 5.0 V, ultralow noise, zero drift, rail-to-rail input/output (RRIO)

ADI ADA4528-2ARMZ ADA4528-2ARMZ

1 U9 Funnel amplifier, fully differential ADI AD8475ARMZ AD8475ARMZ










http://www.analog.com/ADA4528-2?doc=EVAL-AD7177-2SDZ_UG-849.pdf

http://www.analog.com/AD8475?doc=EVAL-AD7177-2SDZ_UG-849.pdf





http://www.analog.com/AD8475?doc=EVAL-AD7177-2SDZ_UG-849.pdf


Rev. A | of 34


1 U10 Linear regulator 3.3 V, ultralow noise, CMOS

ADI ADP7118ARDZ-3.3 ADP7118ARDZ-3.3-R7

1 U11 Voltage converter, switched capacitor, CMOS

ADI ADM660ARZ ADM660ARZ

1 U12 5.0 V ultralow noise, zero-drift, RRIO, dual op-amp

ADI ADA4528-2ARMZ ADA4528-2ARMZ

4 V1 to V4 1206 place holder, do not insert Not applicable Not applicable 1 Y1 Crystal, miniature, SMD, 16 MHz,

10 ppm, 9 pF Epson FA-20H FEC 71-2814

I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).

ESD Caution ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality.

Legal Terms and Conditions By using the evaluation board discussed herein (together with any tools, components documentation or support materials, the “Evaluation Board”), you are agreeing to be bound by the terms and conditions set forth below (“Agreement”) unless you have purchased the Evaluation Board, in which case the Analog Devices Standard Terms and Conditions of Sale shall govern. Do not use the Evaluation Board until you have read and agreed to the Agreement. Your use of the Evaluation Board shall signify your acceptance of the Agreement. This Agreement is made by and between you (“Customer”) and Analog Devices, Inc. (“ADI”), with its principal place of business at One Technology Way, Norwood, MA 02062, USA. Subject to the terms and conditions of the Agreement, ADI hereby grants to Customer a free, limited, personal, temporary, non-exclusive, non-sublicensable, non-transferable license to use the Evaluation Board FOR EVALUATION PURPOSES ONLY. Customer understands and agrees that the Evaluation Board is provided for the sole and exclusive purpose referenced above, and agrees not to use the Evaluation Board for any other purpose. Furthermore, the license granted is expressly made subject to the following additional limitations: Customer shall not (i) rent, lease, display, sell, transfer, assign, sublicense, or distribute the Evaluation Board; and (ii) permit any Third Party to access the Evaluation Board. As used herein, the term “Third Party” includes any entity other than ADI, Customer, their employees, affiliates and in-house consultants. The Evaluation Board is NOT sold to Customer; all rights not expressly granted herein, including ownership of the Evaluation Board, are reserved by ADI. CONFIDENTIALITY. This Agreement and the Evaluation Board shall all be considered the confidential and proprietary information of ADI. Customer may not disclose or transfer any portion of the Evaluation Board to any other party for any reason. Upon discontinuation of use of the Evaluation Board or termination of this Agreement, Customer agrees to promptly return the Evaluation Board to ADI. ADDITIONAL RESTRICTIONS. Customer may not disassemble, decompile or reverse engineer chips on the Evaluation Board. Customer shall inform ADI of any occurred damages or any modifications or alterations it makes to the Evaluation Board, including but not limited to soldering or any other activity that affects the material content of the Evaluation Board. Modifications to the Evaluation Board must comply with applicable law, including but not limited to the RoHS Directive. TERMINATION. ADI may terminate this Agreement at any time upon giving written notice to Customer. Customer agrees to return to ADI the Evaluation Board at that time. LIMITATION OF LIABILITY. THE EVALUATION BOARD PROVIDED HEREUNDER IS PROVIDED “AS IS” AND ADI MAKES NO WARRANTIES OR REPRESENTATIONS OF ANY KIND WITH RESPECT TO IT. ADI SPECIFICALLY DISCLAIMS ANY REPRESENTATIONS, ENDORSEMENTS, GUARANTEES, OR WARRANTIES, EXPRESS OR IMPLIED, RELATED TO THE EVALUATION BOARD INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, TITLE, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS. IN NO EVENT WILL ADI AND ITS LICENSORS BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT, OR CONSEQUENTIAL DAMAGES RESULTING FROM CUSTOMER’S POSSESSION OR USE OF THE EVALUATION BOARD, INCLUDING BUT NOT LIMITED TO LOST PROFITS, DELAY COSTS, LABOR COSTS OR LOSS OF GOODWILL. ADI’S TOTAL LIABILITY FROM ANY AND ALL CAUSES SHALL BE LIMITED TO THE AMOUNT OF ONE HUNDRED US DOLLARS ($100.00). EXPORT. Customer agrees that it will not directly or indirectly export the Evaluation Board to another country, and that it will comply with all applicable United States federal laws and regulations relating to exports. GOVERNING LAW. This Agreement shall be governed by and construed in accordance with the substantive laws of the Commonwealth of Massachusetts (excluding conflict of law rules). Any legal action regarding this Agreement will be heard in the state or federal courts having jurisdiction in Suffolk County, Massachusetts, and Customer hereby submits to the personal jurisdiction and venue of such courts. The United Nations Convention on Contracts for the International Sale of Goods shall not apply to this Agreement and is expressly disclaimed.

©2015–2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. UG13282-0-8/18(A)







http://www.analog.com

EVAL-AD7177-2SDZ User Guide - Analog Devices · 2018. 8. 7. · EVAL-AD7177-2SDZ User Guide UG-849...

Documents

Transcript of EVAL-AD7177-2SDZ User Guide - Analog Devices · 2018. 8. 7. · EVAL-AD7177-2SDZ User Guide UG-849...