[01]F (A, B, C, D) = m(2, 7, 8, 13) + d(0, 5, 10)(a)

AB

01001011CD

00001

01010

110100

10100

F (ABCD) = BD+BCD+ABD

(b) Find the optimized sumofproducts (SOP) expression for F.

01001011CD

00001

01010

110100

10100

F (ABCD) = BD+BCD+ABD

(c) Find the optimized productofsums (POS) expression for F.

AB

01001011CD

00001

01010

110100

10100

F (ABCD) = ABD+ABD+AC+BD(d)

[Q2] (a) F1(A,B,C)= m(0, 1, 2, 4, 6, 7) AB000111 10

C

01111

11010

F1(A,B,C)= C+AB+AB

F2(A,B,C)= m(0, 1, 3, 5, 7)

AB000111 10

C

01000

11111

F2(A,B,C)= C+AB

F3(A,B,C)= m(0, 1, 2, 3, 6, 7) AB000111 10

C

01110

11110

F3(A,B,C)= A+B

F4(A,B,C)= m(0, 2) AB000111 10

C

01100

10000

F4(A,B,C)= AC

(b) Draw truth tables for the above expressions.F1(A,B,C)= C+AB+AB

ABCABCABABC+AB+AB

000111011

001110011

010101001

011100000

100011001

101010000

110001101

111000101

F2(A,B,C)= C+ABABCABABC+AB

0001111

0011111

0101000

0111001

1000100

1010101

1100000

1110001

F3(A,B,C)= A+BABCAA+B

00011

00111

01011

01111

10000

10100

11001

11101

F4(A,B,C)= ACABCACAC

000111

001100

010111

011100

100010

101000

110010

111000

(c) i. ROM ii. PLAF1(A,B,C)=C+AB+AB P1 P2 P3F2(A,B,C)= C+AB P4F3(A,B,C)= A+B P5 P6F4(A,B,C)= AC P7

iii. PAL

(d) ROMPLAPAL

Devices with fixed AND array (which is a decoder) and programmable OR array.Compared to a ROM and a PAL, a PLA is the most flexible having a programmable set of ANDs combined with a programmable set of ORs. The PAL is the opposite of the ROM, having a programmable set of ANDs combined with fixed ORs.

The AND array (decoder) generates all 2n possible minterm products of its n inputs (often referred to as n-to-2n decoder).n input lines, m output lines.

A PLA can have large N and M permitting implementation of equations that are impractical for a ROM (because of the number of inputs, N, requiredROM guaranteed to implement any M functions of Ninputs. PAL may have too few inputs to the OR gates

Bit combination of input variables address.

A PLA has all of its product terms connectable to all outputs, overcoming the problem of the limited inputs to the PAL ORsSome PLAs have outputs that can be complemented, adding POS functions

.

Bit combination of output lines word (each word contains m bits).Often, the product term count limits the application of a PLA. .For given internal complexity, a PAL can have larger N and M.Some PALs have outputs that can be complemented, adding POS functionsNo multilevel circuit implementations in ROM (without external connections from output to input). PAL hasoutputs from OR terms as internal inputs to all ANDterms, making implementation of multi-level circuits easier.

[Q3](a)

Setup time (tsu ): The minimum amount of time the data signal should be held steady before the clock event so that the data is reliably sampled by the clock. This applies to synchronous input signals to the flip-flop.Hold time (th): The minimum amount of time the data signal should be held steady after the clockevent so that the data are reliably sampled. This applies to synchronous input signals to the flip-flop.

Propagation delay (tp): the time a flip-flop takes to change its output after the clock edge

(b) (c)

[Q4](a)

X1 0 1 0 0 1 1 0 1 1 0 0 1 1

Z0 0 0 0 0 1 0 1 0 0 1 0 1 0 .

(b) Draw a state table for the pattern detector.

Present StateNext State /Output

X=0X=1

S0S1/0S2/0

S1S1/0S3/0

S2S4/0S2/0

S3S4/0S5/0

S4S6/0S3/0

S5S4/1S2/0

S6S1/0S3/1

(c) Draw a transition table for the pattern detector.

2P-1 < 7P=3

Present StateNext State /Output

X=0X=1

Y2 Y1 Y0Y2 Y1 Y0 Y2 Y1 Y0 /Z

S0 0 0 0 0 0 1/00 1 0/0

S1 0 0 1 0 0 1/00 1 1/0

S2 0 1 0 1 0 0/00 1 0/0

S3 0 1 1 1 0 0/01 0 1/0

S41 0 0 1 1 0/00 1 1/0

S51 0 1 1 0 0/10 1 0/0

S61 1 0 0 0 1/00 1 1/1

Y0Y1(d) Implement the pattern detector using D Flip Flop and other digital gates.

Y2X10110100001001

01 0011

1110X1

100000

D0=Y1Y2X + Y1Y2X + Y0X

Y0Y1Y2X10110100000000

011101

1110X1

101001

D1=Y1X + Y1Y2 + Y0Y2X

Y0Y1

Y2X00011110000110

010010

1101X1

101101

D2=Y1Y2X + Y1Y2X + Y0Y1X + Y0Y1Y2 + Y0Y2X

Y0Y1

Y2X00011110000000

010000

1101X0

100001

Z=Y1Y2X + Y0Y1Y2X