Differential Amplifier Offset Causes of DC voltage and ... · PDF fileESE319 Introduction to...

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ESE319 Introduction to Microelectronics 1 2008 Kenneth R. Laker (based on P. V. Lopresti 2006) update KRL 21Oct08 Differential Amplifier Offset Causes of DC voltage and current offset Modeling DC offset R C mismatch I S mismatch β mismatch

Transcript of Differential Amplifier Offset Causes of DC voltage and ... · PDF fileESE319 Introduction to...

Page 1: Differential Amplifier Offset Causes of DC voltage and ... · PDF fileESE319 Introduction to Microelectronics 2008 Kenneth R. Laker (based on P. V. Lopresti 2006) update KRL 21Oct08

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Differential Amplifier Offset

● Causes of DC voltage and current offset● Modeling DC offset

● RC mismatch● IS mismatch● β mismatch

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IC1

RC1 RC2

IC2

VCCVCC

+- VO

VO−dm=−RC2 I C2−−RC1 I C1=RC1 I C1−RC2 I C2

I

Q1 Q2

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First, assume that:

I C1= I C2=I2

RC1≠RC2

Split the mismatch between bothcollector resistors:

RC=RC2RC1

2RC=RC2−RC1

(common or meanor nominal)

(differential)

Then, it can be shown that:

RC2=RCRC

2=RC 1

12RC

RC

RC1=RC−RC

2=RC 1−

12RC

RC

Let:

I2

I2

and RC2RC1

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VO−dm=RC2 I C2−RC1 IC1

Recall:

VO−dm=RC−RC

2 I C1−RCRC

2 I C2

VO−dm=RC−RC

2 I2−RC

RC

2 I2

I C1= I C2=I2

Hence:

or:

VO−dm=−I2RC output offset voltage

I2

I2

random variable (rv)

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VO−dm=−I2RC

Collector-collector voltage due toresistor mismatch:

Define the input offset voltageas that input voltage that will cancelVO-dm. If the amplifier differential gainis Gdm:

VOS≡VO−dm

Gdm

Input offset voltage is the output off-set voltage referred to the input due to mismatch .RC

I2

I2

VOS is highly variable, rv & can be + or -

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Differential Mode Small-signal Analysis

ib−dm=vdm

2 1r e

Collector-collector voltage:vo−dm=vc2g−dm−vc1g−dm

vo−dm=RC2 ib−dm−−RC1−ib−dm

vo−dm

vdm=

2RC

21 r e

r e=VT

I E=

1

VT

I C=

1

1gm

Gdm=I C

VTRC=g m RC

v-dm/2 v-dm/2ib-dm ib-dm

ic-dmic-dm

ie-dm ie-dm

vdm

2=r e 1ib−dmr e 1 ib−dm−

vdm

2

+ +

vo-dm

r e1=r e2=r e

RC1=RC2=RC

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VOS=∣VO−dm∣∣Gdm∣

VOS=

I2RC

gm RC

gm=I C

VT= I

21

VT

VOSRC=VT

RC

RC

Input referred offset due to ΔRC mismatch:

where Gdm=g m RC

I2

I2

rv

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Offset Voltage From Transistor Mismatch

VO−dm=0⇒RC1 I C1=RC2 I C2

Perfect balance requires:

Previous case considered unequalresistors RC1 ≠ RC2. Here considerunequal collector currents. ASSUME: 1. VBE1 = VBE2 2. VT1=VT2Only difference is in the saturationcurrents of the transistors, i.e.

I S1≠ I S2

+ +

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Again using common and differentialmode concepts:

I S=I S2 I S1

2

I S= I S2− I S1

The two transistor saturation currentsare:

I S2=I S I S

2

I S1= I S− I S

2

+ +

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Large signal Model:

I C1= I S− I S

2 eV BE

VT

I C1= I S eVBE

VT − I S

2 eV BE

VT

I C2= I S eVBE

VT I S

2e

V BE

VT

The parallel current sources areillustrated in the schematic.

IC1

IC2C2

C1

B1

B1

E2

E1

D2

D1

B2

also

I S exp VBE/VT

I S exp VBE/VT

I S

2exp VBE/VT

I S

2exp VBE/VT

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Note: differential IC componentscause current flow in oppositedirections through the RC'sresulting in an offset voltage. Thecommon mode IC componentscause no offset voltage.

I C2= I S eVBE

VT I S

2e

VBE

VT = I S eVBE

VT 1 I S

2 I S

VO−dm=RC I C1−RC I C2=−2 I2 I S

2 I SRC=−

I2

I S

I SRC

I C1= I S eVBE

VT − I S

2e

VBE

VT = I S eVBE

VT 1− I S

2 I S

.=I21

I S

2 I S

.=I21−

I S

2 I S

IC-dm/2

IC-dm/2

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gm=I C

VT= I2

1VT

Recall:

VO−dm=− I2

I S

I SRC

VO−dm=− I2

VT

VT

I S

I SRC

VO−dm=−gmVT I S

I SRC

VOS I S=VT

I S

I S

VOS I S=

VO−dm

Gdm=

VO−dm

gm RC=VT

I S

I S

rv

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Offset Voltage SummaryWe considered two sources of offset voltage:

Unbalanced collector resistorsUnbalanced saturation currents

Mismatched transistor geometriesWe ignored base or emitter circuit unbalance

Since the relationship between resistor and currentunbalances are statistically random and assumedindependent, we combine their effect as an rms quantity:

VOS rms=VOS−RC2VOS− I S

2=VTRC

RC 2

I S

I S 2

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Average & Offset Base (input) Bias CurrentsConsider the case where the base currents differ IB1 ≠ IB2.

Since IB1 & IB2 are related to bias current I, their mismatch is due to β1 ≠ β2.

Let's use differential- common mode models for beta mismatch:

1=2

2=−2

I B1 I B2

I E1=I2

I E2=I2

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I B1=I2

111

=I2

1

2

1=

I2

11

1

1

21

Using this notation, the two base currents are:

I B2=I2

121

=I2

1

21

=I2

11

1

1− 21

11x

=1−xx2−x3...

For x < 1 we can expand the fraction as the series:

where x=±

21≈

12

nonlinearf(Δβ)

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I B1≈I2

11 1−1

2 I B2≈

I2

11 11

2

Using the expansion and approximating :

Since the input bias current IB is defined as: I B=I B1 I B2

2= I

21

I OS≡∣I B1− I B2∣=I

1

I OS = I B

The base or input offset current can also be written as:

(input offset current)

1≈