www.irf.com 104/03/03

IRFR3707ZIRFU3707Z

HEXFETPower MOSFET

Notesthrough are on page 11

Applications

Benefits Very Low RDS(on) at 4.5V VGS

Ultra-Low Gate Impedance Fully Characterized Avalanche Voltage and Current

High Frequency Synchronous Buck Converters for Computer Processor Power

High Frequency Isolated DC-DC Converters with Synchronous Rectification for Telecom and Industrial Use

I-PakIRFU3707Z

D-PakIRFR3707Z

VDSS RDS(on) max Qg30V 9.5m 9.6nC

Absolute Maximum RatingsParameter Units

VDS Drain-to-Source Voltage V

VGS Gate-to-Source Voltage

ID @ TC = 25°C Continuous Drain Current, VGS @ 10V A

ID @ TC = 100°C Continuous Drain Current, VGS @ 10V

IDM Pulsed Drain Current

PD @TC = 25°C Maximum Power Dissipation W

PD @TC = 100°C Maximum Power Dissipation

Linear Derating Factor W/°CTJ Operating Junction and °C

TSTG Storage Temperature Range

Soldering Temperature, for 10 seconds

Thermal ResistanceParameter Typ. Max. Units

RθJC Junction-to-Case ––– 3.0 °C/W

RθJA Junction-to-Ambient (PCB Mount) ––– 50

RθJA Junction-to-Ambient ––– 110

300 (1.6mm from case)

-55 to + 175

50

0.33

25

Max.

56

39

220

± 20

30

2 www.irf.com

S

D

G

Static @ TJ = 25°C (unless otherwise specified)Parameter Min. Typ. Max. Units

BVDSS Drain-to-Source Breakdown Voltage 30 ––– ––– V

∆ΒVDSS/∆TJ Breakdown Voltage Temp. Coefficient ––– 0.023 ––– V/°C

RDS(on) Static Drain-to-Source On-Resistance ––– 7.5 9.5 mΩ

––– 10 12.5

VGS(th) Gate Threshold Voltage 1.35 1.80 2.25 V

∆VGS(th)/∆TJ Gate Threshold Voltage Coefficient ––– -5.0 ––– mV/°C

IDSS Drain-to-Source Leakage Current ––– ––– 1.0 µA

––– ––– 150

IGSS Gate-to-Source Forward Leakage ––– ––– 100 nA

Gate-to-Source Reverse Leakage ––– ––– -100

gfs Forward Transconductance 71 ––– ––– S

Qg Total Gate Charge ––– 9.6 14

Qgs1 Pre-Vth Gate-to-Source Charge ––– 2.6 –––

Qgs2 Post-Vth Gate-to-Source Charge ––– 0.90 ––– nC

Qgd Gate-to-Drain Charge ––– 3.5 –––

Qgodr Gate Charge Overdrive ––– 2.6 ––– See Fig. 16

Qsw Switch Charge (Qgs2 + Qgd) ––– 4.4 –––

Qoss Output Charge ––– 5.8 ––– nC

td(on) Turn-On Delay Time ––– 8.0 –––

tr Rise Time ––– 11 –––

td(off) Turn-Off Delay Time ––– 12 ––– ns

tf Fall Time ––– 3.3 –––

Ciss Input Capacitance ––– 1150 –––

Coss Output Capacitance ––– 260 ––– pF

Crss Reverse Transfer Capacitance ––– 120 –––

Avalanche CharacteristicsParameter Units

EAS Single Pulse Avalanche Energy mJ

IAR Avalanche Current A

EAR Repetitive Avalanche Energy mJ

Diode Characteristics Parameter Min. Typ. Max. Units

IS Continuous Source Current ––– ––– 56

(Body Diode) AISM Pulsed Source Current ––– ––– 220

(Body Diode)VSD Diode Forward Voltage ––– ––– 1.0 V

trr Reverse Recovery Time ––– 25 38 ns

Qrr Reverse Recovery Charge ––– 17 26 nC

ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)

MOSFET symbol

VGS = 4.5V, ID = 12A

–––

VGS = 4.5V

Typ.–––

–––

ID = 12A

VGS = 0V

VDS = 15V

TJ = 25°C, IF = 12A, VDD = 15V

di/dt = 100A/µs

TJ = 25°C, IS = 12A, VGS = 0V

showing theintegral reverse

p-n junction diode.

VDS = VGS, ID = 250µA

VDS = 24V, VGS = 0V

VDS = 24V, VGS = 0V, TJ = 125°C

Clamped Inductive Load

VDS = 15V, ID = 12A

VDS = 15V, VGS = 0V

VDD = 16V, VGS = 4.5V

ID = 12A

VDS = 15V

ConditionsVGS = 0V, ID = 250µA

Reference to 25°C, ID = 1mA

VGS = 10V, ID = 15A

VGS = 20V

VGS = -20V

Conditions

5.0

Max.42

12

ƒ = 1.0MHz

www.irf.com 3

Fig 4. Normalized On-Resistancevs. Temperature

Fig 2. Typical Output CharacteristicsFig 1. Typical Output Characteristics

Fig 3. Typical Transfer Characteristics

0.1 1 10

VDS, Drain-to-Source Voltage (V)

0.001

0.01

0.1

1

10

100

1000

10000

I D, D

rain

-to-

Sou

rce

Cur

rent

(A

)

2.2V

20µs PULSE WIDTHTj = 25°C

VGSTOP 10V

6.0V4.5V4.0V3.3V2.8V2.5V

BOTTOM 2.2V

0.1 1 10

VDS, Drain-to-Source Voltage (V)

0.1

1

10

100

1000

I D, D

rain

-to-

Sou

rce

Cur

rent

(A

)

2.2V

20µs PULSE WIDTHTj = 175°C

VGSTOP 10V

6.0V4.5V4.0V3.3V2.8V2.5V

BOTTOM 2.2V

0 2 4 6 8

VGS, Gate-to-Source Voltage (V)

0.01

0.1

1

10

100

1000

I D, D

rain

-to-

Sou

rce

Cur

rent

(Α

)

TJ = 25°C

TJ = 175°C

VDS = 10V

20µs PULSE WIDTH

-60 -40 -20 0 20 40 60 80 100 120 140 160 180

TJ , Junction Temperature (°C)

0.5

1.0

1.5

2.0

RD

S(o

n) ,

Dra

in-t

o-S

ourc

e O

n R

esis

tanc

e

(

Nor

mal

ized

)

ID = 30A

VGS = 10V

4 www.irf.com

Fig 8. Maximum Safe Operating Area

Fig 6. Typical Gate Charge vs.Gate-to-Source Voltage

Fig 5. Typical Capacitance vs.Drain-to-Source Voltage

Fig 7. Typical Source-Drain DiodeForward Voltage

1 10 100

VDS, Drain-to-Source Voltage (V)

100

1000

10000

C, C

apac

itanc

e(pF

)

VGS = 0V, f = 1 MHZCiss = Cgs + Cgd, C ds SHORTED

Crss = Cgd Coss = Cds + Cgd

Coss

Crss

Ciss

0 2 4 6 8 10 12

QG Total Gate Charge (nC)

0.0

1.0

2.0

3.0

4.0

5.0

6.0

VG

S, G

ate-

to-S

ourc

e V

olta

ge (

V) VDS= 24V

VDS= 15V

ID= 12A

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2

VSD, Source-to-Drain Voltage (V)

0.10

1.00

10.00

100.00

1000.00

I SD

, Rev

erse

Dra

in C

urre

nt (

A)

TJ = 25°C

TJ = 175°C

VGS = 0V

0 1 10 100 1000

VDS, Drain-to-Source Voltage (V)

0.1

1

10

100

1000

I D,

Dra

in-t

o-S

ourc

e C

urre

nt (

A)

1msec

10msec

OPERATION IN THIS AREA LIMITED BY RDS(on)

100µsec

Tc = 25°CTj = 175°CSingle Pulse

www.irf.com 5

Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case

Fig 9. Maximum Drain Current vs.Case Temperature

Fig 10. Threshold Voltage vs. Temperature

25 50 75 100 125 150 175

TC , Case Temperature (°C)

0

10

20

30

40

50

60

I D,

Dra

in C

urre

nt (

A)

Limited By Package

-75 -50 -25 0 25 50 75 100 125 150 175 200

TJ , Temperature ( °C )

1.0

1.5

2.0

2.5

VG

S(t

h) G

ate

thre

shol

d V

olta

ge (

V)

ID = 250µA

1E-006 1E-005 0.0001 0.001 0.01 0.1

t1 , Rectangular Pulse Duration (sec)

0.001

0.01

0.1

1

10

The

rmal

Res

pons

e (

Z th

JC )

0.20

0.10

D = 0.50

0.020.01

0.05

SINGLE PULSE( THERMAL RESPONSE )

Notes:1. Duty Factor D = t1/t22. Peak Tj = P dm x Zthjc + Tc

Ri (°C/W) τi (sec)0.823 0.000128

1.698 0.000845

0.481 0.016503

τJ

τJ

τ1

τ1τ2

τ2 τ3

τ3

R1

R1 R2

R2 R3

R3

ττC

Ci= τi/RiCi= τi/Ri

6 www.irf.com

D.U.T.VDS

IDIG

3mA

VGS

.3µF

50KΩ

.2µF12V

Current RegulatorSame Type as D.U.T.

Current Sampling Resistors

+

-

Fig 13. Gate Charge Test Circuit

Fig 12b. Unclamped Inductive Waveforms

Fig 12a. Unclamped Inductive Test Circuit

tp

V(BR)DSS

IAS

Fig 12c. Maximum Avalanche Energyvs. Drain Current

RG

IAS

0.01Ωtp

D.U.T

LVDS

+- VDD

DRIVER

A

15V

20VVGS

Fig 14a. Switching Time Test Circuit

Fig 14b. Switching Time Waveforms

VGS

VDS90%

10%

td(on) td(off)tr tf

VGS

Pulse Width < 1µsDuty Factor < 0.1%

VDD

VDS

LD

D.U.T

+

-

25 50 75 100 125 150 175

Starting TJ , Junction Temperature (°C)

0

20

40

60

80

100

120

140

160

180

200

EA

S ,

Sin

gle

Pul

se A

vala

nche

Ene

rgy

(mJ) ID

TOP 3.7A5.6A

BOTTOM 12A

www.irf.com 7

Fig 15. for N-ChannelHEXFETPower MOSFETs

• • •

P.W.Period

di/dt

Diode Recoverydv/dt

Ripple ≤ 5%

Body Diode Forward DropRe-AppliedVoltage

ReverseRecoveryCurrent

Body Diode ForwardCurrent

VGS=10V

VDD

ISD

Driver Gate Drive

D.U.T. ISD Waveform

D.U.T. VDS Waveform

Inductor Curent

D = P.W.Period

+

-

+

+

+-

-

-

•

• !"!!• #$$• !"!!%"

Fig 16. Gate Charge Waveform

Vds

Vgs

Id

Vgs(th)

Qgs1 Qgs2 Qgd Qgodr

8 www.irf.com

Control FET

!" # $

%& !" #

#'

Ploss

= Pconduction

+ Pswitching

+ Pdrive

+ Poutput

This can be expanded and approximated by;

Ploss = Irms2 × Rds(on )( )

+ I ×Qgd

ig× Vin × f

+ I ×

Qgs2

ig

× Vin × f

+ Qg × Vg × f( ) + Qoss

2×Vin × f

" (

%& !"

%& !" "

) #

*

%+

%& !"# # ,

#

-./

#

#

Synchronous FET

The power loss equation for Q2 is approximatedby;

Ploss = Pconduction + Pdrive + Poutput*

Ploss = Irms

2× Rds(on)( )

+ Qg × Vg × f( ) + Qoss

2×Vin × f

+ Qrr × Vin × f( )

*dissipated primarily in Q1.

For the synchronous MOSFET Q2, Rds(on) is an im-portant characteristic; however, once again the im-portance of gate charge must not be overlooked sinceit impacts three critical areas. Under light load theMOSFET must still be turned on and off by the con-trol IC so the gate drive losses become much moresignificant. Secondly, the output charge Qoss and re-verse recovery charge Qrr both generate losses thatare transfered to Q1 and increase the dissipation inthat device. Thirdly, gate charge will impact theMOSFETs’ susceptibility to Cdv/dt turn on.

The drain of Q2 is connected to the switching nodeof the converter and therefore sees transitions be-tween ground and Vin. As Q1 turns on and off there isa rate of change of drain voltage dV/dt which is ca-pacitively coupled to the gate of Q2 and can inducea voltage spike on the gate that is sufficient to turnthe MOSFET on, resulting in shoot-through current .The ratio of Qgd/Qgs1 must be minimized to reduce thepotential for Cdv/dt turn on.

Power MOSFET Selection for Non-Isolated DC/DC Converters

Figure A: Qoss Characteristic

www.irf.com 9

0 - .

6.73 (.265)6.35 (.250)

- A -

4

1 2 3

6.22 (.245)5.97 (.235)

- B -

3X0.89 (.035)0.64 (.025)

0.25 (.010) M A M B

4.57 (.180)

2.28 (.090)

2X1.14 (.045)0.76 (.030)

1.52 (.060)1.15 (.045)

1.02 (.040)1.64 (.025)

5.46 (.215)5.21 (.205)

1.27 (.050)0.88 (.035)

2.38 (.094)2.19 (.086)

1.14 (.045)0.89 (.035)

0.58 (.023)0.46 (.018)

6.45 (.245)5.68 (.224)

0.51 (.020) MIN.

0.58 (.023)0.46 (.018)

LEAD ASSIGNMENTS

1 - GATE

2 - DRAIN

3 - SOURCE

4 - DRAIN

10.42 (.410)

9.40 (.370)

NOTES:

1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982.

2 CONTROLLING DIMENSION : INCH.

3 CONFORMS TO JEDEC OUTLINE TO-252AA.

4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP,

SOLDER DIP MAX. +0.16 (.006).

EXAMPLE:

LOT CODE 9U1P

THIS IS AN IRFR120WITH ASSEMBLY

WEEK = 16

DATE CODEYEAR = 0

LOGORECTIFIER

INTERNATIONAL

ASSEMBLYLOT CODE

016

IRFU120

9U 1P

Notes: This part marking information applies to devices produced before 02/26/2001

INTERNATIONAL

LOGORECTIFIER

3412

IRFU120

916A

LOT CODEASSEMBLY

EXAMPLE:WITH ASSEMBLYTHIS IS AN IRFR120

YEAR 9 = 1999DATE CODE

LINE AWEEK 16IN THE ASSEMBLY LINE "A"

ASSEMBLED ON WW 16, 1999LOT CODE 1234

PART NUMBER

Notes: This part marking information applies to devices produced after 02/26/2001

10 www.irf.com

0 - .

6.73 (.265)6.35 (.250)

- A -

6.22 (.245)5.97 (.235)

- B -

3X0.89 (.035)0.64 (.025)

0.25 (.010) M A M B2.28 (.090)

1.14 (.045)0.76 (.030)

5.46 (.215)5.21 (.205)

1.27 (.050)0.88 (.035)

2.38 (.094)2.19 (.086)

1.14 (.045)0.89 (.035)

0.58 (.023)0.46 (.018)

LEAD ASSIGNMENTS

1 - GATE

2 - DRAIN

3 - SOURCE

4 - DRAIN

NOTES:

1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982.

2 CONTROLLING DIMENSION : INCH.

3 CONFORMS TO JEDEC OUTLINE TO-252AA.

4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP,

SOLDER DIP MAX. +0.16 (.006).

9.65 (.380)8.89 (.350)

2X

3X

2.28 (.090)1.91 (.075)

1.52 (.060)1.15 (.045)

4

1 2 3

6.45 (.245)5.68 (.224)

0.58 (.023)0.46 (.018)

WEEK = 16

DATE CODEYEAR = 0

Notes: This part marking information applies to devices produced before 02/26/2001

EXAMPLE:

LOT CODE 9U1P

THIS IS AN IRFR120WITH ASSEMBLY

ASSEMBLY

INTERNATIONALRECT IFIER

LOGO

LOT CODE

IRFU120

9U 1P

016

INTERNATIONAL

LOGORECTIFIER

LOT CODEASSEMBLY

EXAMPLE:WITH ASSEMBLYTHIS IS AN IRFR120

YEAR 9 = 1999DATE CODE

LINE AWEEK 19

IN THE ASSEMBLY LINE "A"ASSEMBLED ON WW 19, 1999LOT CODE 5678

PART NUMBER

Notes: This part marking information applies to devices produced after 02/26/2001

56

IRFU120919A

78

www.irf.com 11

0 - .

TR

16.3 ( .641 )15.7 ( .619 )

8.1 ( .318 )7.9 ( .312 )

12.1 ( .476 )11.9 ( .469 )

FEED DIRECTION FEED DIRECTION

16.3 ( .641 )15.7 ( .619 )

TRR TRL

NOTES :1. CONTROLLING DIMENSION : MILLIMETER.2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).3. OUTLINE CONFORMS TO EIA-481 & EIA-541.

NOTES :1. OUTLINE CONFORMS TO EIA-481.

16 mm

13 INCH

Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market.

Qualification Standards can be found on IR’s Web site.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105TAC Fax: (310) 252-7903

Visit us at www.irf.com for sales contact information. 03/03

Repetitive rating; pulse width limited by max. junction temperature. Starting TJ = 25°C, L = 0.58mH, RG = 25Ω,

IAS = 12A. Pulse width ≤ 400µs; duty cycle ≤ 2%.

Calculated continuous current based on maximum allowable junction temperature. Package limitation current is 30A. When mounted on 1" square PCB (FR-4 or G-10 Material). For recommended footprint and soldering techniques refer to application note #AN-994.

Note: For the most current drawings please refer to the IR website at: http://www.irf.com/package/