Ch16p
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Transcript of Ch16p
Chapter 16 Exercise Solutions EX16.1
( )( )
( )( )( )( )
( )
147 2
8
19 14 15 12
7
3.9 8.85 101.726 10 F / cm
200 10
2 1.6 10 11.7 8.85 10 100.1055 V
1.726 100.576 0.576 0.1055 0.576 5 0.576
0.169 V
OX
TN SB
TN
C
V r V
V
γ
−−
−
− −
−
×= = ×
×
× ×= =
×⎡ ⎤ ⎡ ⎤Δ = + − = + +⎣ ⎦ ⎣ ⎦
Δ =
EX16.2 (a)
( )
( ) ( )( ) ( )
2
2
3 2 3 0.52
0.10.060.1 3 5 5 0.1 0.1
20.1 3 0.0735
39.5 K
o DD D D
no o o D
o
D
D
D
v V I Rk Wv v v R
Lv
R
RR
= −′⎛ ⎞⎛ ⎞ ⎡ ⎤= − − −⎜ ⎟⎜ ⎟ ⎣ ⎦⎝ ⎠⎝ ⎠
=
⎛ ⎞ ⎡ ⎤= − −⎜ ⎟ ⎣ ⎦⎝ ⎠= −=
(b)
( )( )( ) ( )
( ) ( )
( ) ( )( )( )
2
2
0.06 5 39.5 0.5 0.5 3 02
5.925 0.5 0.5 3 0
1 1 4 5.925 30.5
2 5.9250.632 V
1.132 V
It It
It It
It Ot
Ot
It
V V
V V
V V
VV
⎛ ⎞ − + − − =⎜ ⎟⎝ ⎠
− + − − =
− ± +− = =
==
EX16.3 (a) (i)
3 0.42.6 V
o DD TNL
o
v V Vv
= − = −=
(ii)
( ) [ ]
( ) [ ]
( )( )( )
22
22
2 2
2
2 0.4 0.4
16 2 2.6 0.4 2 3 0.4
35.2 8 6.76 5.29 40.4 6.76 0
40.4 1632.16 4 9 6.762 9
0.174 V
I o o DD oD L
o o o
o o o o
o o
o
o
W Wv v v V vL L
v v v
v v v vv v
v
v
⎛ ⎞ ⎛ ⎞⎡ ⎤− − = − −⎜ ⎟ ⎜ ⎟⎣ ⎦⎝ ⎠ ⎝ ⎠
⎡ ⎤− − = − −⎣ ⎦− = − +
− + =
± −=
=
(b)
[ ]260 (2) 3 0.174 0.42
353.1 A1.06 mW
D
D
D DD
i
iP i V
μ
⎛ ⎞= − −⎜ ⎟⎝ ⎠
== ⋅ =
EX16.4 (a)
( ) ( )( )
( ) ( )
( )( )
22
2
2
2 0.4 0.8
6 2 3 0.4 2 0.64
6 31.2 1.28 0
31.2 973.44 4 6 1.282(6)
41.4 mV
I o oD L
o o
o o
o
o
W Wv v vL L
v v
v v
v
v
⎛ ⎞ ⎛ ⎞⎡ ⎤− − = − −⎜ ⎟ ⎜ ⎟⎣ ⎦⎝ ⎠ ⎝ ⎠
⎡ ⎤− − =⎣ ⎦− + =
± −=
=
(b)
( ) ( )
( ) ( )
2 2
2
0.4 ( 0.8)
6 0.4 2 0.64
0.862 VDriver
0.862 0.4 0.462 V
0.862 VLoad
3 0.8 2.2 V
ItD L
It
It
Ot
It
Ot DD TNL
W WvL L
v
vv
vv V V
⎛ ⎞ ⎛ ⎞− = − −⎜ ⎟ ⎜ ⎟⎝ ⎠ ⎝ ⎠
− =
⇒ = ⎫⎬= − = ⎭
= ⎫⎬= + = − = ⎭
(c)
( )( )260 (2) 0.8 38.4 A2
115.2 W
D
D DD
i
P i V
μ
μ
⎛ ⎞= − − =⎜ ⎟⎝ ⎠
= ⋅ =
EX16.5 We have
{ }{ }
2 2
5 0.8 0.35 0.73 0.73
4.499 0.35 0.73
OH DD TNLO fP SB fP
OH OH
OH OH
V V V r V
V V
V V
φ φ⎡ ⎤= − + + −⎣ ⎦
⎡ ⎤= − + + −⎣ ⎦
− = − +
Squaring both sides 2
2
8.998 20.241 0.1225(0.73 )9.1205 20.15 0
9.1205 83.1835 4(20.15)2
3.76 V
OH OH OH
OH OH
OH
OH
V V VV V
V
V
− + = +− + =
± −=
=
EX16.6 a. i. logic 1 10 V, logic 0A B= = = “A” driver in nonsaturation. “B” driver off
( ) ( )
( ) ( ) ( )( )
( ) ( )( )
2 2
2 20 0
20 0
20 0
2
0 0
22 2
2 3 10 2 10 1.5
9 5 17
5 85 9 0
85 85 4 5 90.107 V
2(5)
nTNL I TND OL OL
L D
L L
L L
L L
L L
k W k WV v v V VL L
V V
V V
V V
V V
′ ′⎛ ⎞⎛ ⎞ ⎛ ⎞⎛ ⎞ ⎡ ⎤− = − −⎜ ⎟ ⎜ ⎟⎜ ⎟⎜ ⎟ ⎣ ⎦⎝ ⎠ ⎝ ⎠⎝ ⎠⎝ ⎠
⎡ ⎤= − −⎣ ⎦
= −
− + =
± −= ⇒ =
ii. A = B = logic 1
( ) ( )
( ) ( )( ) ( )( )
( ) ( )( )( )
2 2
2 20 0
20 0
20 0
2
0 0
2 22 2
2 3 2 10 2 10 1.5
9 10 17
10 170 9 0
170 170 4 10 90.0531 V
2 10
nTNL I TND OL OL
L D
L L
L L
L L
L L
k W k WV v v V VL L
V V
V V
V V
V V
′ ′⎛ ⎞⎛ ⎞ ⎛ ⎞⎛ ⎞ ⎡ ⎤− = − −⎜ ⎟ ⎜ ⎟⎜ ⎟⎜ ⎟ ⎣ ⎦⎝ ⎠ ⎝ ⎠⎝ ⎠⎝ ⎠
⎡ ⎤= − −⎣ ⎦
= −
− + =
± −= ⇒ =
b. Both cases.
( ) ( )235 2 3 315 A 3.15 mW2D D DDi P i V Pμ= ⋅ = ⇒ = ⋅ ⇒ =
EX16.7
( )
( )( ) ( )
2
2
800 160 A5
35160 1.4 34.3 4.662
35160 2 5 0.8 0.12 0.12 9.202
D DD D
DL L L
DD D
P i V i
W W WiL L L
W WiL L
μ= ⋅ ⇒ = =
⎛ ⎞ ⎛ ⎞ ⎛ ⎞= = ⋅ = ⇒ =⎜ ⎟ ⎜ ⎟ ⎜ ⎟⎝ ⎠ ⎝ ⎠ ⎝ ⎠
⎛ ⎞ ⎛ ⎞⎡ ⎤= = ⋅ − − ⇒ =⎜ ⎟ ⎜ ⎟⎣ ⎦⎝ ⎠ ⎝ ⎠
EX16.8
(a) 2.1 1.05 V2 2
1.05 ( 0.4) 1.45 V1.05 0.4 0.65 V
DDIt
OPt It TD
ONt It TN
VV
V V VV V V
= = =
= − = − − == − = − =
(b) 2.1 ( 0.4) 0.5(0.4) 1.16 V1 0.5
1.16 0.4 1.56 V1.16 0.4 0.76 V
It
OPt
ONt
V
VV
+ − += =+
= + == − =
(c) 2.1 ( 0.4) 2(0.4) 0.938 V1 2
0.938 0.4 1.338 V0.538 V
It
OPt
ONt
V
VV
+ − += =+
= + ==
EX16.9
( ) ( )( )
2
26 12
4
0.10 10 0.5 10 3
2.22 10 Hz 22.2 kHz
L DDP f C V
f
f f
− −
= ⋅ ⋅
× = ×
= × ⇒ =
EX16.10 a.
0
0
10 2 2.5(2)/ 200 / 80 2.5 4.32 V1 2.5
6.32 V2.32 V
n p It It
Pt
Nt
K K V V
VV
− += = ⇒ = ⇒ =+
==
b.
{ }0
0
0
0
10 2 2 2.52 2 1 3.39 V2.5 1 2.5 3
1 (1 2.5)(3.39) 10 (2.5)(2) 229.43 V
10 2 2 2(2.5)2 1 4.86 V2.5 1 3(2.5) 1
(4.86)(1 2.5) 10 (2.5)(2) 22(2.5)
0.802 V
IL IL
HU
HU
IH IH
LU
LU
V V
V
V
V V
V
V
⎡ ⎤− −= + ⋅ − ⇒ =⎢ ⎥− +⎣ ⎦
= + + − +
=
⎡ ⎤− −= + ⋅ − ⇒ =⎢ ⎥− +⎢ ⎥⎣ ⎦+ − − +=
=
c. 0
0
3.39 0.802 2.59 V
9.43 4.86 4.57 VL IL LU L
H HU IH H
NM V V NM
NM V V NM
= − = − ⇒ =
= − = − ⇒ =
EX16.11 3 PMOS in series and 3 NMOS in parallel. Worst Case: Only one NMOS is ON in Pull-down mode ⇒ same as the CMOS inverter .nW W⇒ = All 3 PMOS are on during pull-up mode 3(2 ) 6 .pW W W⇒ = = EX16.12 NMOS: Worst Case, ,NAM NBM on, 2( )nW W= or ,NCM NDM or NCM , NEM on 2( ).nW W⇒ = PMOS: PAM and PCM on or PAM and PBM on 2(2 ) 4WPW W⇒ = = If PDM and PEM on, need 2(4 ) 8WPW W= = EX16.13 a. 05 V 4 VIv vφ= = ⇒ =
b. 03 V, 5 V 3 VIv vφ= = ⇒ =
c. 4.2 V,Iv = 05 V 4 Vvφ = ⇒ =
d. 5 V,Iv = 03 V 2 Vvφ = ⇒ = EX16.14 (a) 8 ,Iv V= 10 8GSDV v Vφ = ⇒ =
DM in nonsaturation
[ ]
( )( ) ( ) [ ]
2
2
22
2( )
2 8 2 0.5 0.5 10 0.5 2 9.78
D GSD TND O O
L DD O TNL
D D
L L
K v V v v
K V v VK KK K
⎡ ⎤− −⎣ ⎦
− −
⎡ ⎤− − = − − ⇒ =⎣ ⎦
(b)
( )( ) ( ) [ ]22
8 6
2 6 2 0.5 0.5 10 0.5 2 15
I GSD
D D
L L
v V v VK KK K
φ= = ⇒ =
⎡ ⎤− − = − − ⇒ =⎣ ⎦
EX16.15 16 16384K ⇒ cells Total Power 125 (2.5) 50 T TmW I I mA= = ⇒ =
Then, for each cell, 50 3.05 16384
mAI I Aμ= ⇒ =
Now, DDVIR
≅ or 2.5 0.82 3.05
DDVR R MI
= = ⇒ = Ω
TYU16.1
2
2
2
750 150 A5
35150 (5 0.2 0.8)2
150 280 0.536
2( )235150 2(4.2 0.8)(0.2) (0.2)2
150 23.1 6.49
D DD D
L
L L
nD I TND O O
D
D
D D
P i V i
WLW WL L
k Wi v V v vL
WL
W WL L
μ= ⋅ ⇒ = =
⎛ ⎞= − −⎜ ⎟⎝ ⎠
⎛ ⎞ ⎛ ⎞= ⇒ =⎜ ⎟ ⎜ ⎟⎝ ⎠ ⎝ ⎠
′⎛ ⎞⎛ ⎞ ⎡ ⎤= − −⎜ ⎟⎜ ⎟ ⎣ ⎦⎝ ⎠⎝ ⎠⎛ ⎞ ⎡ ⎤= − −⎜ ⎟ ⎣ ⎦⎝ ⎠
⎛ ⎞ ⎛ ⎞= ⋅ ⇒ =⎜ ⎟ ⎜ ⎟⎝ ⎠ ⎝ ⎠
TYU16.2
( )
( )
( )( ) ( )
2
2
2
350 70 A5
23570 2 12
35 2 5 0.8 0.05 0.052
70 7.31 9.58
D DD D
nD TNL
L
L L
DD
D D
P i V I
k Wi VL
W WL L
WiLW WL L
μ= ⋅ ⇒ = =
′⎛ ⎞⎛ ⎞= −⎜ ⎟⎜ ⎟⎝ ⎠⎝ ⎠⎛ ⎞ ⎛ ⎞= ⋅ ⇒ =⎜ ⎟ ⎜ ⎟⎝ ⎠ ⎝ ⎠
⎛ ⎞ ⎡ ⎤= ⋅ − −⎜ ⎟ ⎣ ⎦⎝ ⎠
⎛ ⎞ ⎛ ⎞= ⋅ ⇒ =⎜ ⎟ ⎜ ⎟⎝ ⎠ ⎝ ⎠
TYU16.3
( )
( )( ) ( )
2
2
800 160 A5
35160 1.4 4.662
35 1160 A 2 5 0.8 0.12 0.12 27.62 3
D DD D
DL L
DD D
P i V i
W WiL L
W WiL L
μ
μ
= ⋅ ⇒ = =
⎛ ⎞ ⎛ ⎞= = ⋅ ⇒ =⎜ ⎟ ⎜ ⎟⎝ ⎠ ⎝ ⎠
⎛ ⎞ ⎛ ⎞⎡ ⎤= = ⋅ ⋅ − − ⇒ =⎜ ⎟ ⎜ ⎟⎣ ⎦⎝ ⎠ ⎝ ⎠
TYU16.4 a. From the load transistor:
( ) ( )( )2 235 0.5 5 0.15 0.72 2n
DL GSL TNLL
k WI V VL
′⎛ ⎞⎛ ⎞= − = − −⎜ ⎟⎜ ⎟⎝ ⎠⎝ ⎠
or 150.7 ADLI μ=
Maximum 0v occurs when either A or B is high and C is high. For the two NMOS is series, the effective
Nk is cut in half, so
( ) 21 22 2
nDL GSD TND DS DS
D
k WI V V V VL
′⎡ ⎤⎛ ⎞⎛ ⎞ ⎡ ⎤= − −⎢ ⎥⎜ ⎟⎜ ⎟ ⎣ ⎦⎝ ⎠⎝ ⎠⎣ ⎦
or
( )( ) ( )21 35150.7 2 5 0.7 0.15 0.152 2 D
WL
⎡ ⎤⎛ ⎞ ⎡ ⎤= ⋅ − −⎢ ⎥⎜ ⎟ ⎣ ⎦⎝ ⎠⎣ ⎦
which yields
13.6D
WL
⎛ ⎞ =⎜ ⎟⎝ ⎠
b. ( )( )150.7 5 753 WD DDP i V P μ= ⋅ = ⇒ = TYU16.5 a. 0 (max)v occurs when 1A B= = and 0C D= = or 0A B= = and 1C D= =
2 2
2 2
1( ) 2( )2
1(0.5)(1.2) 2(5 0.7)(0.15) (0.15)2
0.72 (0.634) 1.14
TNL I TND O OL D
D
D D
W WV v V v vL L
WL
W WL L
⎛ ⎞ ⎛ ⎞ ⎡ ⎤− = ⋅ − −⎜ ⎟ ⎜ ⎟ ⎣ ⎦⎝ ⎠ ⎝ ⎠
⎛ ⎞ ⎡ ⎤= ⋅ − −⎜ ⎟ ⎣ ⎦⎝ ⎠
⎛ ⎞ ⎛ ⎞= ⇒ =⎜ ⎟ ⎜ ⎟⎝ ⎠ ⎝ ⎠
b.
[ ]22 35( ) (0.5) ( 1.2)2 2
12.6 A(12.6)(5) 63 W
nD TNL
L
D
D DD
k Wi VL
iP i V P
μμ
′⎛ ⎞⎛ ⎞ ⎛ ⎞= − = − −⎜ ⎟ ⎜ ⎟⎜ ⎟⎝ ⎠ ⎝ ⎠⎝ ⎠== ⋅ = ⇒ =
TYU16.6 a.
2
2 2
50 /
2.5 V
(max) ( ) 50(2.5 0.8) (max) 145 A
n p
It
D n It TN D
K K A V
V
i K V V i
μ
μ
= =
=
= − = − ⇒ =
b. 2
2
200 /
2.5 V
(max) (200)(2.5 0.8) (max) 578 A
n p
It
D D
K K A V
V
i i
μ
μ
= =
=
= − ⇒ =
TYU16.7 a.
0
0
5 2 (1)(0.8)1 1
1.9 V3.9 V1.1 V
It
It
Pt
Nt
V
VVV
− +=+
===
b.
{ }
{ }
0
0
0
0
30.8 [5 2 0.8] 1.63 V8
1 2(1.63) 5 0.8 224.73 V
50.8 (5 2 0.8) 2.18 V8
1 2(2.18) 5 0.8 220.275 V
IL IL
HU
HU
IH IH
LU
LU
V V
V
V
V V
V
V
= + ⋅ − − ⇒ =
= + − +
=
= + − − ⇒ =
= − − +
=
c. 0
0
1.63 0.275 1.35 V
4.73 2.18 2.55 VL IL LU L
H HU IH H
NM V V NM
NM V V NM
= − = − ⇒ =
= − = − ⇒ =
TYU16.8
TYU16.9
( )
( )
NMOS 2 transistors in series2 2W
PMOS 2 transistors in series2 2 4W
n
p
W W
W W
−= =
−= =
TYU16.10 The NMOS part of the circuit is:
TYU16.11 The NMOS part of the circuit is:
TYU16.12 Exclusive-OR A B f 0 0 0 1 0 1 0 1 1 1 1 0
TYU16.13
NMOS conducting for 0 4.2 VIv≤ ≤ ⇒ NMOS Conducting: 0 8.4 st≤ ≤ NMOS Cutoff: 8.4 10 st≤ ≤ PMOS cutoff for 0 1.2 VIv≤ ≤ ⇒ PMOS Cutoff: 0 2.4 st≤ ≤ PMOS Conducting: 2.4 10 st≤ ≤
TYU16.14 (a) 1 32 32K ⇒ × array Each row and column requires a 5-bit word ⇒ 6 transistors per row and column, 32 6 32 6 384⇒ × + × = transistors plus buffer transistors. (b) 4 64 64K ⇒ × array Each row and column requires a 6-bit word ⇒ 7 transistors per row and column 64 7 64 7 896⇒ × + × = transistors plus buffer transistors. (c) 16 128 128K ⇒ × array Each row and column requires a 7-bit word ⇒ 8 transistors per row and column
128 8 128 8 2048⇒ × + × = transistors plus buffer transistors. TYU16.15 From Equation (16.84) ( )( )
( )( ) ( )
2 2
2 21
/ 2 3 2(2.5)(0.4) 3(0.4) 0.526/ 2 2.5 2(0.4)
DD TN TNnA
n DD TN
W L V V VW L V V
− −= = =− −
From Equation (16.86)
( )( )
( )( )
2 2
2 2
/ 2 3 2(2.5)(0.4) 3(0.4)(2.5) 0.862/ (2.5 0.4)
p DD TN TNn
pnB DD TP
W L V V VkW L k V V
−′ ⎡ ⎤−= ⋅ = =⎢ ⎥′ −+ ⎣ ⎦
So WL
⎛ ⎞⎜ ⎟⎝ ⎠
of transmission gate device must be 0.526< times the WL
⎛ ⎞⎜ ⎟⎝ ⎠
of the NMOS transistors in the
inverter cell. The WL
⎛ ⎞⎜ ⎟⎝ ⎠
of the PMOS transistors must be 0.862< times the WL
⎛ ⎞⎜ ⎟⎝ ⎠
of the transmission gate
devices. Then the WL
⎛ ⎞⎜ ⎟⎝ ⎠
of the PMOS devices must be 0.453< times WL
⎛ ⎞⎜ ⎟⎝ ⎠
of NMOS devices in cell.
TYU16.16 Initial voltage across the storage capacitor 3 0.5 2.5 .DD TNV V V= − = − = Now
dVI Cdt
− = or IV t KC
= − ⋅ +
where 2.5 ,K V= 1.5 ,t ms= 2.5 1.25 ,2
V V= = and 0.05 .C pF= Then
3
12
11
(1.5 10 )1.25 2.5(0.05 10 )
4.17 10 41.7
I
I A I pA
−
−
−
×= − ⇒×
= × ⇒ =