C.  Della  Fiore,  F.  Maloberti:  "Design  of  ΣΔ  Modulators  with  Reduced  Number  of   Operational   Amplifiers";   Proc.   of   the   European   Conf.   Circuit   Theory   and  Design,  ECCTD  2005,  Cork,  28  August  2005,  Vol.  1,  pp.  205-­‐208.  

 

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Design of !" Modulators with Reduced Number of Operational Amplifiers

Cristina Della Fiore# Franco Maloberti*

# Department of Electronic, University of Pavia, via Ferrata 1, 27100 Pavia, Italy, e-mail: [cristina.dellafiore,franco.maloberti]@unipv.it, tel.: +39 0382 985226, fax: +39 0382 985677.

Abstract $ A method that reduces the number of operational amplifier used in sigma delta modulators is described. The approach together with the double sampling method permits the designer to obtain very low figure of merits (and low power) as required by portable wireless applications. The proposed technique is applied to second and third order architectures. The limits due to capacitor mismatches make the approach useful for medium resolution and low over-sampling ratios. A case study meeting typical WCDMA specification is given.

1 INTRODUCTION

Sigma Delta (!") modulators are good solutions for answering the data conversion requirement of wireless portable applications. The specifications for 3G systems require medium resolution (from 60 to 75 dB) bandwidth in the 2 MHz range and very low power consumption. The use of high over-sampling ratio (OSR) obtains good resolutions. However, the high sampling frequency leads to high power consumption in the op-amps. The use of high order modulators enhances the noise shaping. On another hand, the number of op-amps increases, being required one op-amp per integrator. The use of multi-bit architecture helps in obtaining extra bits. However, multi-bit requires using flash ADC and can require using the dynamic element matching (DEM) in the DAC if unity elements are kept at the minimum permitted by the technology.

The above considerations show that the choice of the best architecture is a proper trade-off between different design parameters. In addition it is possible to use special techniques like the double sampling and the op-amp sharing for obtaining a reduction of power consumption.

This paper describes a technique that reduces the number of operational amplifiers used in an high order modulator. The method is different from the op-amp sharing technique since it does not require using a specific time-slot per op-amp function. The method can be applied to any modulator order. The approach recently proposed in [1] is a particular case of the method described here. The following illustrates the technique that is applied to second-order and third order architectures. Than, the paper analyzes the limitations due to element mismatches.

2 THE METHOD

Fig. 1 shows a quite general architecture of !" modulator. It is the cascade of n analog blocks (typically integrator) followed by an ADC and n feedbacks from the digital output. Feed-forward of the analog input are not used.

Figure 1: Generic sigma-delta architecture

Basic observation is that the feedback path at the input of the i-th stage can be moved to the input of the previous (i-1)-th stage by dividing its contribution by Hi-1(z). Since the feedback from the digital output requires using digital-to-analog conversion, the signal processing can be possibly performed in the digital domain before the DAC. If all the feedbacks are moved up to the first feedback position, the circuit of Fig. 1 becomes the one shown in Fig.2. The coefficient kT is

% kT & k1 'k2

H1(z)' ...' kn

H1(z)H2(z)...Hn$1(z)% ()*%

The cascade of analog blocks H1(z), …, Hn(z) has

only one input and one output and can be realized with a minimum number of operational amplifiers.

Figure 2: Sigma-delta with removed internal feedbacks

The scheme of Fig. 2 removes all the internal

feedback branches. However, it is possible to have a partial removal with, for example, two sum points instead of one. The removal strategy depends on the optimum implementation of the resulting architecture and on the possible stability problems that the practical circuit may have. Thus, the proposed method is a transformation technique of the modulator architecture for an optimum circuit implementation.

H1(z) H n (z ) H2(z)

k1 k2 k n

x y-+ -+ - +

H1(z) H n (z ) H2(z)

kT

x y-+

The transfer function of the cascade HT(z) of a number of linear blocks is, obviously, the product of the transfer function of single blocks H1(z), …, Hn(z). Since sigma delta modulators use integrators we will have

n

p

T zzzH

)1()( 1$

$

$& ! "

where, n is the number of cascaded integrator and p is the total delay around the loop.

The circuit implementation of (2) can be based on the block diagram of Fig. 3. The filter Pn(z) is given by

% + ,1)1()( 1 $$$& $ nn zzzP % (-*%

Thus, for n=2 and n=3 we obtain

% P2(z) & 2 $ z$1% (.*%

% 213 33)( $$ '$& zzzP % (/*%

that are simple transversal filters with integer coefficients. If the filter Pn(z) is achieved in a passive way (using weighted capacitors for realizing analog delayed storing elements) it is necessary to use only one operational amplifier for the summing operation. As a result we can obtain a second or third order modulator using as key power consuming elements just one op-amp and the quantizer.

Figure 3: Basis for circuit implementation of (2)

3 2-ND AND 3-TH ORDER MODULATORS

The above-described method is applied to a second and a third order modulator. Fig. 4 shows two popular second order architectures. Two integrators one without delay the second one with delay make the first one (top). The second architecture (bottom) uses two integrators with delay and uses gains ½ and 2 to minimize the swing at the output of the first integrator. The removal of the second feedback leads to the following kT coefficients

%)( 12

)( 2 1

bottomzktopzk

T

T

$&$& $

% (0*%

the coefficient kT of the bottom architecture is obviously not achievable. However, the analog transfer function has a double delay around the loop. We can

incorporate one of these delays on the digital section of the loop to obtain a feasible kT.

Figure 4: Architectures of second order sigma-delta

modulator.

The result, for both architectures, is the schematic shown in Fig. 5. The additional delay on the input applies for the bottom scheme of Fig. 4. The analog function enclosed in the big rectangle can be implemented with only one op-amp. The use of fully differential circuits facilitates the realization of positive or negative coefficients. The additional delay can be obtained with two sampling capacitors used in interleaved fashion.

1$z1$zx

++ +

1$z

-1

2

DAC

yADC

12 $$ z

-+

Figure 5: Circuit implementation of the modulator of

Fig. 4

Fig. 6 shows a third order modulator. The removal of the intermediate feedbacks lead to the kT coefficient

33 21 $$ '$& zzkT % (1*%

1 1

x y11

1$$ z 1

1

1 $

$

$ zz

1

111

$$ z

kT

x y11

1$$ z 1

1

1 $

$

$ zz

111

$$ z

(a)

(b)

-+ -+ -+

-+

%

Figure 6: Third order modulator and its modified version%

+ +

P n(z)

) 1 ( $ $ p z 1 $ z

1 1

x y11

1$$ z 1

1 1 $

$ $ z z

1 1

x y1

1

15.0

$

$

$ zz

1

1 1 2

$ $

$ z z

-+ -+

-+ -+

Fig. 7 shows the block diagram for the circuit implementation. The analog section has only one summing node and, as it is for the second order case, it is possible to achieve the function with only one operational amplifier.

Figure 7: Implementation of the scheme of Fig.6 b)

4 EFFECT OF MISMATCHES

Switched capacitor circuits implementing the schemes in Fig. 5 and Fig. 7 achieve the required coefficients by proper capacitor ratios. The coefficients are integer; thus, the accuracy is normally good. However, real implementations are always affected by error. Inaccurate coefficients cause a shift of zeros and poles position of the transfer functions. The effect on the signal transfer function is negligible. A shift in zeros of the noise transfer function modifies the noise shaping. Fig. 8 shows the output spectra for ideal and real coefficients (third order, low pass modulator, mismatch 0.2%). The zeros move from z = 1 and determine a flat noise at low frequency. The effect is significant only if the total noise power largely increases. This depends on the expected SNR and the level of mismatch.

104 105 106 107-300

-250

-200

-150

-100

-50

0

Ideal coefficientsReal coefficients

Figure 8: Output spectra for ideal and real analog

coefficients.

Observe that, because of the shaping, the major noise contribution comes from the frequency region near the signal band limit, fB. A possible flat noise at low frequency is irrelevant if it is kept below the spectrum level at fB. Thus, for the spectrum in Fig. 8 a noise floor even at -110 dB (FFT with 8196 points) is acceptable if the signal band is 2 MHz.

Let us consider a third order modulator with OSR = 10 and 12-levels quantization. The SNR for ideal coefficients and -3 dB input signal is 69 dB (11.2 bits). A statistical study based on real coefficients with 0.2%, 0,4%, 0,6% and 0.8% variance leads to the histograms of Fig. 9. The results are based on 100 samples Monte Carlo analysis. The figure shows that with 0.2% variance the loss of resolution is around 3 dB (half a bit). For 0.8% variance the loss can be 2 bits. The mismatch of capacitors in the 0.1 pF range and modern CMOS technologies causes variances lower than 0.25%,. Therefore, the proposed method is suitable for 10-11 bit of resolution and OSR as low as 10.

Figure 9: Histogram of the resolution loss (0.2-

0.8% variances).

5 DAC IMPLEMENTATION

The proposed circuit realizations have only one feedback from the digital output and the input. Because of the action of the kT filter the number of quantization levels of the DAC is larger than the ones of the ADC. Assume that the ADC has 12 levels to cover the full-scale input range; the third order architecture requires using 48 levels (less than 12 x (3+|-3|+1) = 84) with -3dBFS input. The extra levels are necessary because of the high frequency noise components brought to the input by the kT=(3-3z-1+z-2) filter.

Low power applications implement the DAC with an array of switched capacitors elements that possibly realize also the injection of the input signal. A straightforward realization of a third order modulator with 12 levels ADC requires using 48 unity elements DAC. If the capacitor used in the integrator is CI, the input capacitance is 48/12CI. The resulting op-amp

1 $zx - +

1 $ z

1

3

DAC

yADC

2 $ z

-

2 1 33 $ $ ' $ z z

!

feedback factor imposes a higher bandwidth for the single op-amp used. However, the saving of power is still significant.

Figure 10: Histogram of abs(out) for Vin=-65dBFS

With 11-bit of resolution, having a DAC with 48 unity elements is normally problematic. The mismatch between elements cannot be averaged properly and, in order to have a good matching it is necessary to use large capacitors whose value is larger than what required by the kT/C constraint. As a result the power consumption increases and the benefit of using a single op-amp vanishes.

Fortunately the above observation is not valid for the used scheme. Remind that the dynamic element matching is necessary because for given input amplitude only k or k+1 unity elements are exercised. The mismatch between the set of elements used and the reminder causes harmonic distortion. The DEM transforms the mismatch into noise since it averages the use of elements. Fig. 10 shows that histogram of the absolute value of the output (262144 points) with a very low input (-65dBFS). The figure shows that many elements are used. Therefore, the mismatch between them is naturally averaged and the system possibly requires just a simplified DEM scheme.

The set of comparators of the flash ADC generates a thermometric code. The filter output requires performing a thermometric-binary coding, the transversal filter operations and back to thermometric for the ADC control. An alternative way is the one used in [1]. For a second order architecture, (OSR=20) two DACs are used. They realize the 2 coefficient and the -z-1 term of kT=2-z-1 respectively. The solution just requires using a z-1 delay of the thermometric code. Double elementary capacitors obtain the gain 2. Thus, with a 6 levels ADC the DAC requires 3x6 unity capacitors, more than the minimum required by the dynamic range at the output of the kT filter: 12 levels.

The use of a similar approach to the third order modulator would require three DACs with gain 3, -3 and 1 and one delay on the second and two delay on the third DAC. Another option is to separate the input referred contributions and to drive three DACs with 1, 1-z-1 and (1-z-1)2 as shown in Fig.11 .

Figure 11: Possible DAC realizations for a third order circuit.

5 CASE STUDY

Let us consider the specification requirements for WCDMA. The signal bandwidth is 1.92 MHz, the required SNDR is 60 dB. The use of a single op-amp, double sampling technique and OSR = 20 meet the specifications with a 5-levels ADC. Experimental results reported in [1] show power consumption as low as 1.2 mW. The power is 45% less than the two op-amp realization given in [2]. The two op-amps architecture used a scaling of the power in the second op-amp by 40%. however, the increased feedback factor imposes a 20% increase in the op-amp power consumption. Thus, the benefit of the single op-amp is 25%. However, the double sampling technique permits another 35% power saving leading to the state-of-the-art result.

The use of a third order modulator with 12-level ADC achieves the WCDMA specifications with OSR = 10. With the double sampling technique the clock frequency is only 19.2 MHz, thus requiring an op-amp with unity-gain frequency in the 40 MHz range and estimated current consumption of 0.4 mA. The current budget for the ADC can be 0.2 mA and 0.1 mA for the digital part. Therefore, the expected power consumption with 1.2V can be as low as 0.85 mW.

The performances of the circuit remain good even when using a real op-amp. Simulation using the package in [3] show that with dc gain 60dB, GBW=40MHz and SR=90MV/s the SNR is 70.3dB just 1.6dB below the case with ideal OTA.

References

[1] J. Koh, Y. Choi, G. Gomez: “A 66dB DR 1.2V 1.2mW Single-Amplifier Double-Sampling 2nd-order #" ADC for WCDMA”, IEEE-ISSCC 2005, pp.170-171

[2] J. Yu, F. Maloberti: “A low power multi-bit SD Modulator in 90nm Digital CMOS without DEM”, IEEE-ISSCC 2005, 9.2, pp.168-169.

[3] P. Malcovati, S. Brigati, F. Francesconi, F. Maloberti, P. Cusinato and A. Baschirotto, “Behavioral Modeling of Switched-Capacitor Sigma-Delta Modulators”, IEEE Transaction on Circuits and Systems I, vol. 50, pp. 352-364, March 2003