Integrated Systems Laboratory (IIS)

Analog and Mixed-Signal IC Design Group

Prof. Dr. Qiuting Huang

19th March - 14th September 2007

A Multi-Standard ADC forCellular and WLAN in 65nm

CMOSMaster Thesis

Σ∆

Authors AdvisorTomislav Cvetic Thomas ChristenStephan Senn

Co-AdvisorCraig Keogh

This master thesis deals with the design of a reconfigurable wideband Σ∆-modulatorfor the cellular standards GSM-EDGE and UMTS as well as for the WLAN standardsIEEE 802.11a/b/g and the proposal draft n. A 4th order feed-forward Σ∆-modulator isevaluated and optimized in MATLAB and later implemented in 65nm CMOS in Cadence.The designed Σ∆-modulator fulfills the target specifications for all standards. In detail,it supports a bandwidth that reaches from 100kHz to 20MHz. Further, it has a dynamicrange of 88dB / 79dB / 71dB / 64dB for GSM-EDGE / UMTS / WLAN a/b/g / WLAN nrespectively. Its input stable range is 0.8FS for a differential input swing of 1.4V at a supplyvoltage of 1.2V.

iv

Contents

1 Introduction 11.1 ADC Basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.1.1 Introduction to Σ∆-Converters . . . . . . . . . . . . . . . . . . . . . 31.1.2 Structure of Σ∆-Converters . . . . . . . . . . . . . . . . . . . . . . . 41.1.3 Importance of Σ∆-Converters in Todays Electronics . . . . . . . . . 5

2 System Design 72.1 Transfer Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.1.1 Topologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72.1.2 Effects of Pole-Zero-Placements . . . . . . . . . . . . . . . . . . . . . 82.1.3 Optimization Methods . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.2 System Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112.2.1 System Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . 112.2.2 Goal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122.2.3 Cost Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132.2.4 System Optimization Problem . . . . . . . . . . . . . . . . . . . . . 15

2.3 Multi-Standard Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . 162.4 Hardware-Related Architecture-Transformations . . . . . . . . . . . . . . . 17

2.4.1 Limited Amplifier-Swing Compensation . . . . . . . . . . . . . . . . 172.4.2 Fractions of Small Integers for Path Gains . . . . . . . . . . . . . . . 19

2.5 Chosen Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212.5.1 Signal Flow Graph . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212.5.2 Scaled Signal Flow Graph . . . . . . . . . . . . . . . . . . . . . . . . 212.5.3 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3 Circuit Design 253.1 Main Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.1.1 Circuit Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253.2 Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.2.1 Thermal Noise Calculations . . . . . . . . . . . . . . . . . . . . . . . 303.2.2 Thermal Noise Transfer Functions . . . . . . . . . . . . . . . . . . . 313.2.3 Capacitor Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333.2.4 Variable Capacitor C13 . . . . . . . . . . . . . . . . . . . . . . . . . 343.2.5 Consequences for the Circuit-Scalability . . . . . . . . . . . . . . . . 35

3.3 Quantizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363.3.1 The Ideal Quantizer . . . . . . . . . . . . . . . . . . . . . . . . . . . 363.3.2 Calculation of the Reference Voltages . . . . . . . . . . . . . . . . . 363.3.3 Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

v

vi Contents

3.4 Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413.4.1 Categories of Comparators . . . . . . . . . . . . . . . . . . . . . . . 413.4.2 Implemented Comparator Design . . . . . . . . . . . . . . . . . . . . 423.4.3 Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . 423.4.4 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

3.5 Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513.5.1 Design-Parameter Calculation . . . . . . . . . . . . . . . . . . . . . . 513.5.2 Main Amplifier Design . . . . . . . . . . . . . . . . . . . . . . . . . . 533.5.3 Regulating Amplifier Design . . . . . . . . . . . . . . . . . . . . . . . 543.5.4 Common-Mode Feedback . . . . . . . . . . . . . . . . . . . . . . . . 543.5.5 Amplifier Bias-Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . 573.5.6 Overall Amplifier Performance . . . . . . . . . . . . . . . . . . . . . 58

3.6 Input-Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613.6.1 DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613.6.2 Dynamic Element Matching . . . . . . . . . . . . . . . . . . . . . . . 61

3.7 Bootstrap Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643.7.1 Working Principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643.7.2 Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . 643.7.3 Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

3.8 Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693.8.1 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693.8.2 Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

4 Results 714.1 Dynamic Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 724.2 Temperature and Process Variations . . . . . . . . . . . . . . . . . . . . . . 744.3 Total Power Consumption and Conversion Energy . . . . . . . . . . . . . . 764.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

5 Conclusion and Outlook 79

Appendix 81

Preface

This master thesis was carried out at the Integrated Systems Laboratory (IIS) in the Ana-log and Mixed-Signal IC Design Group of Prof. Dr. Quiting Huang. This institute is partof the Department of Information Technology and Electrical Engineering (D-ITET) at theSwiss Federal Institute of Technology (ETH) in Zurich.

The aim of this master thesis was the design of a wideband Σ∆-modulator for the cellularstandards GSM-EDGE and UMTS as well as for the WLAN standards IEEE 802.11a/b/gand the proposal draft n. As the spread of the design parameters (bandwidth, resolution,dynamic range, over-sampling ratio, etc.) is high, the design is very challenging. A furtherdelicate requirement is the low voltage operation which requires a high input stable range.As such Σ∆-modulators are mainly used in mobile devices, the power consumption shouldbe kept as low as possible.

Chip design is team work. This project would not have been possible without the helpand the advice of other people. Therefore, we would like to express our gratitude to thosepeople. First, we would like to thank our advisor Thomas Christen for his professionalsupport and his useful hints. He gave us enough space to pursuit our own ideas but inter-vened whenever he saw that we were on the wrong path. We would also like to thank ourco-advisor Craig Keogh and his workmate Jurg Treichler for their help at various problems.Finally, we would like to thank Prof. Dr. Quiting Huang for the possibility of carrying outsuch an interesting master thesis. We have learned quite a lot in analog IC design duringthese six months.

At the end of our study, we would also like to thank our parents, our friends, our col-leagues and all those people who motivated us during our long study. Without this moti-vation, such a lengthy and laborious study would not have been possible.

Zurich, 14th September 2007

Tomislav Cvetic

Stephan Senn

vii

Institut fur Integrierte SystemeIntegrated Systems Laboratory

Diploma Thesis at the Dept. ofInformation Technology and Electrical Engineering

Summer term 2007

for

Stephan Senn and Tomislav Cvelic

A Multi-Standard ADC for Cellularand WLAN in 65nm CMOS

Advisor: Thomas Christen, ETZ J90, 01 632 66 36, christen@iis.ee.ethz.chCo-Advisor: Craig Keogh, ETZ J90, 01 632 55 28, keogh@iis.ee.ethz.ch

Handout: Monday, 19. March 2007Due: Friday, 14. September 2007

Two copies of the written report are to be turned in. Both copies remain the propertyof the Integrated Systems Laboratory.

1 Introduction

The increasing need for cheap and ubiquitous wireless standards continuous to pre-cipitate advanced radio standards. This trend is illustrated in Fig. 1. The resultingmultitude of wireless standards calls for radios that allow convergence of wireless ser-vices, allowing access to different standard from the same devices. Software-definedradio (SDR) systems are therefore potentially the next main improvement in mobileand wireless communications.

End-user mobility

2G

3G

Typ

ical

end

-use

r da

ta r

ates

802.11bWLAN

802.11a/gWLAN

GSM

GPRS/EDGE

UMTS

LTE

Bluetooth

WiMax

2000

2005

Figure 1: Evolution of wireless standards.

As advances in technology provide increasingly faster and less expensive digital hard-ware, more of the traditional analog functions of radio receivers will be replaced withdigital hardware. Trends in receiver design have evolved by incorporating digitizationcloser and closer to the receive antenna. Because analog circuitry is usually seenas an impediment to programmability, the digitization of radios is highly desirable inmulti-standard transceivers.

The A/D converter in the receive path has therefore become one of the key elementsin multi-standard receiver design. Fig. 2 shows the block diagram of a (direct con-version) receiver (often used for multi-standard designs), consisting of an antennafollowed by a low-noise amplifier (LNA), a mixer, channel filtering which usually in-corporates programmable gain (PGA) and finally the ADC, followed by the digitalfront-end (DFE).

ADCs are uniquely suited to fully-integrated RF baseband applications for a cou-

ple of reasons. First, because their quantization noise is shaped with a high-passcharacteristic, most of the noise energies fall in the same band as the undesiredblockers. The same digital decimation filter can therefore be used to attenuate boththe quantization noise and the blockers. This relaxes the requirement on the pre-

1

0°90°

ADC

ADC DFE

DFE I-channel

Q-channel

Figure 2: Direct conversion receiver architecture.

ceding channel filter. Second, the same

ADC architecture, differing only in over-sampling ratio, can be used to adapt to the different dynamic range and bandwidthrequirements of multiple RF standards. The ability of

modulators to trade band-

width for resolution makes them well suited for the design of multi-standard ADCs.

2 Thesis

Due to the fully developed infrastructure for standards like GSM, these incumbentstandards need to be retained in mobile terminals, despite of the introduction of 3G-standards like UMTS. Furthermore, future mobile devices will most probably combinethe high mobility offered by cellular standards with the high data rates of WLAN. Thissemester thesis projects is therefore dedicated to the design of a multi-standard

ADC for cellular- (GSM/EDGE, UMTS) and WLAN-standards (IEEE802.11a/b/g/n).

The main challenges of this work include the following topics:

• Performance: Since users will expect the performance of a multi-standard de-vice to be at least as good as for current single-standard devices, the powerconsumption of the envisaged multi-standard

modulator should be com-

parable to state-of-the-art single-standard implementations. This presumes afigure-of-merit (FOM) 0.2pJ/conv.

• Re-configurability: The spread of bandwidth and resolution between the differ-ent standards is very high. It is therefore important that the

modulator

topology is well suited for a wide range of oversampling ratios (OSRs) and allowsprogrammability to be incorporated easily.

• Low voltage operation: The decreasing power supply of modern deep-submicrontechnologies puts new challenges on the design of ADCs. New

topology have

profilirated in order to cope with the low supply voltages.

2

3 Introduction to DT-

Modulation

Delta-sigma modulation is currently a popular technique for making high-resolutionanalog-to-digital and digital-to-analog converters. These oversampled data convert-ers have several advantages over conventional Nyquist-rate converters, including aninsensitivity to many analog circuit imperfections, a simpler anti-aliasing filter andreduced accuracy requirements in the sample-and-hold. These desirable featuresare achieved by oversampling the signal, by employing single-bit quantization and byshaping the quantization noise spectrum in such a way that the quantization noisein the band of interest is virtually eliminated [1].

A(u)

A/D (Quantizer)

D/A

q(w,e)

f(y)

x u w yn

- n

e

Figure 3: Generic ADC as tracking loop

We start the explanation of the

technique with the introduction of a genericADC model in the form of a tracking loop. Many ADCs types such as dual-slope,successive approximation or

converters can be mapped to this scheme. In Fig. 3

the input signal is first subject to the loop function and then quantized in theA-to-D part introducing an error signal to render the output signal with bit reso-lution. The quantizer function is inherently non-linear, but for ease in mathematicaltreatment it is usually modeled in additive form as

(1)

where the error is considered to be random with flat spectral distribution. The quan-tized output signal is fed back to the input and subtracted from the input signal. Ifwe assume high gain of the loop function then, with insertion of Eq. (1) and use ofoperator notation the output signal can be expressed as

! #"$"$% &#"'"$( )"$% &)"'*"+( ,-, .0/21435,-, 6 ,-, .0701435,-, 89:;:#:<:=:#:=:#:=:#:=:> @?A(CB

9"$D ( B

9"$ (2)

where we have assumed that commutative and distributive laws are valid for theoperations and ( . Eq. (2) reveals several important properties of the generic ADC: tracks with the inverse function of ( as desired. If we chose e.g. (EF( B

9 %

then equals directly. The quantization error is attenuated by the gain of the function

3

. Eq. (2) also shows the component that determines linearity and resolution of thegeneric ADC: it is the D/A part. The quantizer essentially only serves to make thedecision on what digital number is to be applied to the D/A function and does notaffect linearity or resolution. For instance, in a traditional successive approximation(SA) ADC the quantizer is only one bit wide and a sequential logic is used to determinethe binary code for the inside DAC bit by bit, starting from MSB down to the LSB.When the quantizer decision levels remain the same, then the equivalent loop gainfor the SAR converter is increased by a factor of 2 for every step which leads to afinal error smaller than an LSB in accordance to Eq. (2). To obtain a resolution of bit for a SA-ADC the internal ADC and DAC must operate times faster than theNyquist rate of the input signal. In a low pass

modulator the tracking loop is

driven even higher in speed with the possibility to reduce the number of bits in theinternal DAC from down to few bits and ultimately only 1 bit, and, hence the samein the ADC. The one bit DAC is guaranteed to be free from differential non-linearitybecause there is only one step. The key element to achieve high performance withthis kind of operation is to make the loop function frequency selective, i.e. isa filter that provides high gain inside the signal band and low gain elsewhere. Theloop filter affects signal and error in different ways: the high inband gain stillguarantees that ( B

9 holds for the signal whereas the error is attenuated most

in the signal band and starts to rise outside. Fig. 4 illustrates this concept for alow pass modulator where the loop filter is of low-pass type. The previously flatspectrum of the error is “noise shaped” to high pass characteristic whereas the inputsignal is unaffected. The achievable performance for the spectral shaping of the errorsignal is dependent on the ratio of the internal clock rate to the Nyquist rate of theinput signal which is called the oversampling ratio of the modulator:

(( ( ( (3)

where we have used the relationship ( ( between Nyquist rate and signal band-width to derive the right hand side. The performance also depends on the steepnessof the filter characteristic, i.e. the order of the loop filter. Thus, we have mainly twoparameters at hand to design

modulators: oversampling ratio and order of the

loop filter.The digital output signal of a

modulator contains both the input signal and

the spectrally shaped quantization error. The latter has to be removed by a digitalfilter to obtain the input signal alone. Because the necessary rate to represent theinput signal in digital form after filtering is the input signals Nyquist rate, the outputrate of the digital filter can be reduced down to that rate whereby the number of bitsto represent the input signal is increased to maintain accuracy. Running the entiredigital filter at ( would result in excessive power consumption and should thereforebe avoided. The combined digital filter and down-sampler is commonly known asdecimator or decimation filter. The combination of modulator loop and decimationfilter build a complete

converter. Fig. 5 shows the discrete-time model of a single-

loop

converter.The decimation filter makes up a substantial part of the area and power consump-

tion of a

converter. The complexity of the decimator grows with the steepness of

4

Original powerspectral density of E

Power spectraldensity of Eat the output

Input signalband

Reduction ofnoise due tofeedback loop

fs/2log f

log Pwr

Figure 4: The concept of noise shaping

H(s) A/D

D/A

-

x(t) y(kTs)Dec.

fs

fs

z(k⋅M⋅Ts)

e(kTs)

Figure 5: Single loop discrete-time

converter

the loop filter function and its proximity to the input signal band. This is the areafor trade-offs between modulator and decimation filter, a topic that goes beyond thescope of this thesis. Here, we concentrate on the analysis and optimization of themodulator, but we should keep in mind that for an optimum converter solution theparameters of the modulator may change as compared to those for an optimal mod-ulator solution alone. So we leave decimation here and pursue with the modulatorpart.

In order to efficiently analyze and design

modulators the quantization andstaircase functions in the internal ADC and DAC are commonly linearized. Conven-tional filter design techniques can then be applied. Fig. 6 shows the linear modulatormodel in its time-discrete form where all signals and functions are represented bytheir s-transform as appropriate for the description of continuous time systems. Forconvenience in mathematical treatment a gain of one has been assumed for ADC and

5

H(s)-

X(s) Y(s)

E(s)

Figure 6: Linearized model of single-loop discrete-time modulator

DAC. For the linear model we then have

) % %% ) (4)

where

% (5)

%% (6)

are called the signal transfer function and the noise transfer function, respectively.They share the relationship

% : (7)

which can easily be derived from their definition.With this brief introduction you should be able to understand the principal be-

havior of

modulators and the main parameters that govern its performance. Thediscussion of different types of architectures as well as the detailed treatment of im-perfections that influence their performance is omitted here. We recommend [1] for adeeper discussion of these topics.

6

4 Specifications

For the envisaged multi-standard

modulator the following specifications shall bemet:

GSM/EDGE Bandwidth%

Dynamic range Cellular OSR 130

UMTS Bandwidth%

Dynamic range OSR 16

IEEE802.11a/b/g Bandwidth%

Dynamic range % WLAN OSR 12

IEEE802.11n Bandwidth

Dynamic range OSR 8

Table 1: Specifications.

5 Task

5.1 Preparation

1. Gain an overview on

modulators [2–4].

2. Study the following topics required for the Thesis:

• Study

converter topologies suited for the implementation in a deep-submicron technology [5].

• Study previous implementations of

converters for wireless receivers [6].

• Study the technology data [7].

• Study the design of the analog circuit blocks [8–12].

3. Plan your Thesis. Discuss your planning with the assistant(s).

5.2 Architectural Design

1. Investigate different

ADC topologies, while limiting you study to single-loop(multi-bit) topologies. Evaluate their performance and choose the one, whichfulfills the requirements best. Consider re-configurability of the converter toachieve optimum performance for all covered standards (SQNR at least 10dBlower than thermal noise).

7

2. Implement the chosen

ADC as a Simulink© model for high-level simula-tions. Conceptionaly develop the circuit implementation of the chosen topologyon paper.

3. Perform coefficient scaling keeping in mind the low supply voltage of the usedtechnology.

4. Also simulate the expected linearity of the DAC and investigate dynamic elementmatching (DEM) algorithms for linearization of your DAC.

5. Carry out a systematic analysis for the specifications for the individual buildingblocks (OTA bandwidth, comparator offsets etc.)

6. Prepare a short presentation describing your topology and summarizing the re-quirements on the circuit blocks before you move on to the circuit implementa-tion.

5.3 Circuit Design

1. Implement your modulator as a behavioral model in Cadence.

2. Design the amplifiers.

3. Finish the circuit level implementation of the integrators.

4. Design the comparator circuits.

5. Implement the DEM block (digital parts can be implemented as behavioral mod-els).

6. Design the remaining circuits (clock generation, ev.bootstrap switches, bias cir-cuits, reference buffer etc.).

7. (Optional) Draw the layout.

8

5.4 Administrative Issues

1. Diploma Thesis report: discuss the Pros and Cons of different design variantsin your report. Explain why you have chosen a specific variant and provideyour calculations, not just list what you have done. This makes your Thesisattractive. Plan enough time for writing the report.

2. The work carried out has to be presented as talk in the Diploma Thesis Collo-quium of the Institute at the end of the semester.

You will be assigned a desk and a Sun workstation for carrying out the work (roomETZ K61). You will receive the corresponding login and password for your computeraccount from the responsible assistant when starting your work.

6 Meetings

Regular meetings with your assistants to evaluate the status of work and to plan thenext steps are a necessary precondition for successful completion of your DiplomaThesis.

Zurich, 30. March 2007 Prof. Dr. Q. Huang

The thesis will not be accepted without returning of the keys!

9

References

[1] G. C. T. James C. Candy, Ed., Oversampling Delta-Sigma Data Converters. IEEEPress, 1992.

[2] S. Norsworthy, R. Schreier, and G. Temes, Delta-Sigma Converters - Theory, De-sign, and Simulation. IEEE Press, 1996.

[3] P. Balmelli, Broadband Sigma-Delta A/D Converters. PhD thesis, ETHZ, 2004.

[4] R. Schreier, G.C. Temes, Ed., Understanding Delta-Sigma Data Converters. WileyIEEE-Press, first ed., 2004.

[5] J. Silva, J.Steensgaard, and G.C. Temes, “Wideband low-distortion delta-sigmaadc topology,” Electronics Letters, pp. 737–738, Dezember 2001.

[6] T.Christen, T.Burger, and Q.Huang, “A 2% CMOS EDGE/UMTS/WLAN Tri-

Mode

ADC with -92dB THD,” in Digest of Technical Papers, IEEE InternationalSolid-State Circuits Conference, ISCC, Februar 2007.

[7] ST Microelectronics, CMOS065 Design Rules Manual, June 2007.

[8] T. Burger, Optimal Design of Operational Tranconductance Amplifiers with Appli-cation for Low Power

Modulators. PhD thesis, ETHZ, 2002.

[9] Q. Huang, “Analog integrated circuit design.” Lecture notes, Apr. 1994.

[10] P. Gray and R. Meyer, Analysis and Design of Analog Integrated Circuits. JohnWiley & Sons, New York, third ed., 1993.

[11] B. Razavi, Design of Analog CMOS Integrated Circuits. McGraw-Hill, 2001.

[12] Philip E.Allen, and Douglas R.Holberg, CMOS Analog Circuit Design. OxfordUniversity Press, 2004.

10

1Introduction

This master thesis deals with an analog-to-digital converter (ADC) for cellular and wirelessstandards. In particular, it deals with a multi-standard wideband Σ∆-modulator for the cel-lular standards GSM-EDGE and UMTS and for the wireless standards IEEE 802.11a/b/gas well as the draft n1. A typical receiver system with such an ADC is shown in fig. 1.1.The modulated signal from a base station is received by the antenna and bandpass filtered.After that, the filtered signal is amplified by a low-noise amplifier (LNA). Then, it is de-modulated and low-pass filtered. The ADC, that follows next, consists of a Σ∆-converterthat transforms the analog input signal to its digital counterpart. Every Σ∆-converterconsists of a Σ∆-modulator and a decimation filter.

Σ∆-

Modulator

Decimation

Filter

Σ∆-ADCLNA

on-chipon-board

Figure 1.1: Simplified scheme of a receiver system

The specialty of the ADC in this master thesis is its reconfigurability. Many ADCsimplemented so far, have only supported a single standard. But todays communicationelectronics ask for the support of multiple standards. Instead of designing dedicated ADCsfor each standard, a single ADC should support all these multiple standards. So the re-ceiver system may be invoked for example to operate for a GSM call and in another momentfor a data connection over WLAN. But there is also another reason for making the ADCreconfigurable: Todays high data traffic, with its predefined frequency bands, asks for an

1The wireless standards are abbreviated as WLAN a/b/g/n in the following.

1

2 CHAPTER 1. INTRODUCTION

efficient bandwidth usage. Only the bandwidth that is absolutely needed should be used.Therefore, the required bandwidth should be negotiated with the required resolution andhence an ADC should be able to adapt the bandwidth while delivering a certain perfor-mance. For all these reasons, the ADC is a key element for reconfigurable receiver systems.

In this chapter, some basic concepts of ADCs are outlined and the terminology used inthis thesis will be introduced. Then, a short introduction to Σ∆-converters is given andtheir importance in the field of communication electronics is presented.

1.1 ADC Basics 3

1.1 ADC Basics

An ADC is a nonlinear system which assigns a digital output to the analog input. Thedifference between the input and the output is called quantization error E(z) and is ameasure for the precision of the conversion. In general, the input can be multiplied with aconstant k during the conversion. So, the output V (z) of the quantizer can be written asa function of the input Y (z):

V (z) = k · Y (z) + E(z) (1.1)

A N -bit quantizer with 2N equally distributed levels has a least significant bit of LSB =(Vmax−Vmin)/2N = 2·Amax/2N , with a maximum sine-amplitude of Amax. The quantizationerror therefore lies in a range of −LSB/2 ≤ E(z) ≤ LSB/2. Although the quantizationerror is deterministic, it is modeled as additive white noise to the output. This model yieldsaccurate results especially for arbitrary input signals. Its limitations are listed in [RS05].

In this context, the quantization error is referred to as quantization noise. The signal toquantization noise ratio (SQNR) can in this case be calculated with the signal power of asine-wave with amplitude A, Psin = A2/2, and the corresponding quantization noise power,Pn = LSB2/12:

SQNR = 10 · log

A2

2“2A

2N

”2

12

(1.2)

= 6.02 ·N + 1.76 (1.3)

The ideal quantizer supplies the digital output without delay and allows to measure theerror directly by subtracting the input from the output signal. It is therefore used as areference for the Σ∆-converter.

The simplest ADC-implementation is a flash-converter, which produces its reference val-ues e.g. using a ladder of equally dimensioned resistors and for each reference value employsa comparator which indicates whether the input value lies above or below the reference.Building a flash-converter is not very efficient in hardware, because the number of com-parator grows linearly with the number of reference values. This growth is unthinkable forADCs with 14 or more bits. Different approaches exist to overcome this problem, one ofwhich is the Σ∆-principle.

1.1.1 Introduction to Σ∆-Converters

One possibility to increase the resolution is to give up the input-output-relation and togather additional information from the input signal by oversampling. The oversamplingratio (OSR) is defined as the fraction of the sampling frequency fs and twice the signalbandwidth fb:

OSR =fs

2fb(1.4)

In other words, the quantization noise, which is spread over the whole spectrum up tofs/2, only has a small portion in the signal-band. In [RS05], the following relation is proved:

SQNR =9A2OSR3

2π2(1.5)

4 1.1 ADC Basics

The basic idea of the Σ∆-converter is to filter the outcoming signal in order to movethe quantization noise out of the signal-band and thereby increase the signal-to-noise ratio(SNR) further. When the still oversampled output sequence is low-pass filtered and down-sampled again by a decimation filter, a value can be attained which has a higher resolutionthan the internal quantizer.

To measure the performance of the Σ∆-converter, the effective number of bits (ENOB)is calculated from the SQNR with eq. 1.3, i.e. the equivalent number of bits of an idealquantizer with the identical SQNR. The quantizer inside the Σ∆-modulator has a greatimpact on the performance of the converter. According to eq. 1.3, it increases the SQNRby 6dB with every bit.

As every other feedback-system, the Σ∆-modulator has stability issues. Since the quan-tization noise requires a part of the input-range, this part can not be used by the signal,too, without overloading the system. In order to get a high SNR, the input signal shouldbe allowed to have a high amplitude. The input stable-range (ISR) indicates the maxi-mally allowable input amplitude for a stable operation and is a performance measure forthe converter.

1.1.2 Structure of Σ∆-Converters

L0

L1

U(z)

V (z)Y (z)

L0

L1

U(z)

V (z)Y (z)

⇐⇒ k

E(z)

Figure 1.2: General structure of a Σ∆-converter

The modulator itself has the structure of a feedback-loop as illustrated in fig. 1.2. Giventhe quantization process of the Nyquist-converter from eq. 1.1 with unity-gain k = 1, theoutput of the loop-filter can be written as:

Y (z) = V (z)− E(z) = L0(z)U(z) + L1(z)V (z) (1.6)

Eq. 1.6 can be separated into a signal transfer function (STF) which is the transferfunction from the system input to the output, and a noise transfer function (NTF), whichis the transfer function from the quantizer (as the quantization noise source) to the output:

V (z) = STF(z)U(z) + NTF(z)E(z) (1.7)

STF(z) =L0(z)

1− L1(z)(1.8)

NTF(z) =1

1− L1(z)(1.9)

While it is desirable that the STF has unity gain in the signal band, which means thatthe signal is not distorted, the NTF should move the noise power out of the signal band.

1.1.3 Importance of Σ∆-Converters in Todays Electronics 5

This high-pass behavior of the NTF is called noise-shaping and can be implemented withan integrator in the simplest case. By connecting n integrators in series, the noise-shapingcan even be enhanced. The NTF for such a structure would be:

NTF(z) =1

(1− z−1)n(1.10)

Instead of using plain integrators, a more sophisticated circuit with a more generaltransfer-function can be used to improve the stability and the noise-shaping of the system.The complexity of the chosen NTF is only limited by hardware-implementation issues. Inthis thesis, such a Σ∆-modulator with a generalized transfer-function was first optimizedwith mathematical models and then built in a state-of-the-art 65nm CMOS process.

1.1.3 Importance of Σ∆-Converters in Todays Electronics

When the first commercial Σ∆-converter had been placed on the market in the late 1980s,further Σ∆-converters soon followed that began competing with state-of-the-art converterarchitectures. Since the mid 1990s, Σ∆-converters started replacing other converter archi-tectures in many fields of applications, especially in audio. Today, they are well situatedin the field of audio, communication, sensor technology and alike [Dev].

Σ∆-converters are so attractive for multi-standard applications, because they offer thepossibility to trade bandwidth for resolution. By changing the OSR, it is basically possibleto achieve a very high resolution in a narrow signal band, or to attend a high bandwidthwith a smaller resolution.

6 1.1 ADC Basics

z−1

2System Design

2.1 Transfer Function

2.1.1 Topologies

The topology of the loop architecture contains elements that allow to manipulate the STFand the NTF. Figs. 2.1-2.4 show the block diagrams of the possibilities to interconnect theintegrator stages. The effects on the transfer-functions are also annotated. The differentpossibilities can of course be combined. The equations presented do not take into accountthat loops can be formed which may significantly change the transfer function. Hence,a detailed analysis of the eventual topology is required to get the final transfer-function.The following considerations should merely serve as a starting point to evaluate differentapproaches of topology-transformations.

1

1−z−1

1

1−z−1

1

1−z−1U(z) Y (z)

V (z)

m

STF(z) =1

(z − 1)n + 1

NTF(z) =(z − 1)n

(z − 1)n + 1

Figure 2.1: Chain of n integrators

1

1−z−1

1

1−z−1

1

1−z−1U(z) Y (z)

V (z)

m

b

STF(z) =b(z − 1)m + 1

(z − 1)n + 1

NTF(z) =(z − 1)n

(z − 1)n + 1

Figure 2.2: Input feed-forward path over m integrators

7

8 2.1 Transfer Function

1

1−z−1

1

1−z−1

1

1−z−1U(z) Y (z)

V (z)

g

k

STF(z) =1

−g(z − 1)k + (z − 1)n + 1

NTF(z) =(z − 1)n − g(z − 1)k

−g(z − 1)k + (z − 1)n + 1

Figure 2.3: Local Resonator over k integrators

1

1−z−1

1

1−z−1

1

1−z−1U(z)

Y (z)

V (z)

a

m

STF(z) =a(z − 1)m + 1

a(z − 1)m + (z − 1)n + 1

NTF(z) =(z − 1)n

a(z − 1)m + (z − 1)n + 1

Figure 2.4: Integrator feed-forward over m integrators

A non unity-gain STF can filter the input-signal outside the signal-band. But the STFthen amplifies a part of the signal near the corner frequency. This can amplify adjacentchannel blockers, which should be prevented. To achieve unity-gain for the STF, an inputfeed-forward path is added. If no quantization error were present, the input of the loopwould always be zero. A detailed analysis shows that a unity-gain feed-forward path fromthe input to the output, i.e. setting m = n and b = 1 in fig. 2.2, yields the desired effect,even if combined with other paths.

To optimize the noise shaping, the poles of the NTF should be adjustable. This can beachieved by using integrator feed-forward signals.

Placing a local resonator moves the zero of the NTF, which cancels the noise at a certainfrequency and therefore attenuates the noise power in the signal band. For frequencies belowthe zero, the high-pass attenuation of the NFT is reduced by the order of the resonator.This is acceptable, if the thermal noise dominates in this region.

The selection of the implemented architecture is based on the presented topology discus-sion, simulation results and results from the prior semester thesis [Sen06] and [Bla06]. A4th order Σ∆-structure is implemented with integrator feed-forward, one resonator and a3-bit quantizer. It is shown in fig. 2.5.

The choice of the filter coefficients determines the pole-zero-placement of the system. Bychanging the poles and zeros of the modulator, both the noise shaping performance in thesignal band and the stability of the loop are altered. To get a better understanding of themodulator-system, the effects of different pole-zero-placements are illustrated in the nextsection.

2.1.2 Effects of Pole-Zero-Placements

In the z-domain, the unit circle corresponds to the imaginary axis of the s-plane, the pointsinside the unit circle correspond to the left half-plane and the points outside the unit circleto the right half-plane of the s-plane. A stable system thus has all its zeros strictly withinthe unit circle.

An ideal high-pass filter will be taken as the reference configuration. It has all polesat z = 0 to assert maximum stability, and maximum DC attenuation which is achieved

2.1.2 Effects of Pole-Zero-Placements 9

3-bit Quantizer

V (z)

a3a2

+ E(z)

+

g

z−1

1−z−1

1

1−z−1

z−1

1−z−1

z−1

1−z−1

+ + +

a4a1

+ z−1

b4 b5b3b2b1

U(z)

−

−

Y (z)

Figure 2.5: Implemented architecture

by placing the zeros at z = 1. The resulting system zn/(z − 1)n is compared to otherconfigurations with different pole-zero locations in fig. 2.6.

The quantization noise of the system is shown in fig. 2.6(a) as the black line in thefrequency domain. When filtered by the ideal high-pass, the noise is shaped, as seen in theblue curve. The noise power in the signal band is attenuated, which increases the SQNR.On the other side, the noise power is amplified outside the signal band, which reduces theISR. The optimal solution provides the highest possible DR for the highest possible ISR.

In fig. 2.6(b), the poles of the system are moved along the real axis. By moving thepoles towards the zeros at z = 1, the system behaves more like a third-order system, whichmeans less attenuation in the signal band but a more stable system. On the other hand,for higher DRs, the poles have to be moved towards z = −1.

When moving the poles on the imaginary axis, the noise is attenuated everywhere butin the region of the resonance frequency. The consequence is, that the DR is increasedwithout reducing the input stability as much as in the case, when the poles are moved onthe real axis. This effect is shown in fig. 2.6(c).

The movement of the zeros along the unit-circle cause the noise to be canceled outcompletely at the zero-frequency as shown in fig. 2.6(d). The stability is not negativelyaffected in this case, but the increase of the DR is substantial. The placement of the zeros,also called the notch of the transfer function, is the main means to provide reconfigurabilityof the system. For every standard, a notch is calculated, that lies just below the signal-band.With this simple measure, the DR can be increased by many dB.

10 2.1 Transfer Function

log (ω)

‖N

TF‖

ωBW

Im

Re

ejω

Input Stability [%FS]

100%0%

[dB]

(a) Reference system: Chain of integrators

log (ω)

‖N

TF‖

ωBW

Im

Re

ejω

Input Stability [%FS]

100%0%

[dB]

(b) Moving poles along the real axis

log (ω)

‖N

TF‖

ωBW

Im

Re

ejω

Input Stability [%FS]

100%0%

[dB]

(c) Moving poles along the imaginary axis

log (ω)

‖N

TF‖

ωBW

Im

Re

ejω

Input Stability [%FS]

100%0%

[dB]

(d) Moving zeros along the unit circle

Figure 2.6: Effects of the pole-zero-placement

2.1.3 Optimization Methods

The goal is to optimize the transfer function in order to achieve the highest possible DRfor a defined input-range. Three different approaches were simultaneously evaluated duringthis thesis to calculate good pole-zero-configurations.

Brute-Force Search

The computer is given a coarse range inside the unit-circle of the z-domain, where it canplace the pole-pairs. Then, for every possible combination of two pole-pairs, the systemis simulated and the DR is determined. Based on the best combinations, the algorithmdetermines finer ranges, where the next search is started and iterates.

This method is computationally very intense. For higher order systems, the complexitygrows exponentially, and also, if the implicit assumption is voided, that poles only comeas complex conjugated pairs1. On the other hand, after a few iterations, regions with highDRs can be pointed out, which can be used by other algorithms as starting configurations.

Simulation-Based Method of Gradients

Given a stable pole configuration, the system is simulated for configurations in the vicinityand the DR is evaluated. With these results, an algorithm based on the method of gradientsis executed to find the configuration with the highest DR.

1The system is still real, if two poles are not complex conjugates but real instead.

2.2 System Optimization 11

One problem with this approach is, that the measured DR is not a smooth function ofthe pole-placement. Therefore, this method is very unreliable for small steps. A possibleimprovement could be to compute the mean value of several measurements to get a smootherfunction.

A common problem of both methods presented so far is, that the stability of the system isonly evaluated for a single amplitude. Therefore, it is not possible to predict how the systembehaves for different input amplitudes. Simulating the system for various amplitudes wouldfurther increase the required number of simulations.

Also, both methods have to be tested for sensitivity to different parameters. Often,a system with a very high DR is on the verge to instability. A series of Monte Carlosimulations is therefore compulsory for a configuration found by these algorithms.

Analytic Pole Calculation

An analytic approach was developed by John Kenney and Richard Carley in [JGK93].They basically use a butterworth high-pass filter as starting configuration and optimize thein-band noise power while ensuring a certain input stable-range for the Σ∆-converter. Incontrast to the method described above, the DR calculated from the in-band noise poweris a smooth function of the poles and therefore, the method of conjugated gradients canbe applied well and yields optimal results for the given boundary conditions. Also, thespecified ISR of the system can be mathematically guaranteed with this method.

Schreier and Temes used the algorithm in their closed-loop analysis of noise-shapers(CLANS) in [RS05].

The optimization used in this thesis makes use of the formulæ presented in [JGK93] tofind a measure for the stability of the modulator and to calculate the noise power in thesignal band. The main difference is, that the cost function in this thesis optimizes both thein-band noise power and the stable input-range simultaneously. When a solution is foundwith the algorithm, the designer can simulate it and then adjust the parameters in orderto improve either the input-stability or the dynamic range. This allows a flexible search forthe best trade-off. The additional time-investment is rather small compared to the wholedesign project of a Σ∆-converter but has a large impact on the system performance.

The optimization process will first be explained for a single-standard converter. Then,the applied methods are extended to optimize multi-standard systems as well.

2.2 System Optimization

2.2.1 System Configurations

The system configuration describes the system uniquely. In the implemented system, thiscan either be a set of poles p and zeros z or a set of filter-coefficients a, b and g. Accordingto the formulæ in app. C, one set can be converted into the other and vice versa.

The optimal configuration achieves the highest possible DR with an acceptable ISR.

12 2.2 System Optimization

2.2.2 Goal Functions

The optimization goals are the ISR and the DR. They determine the quality of a configu-ration and should both be as high as possible. The goal functions have to be calculated asa function of a given configuration.

Dynamic Range

Under the assumption that the quantization noise is white, which is synonymous to havinga constant power spectral density in the frequency domain, the filtered noise power spectraldensity can be calculated by multiplying the transfer function with the noise power N0. Theinband noise is then calculated by integrating the transfer function along the signal-band:

Pn,ib = N0

∫ fb

0|NTF(jω)|2 · dω (2.1)

In order to compare two configurations, they are assumed to have the same input powerPs. The DR can therefore easily be calculated according to its definition in eq. B.6:

DR = 10 log(

Ps

Pn,ib

)(2.2)

Fig. 2.7 shows the calculated in-band noise of the entire system for the choice of thesecond pole pair, if the first pole pair is fixed to p1,2 = 0.6875.

−1

−0.5

0

0.5

1−1

−0.8−0.6

−0.4−0.2

00.2

0.40.6

0.81

0

0.001

0.002

0.003

0.004

0.005

0.006

0.007

0.008

0.009

0.01

imaginary axis

Inband−noise−Plot

real axis

Inba

nd−

nois

e

0

0.02

0.04

0.06

0.08

0.1

Figure 2.7: In-band noise of the system as a function of the 2nd pole pair’s position

Input Stable Range

For the ISR, a formula is derived in [RS05] which provides a sufficient, but not necessarycondition for the input signal to guarantee stability. The derivation states that in order to

2.2.3 Cost Function 13

guarantee stability, the quantizer must never be overdriven. When analyzing the outputsignal Y (z) in the time domain, eq. 1.7 transforms to:

y[n] = stf[n] ∗ u[n] + ntf[n] ∗ e[n]− e[n] (2.3)

Since the STF does not distort the input signal, it is only allowed to contribute a k-folddelay. Writing out the convolution and normalizing the input amplitude to 1, the equationcan be rewritten as:

y[n] = u[n− k] +∞∑i=1

h[i]e[n− i] (2.4)

To keep the quantizer out of saturation, |y[n]| ≤ 1 has to hold at all times. Therefore,to create the worst case, the input and the error signal have to contribute maximally tothe output. The maximum quantization error is 1/2 LSB or 1/(2∆). This results in thefollowing condition:

umax = maxn|u[n]| ≤ 1− 1

2∆(||h||1 − 1) (2.5)

||h||1 =∞∑

n=0

|h[n]| (2.6)

Being sufficient but not necessary, this formula yields very pessimistic results. Thedifference between predicted and actual ISR is also nonlinear and shows a large gap in thearea of interest around 0.5FS-0.8FS. A more realistic worst-case assumption can be set upby calculating coefficients for fitting the lowest measured values onto a polynomial curveas a function of the predicted values. Fig. 2.8 shows a plot of predicted ISR-values and themeasured input stable ranges for a 4th order system with a 3-bit quantizer.

A third-order polynomial suffices to improve the prediction for inputs in the criticalregion where stability should be guaranteed. The final formula used for the ISR-predictionis accordingly:

ISR = α3 · u3max + α2 · u2

max + α1 · umax + α0 (2.7)

The coefficients for the implemented architecture are listed in tab. 2.1.

Table 2.1: Coefficients for ISR polynomial fittingα3 α2 α1 α0

11 -12.5 5.2 0

Fig. 2.9 shows the system stability of the entire system for the choice of the second polepair, if the first pole pair is fixed to p1,2 = 0.6875.

2.2.3 Cost Function

The cost function allows the comparison of different configurations with one scalar measure.To combine the ISR and the DR from eqs. 2.2 and 2.7, the goal functions have to bereshaped, scaled and weighted.

14 2.2 System Optimization

0 0.2 0.4 0.6 0.8 10

0.2

0.4

0.6

0.8

1

1.2

Predicted ISR

Mea

sure

d IS

R

Predicted vs. Measured Input Stable Range

Measured points

Fitted curve

Figure 2.8: Predicted vs. mea-sured ISR

−1

−0.5

0

0.5

1−1

−0.8−0.6

−0.4−0.2

00.2

0.40.6

0.81

0

0.5

1

1.5

imaginary axis

Stable input range−Plot

real axis

S

tabl

e in

put r

ange

0

0.2

0.4

0.6

0.8

1

1.2

Figure 2.9: Input stable range of the system as a func-tion of the 2nd pole pair’s position

Function Reshaping

Ideally, the cost-contribution of the components should be small and the gradient should beflat if they lie in the required range. It should have a steep gradient if they start to diverge.To be comparable, the functions need to be reshaped. To achieve the requirements, anexponential behavior is chosen.

Function Scaling

To scale the values properly, both goal-functions are transformed into linear functions, andtheir coefficients are scaled in order that the functions have the value T = 1 for the targetvalue, and C = 2 for the critical value2. For the DR, the following equations are solved forthe scaling-factors aDR and bDR (the calculation for the ISR is analogical):

T = aDR ·DRtar + bDR (2.8)C = aDR ·DRcrit + bDR (2.9)

The two goal functions can now be expressed as:

fDR = eaDRDR+bDR (2.10)fISR = eaISRISR+bISR (2.11)

Function Weighting

The DR- and the ISR-component are each multiplied with a parameter, γDR and γISR

respectively, and added to build the cost-function that looks as shown in fig. 2.10.2Since the transformed functions are linear, T and C can be chosen freely.

2.2.4 System Optimization Problem 15

−1

−0.5

0

0.5

1−1

−0.8−0.6

−0.4−0.2

00.2

0.40.6

0.81

0

1

2

3

4

5

6

7

8

imaginary axis

Cost−value−Plot

real axis

Cos

t−va

lue

3

4

5

6

7

8

Figure 2.10: Cost-function of the system as a function of the 2nd pole pair’s position

The cost function can eventually be written as:

fcost = γDR · eaDRDR+bDR + γISR · eaISRISR+bISR (2.12)

2.2.4 System Optimization Problem

By choosing the values DRtar and DRcrit, the designer can influence the optimization.Setting the target and critical values close to each other results in a very sharp transitionbetween acceptable and unacceptable performance, but carrying it too far will eventuallycrash the algorithm’s capability of finding a solution.

The algorithm used is a method of gradients applied on the cost-function. The MATLABoptimization algorithm FMINCON was used to solve the problem numerically. The problemis entered as:

Given p,z or a, b, g (2.13)minimize fcost (2.14)

under the condition 0 ≤ |pi| < 1, |zi| = 1. (2.15)

The boundary conditions claim, that the system be stable and have the zeros on theunit circle, which corresponds to having them at real frequencies, which maximizes theattenuation.

When a solution is found, the simulation based approaches in sec. 2.1.3 can be applied tosearch the best configuration within a small range and make use of simulated data whichis not subject to the simplifying assumptions of the described model for the calculations.

16 2.3 Multi-Standard Compliance

2.3 Multi-Standard Compliance

The presented method for optimizing Σ∆-modulators allows designing a system by pole-zero-optimization and therefore offers a certain amount of insight in the system propertiesbefore actually running a simulation. When implementing the architecture in hardware,the pole-zero-configuration is implicitly given by the choice of the gain parameters for thefeed-forward paths, a and b, and the resonator g. These parameters in turn are realized ina switched-capacitor circuit with ratios of capacitances. The filter coefficients depend onthe exact matching of these capacitors.

When designing a multi-standard converter, the modulator has in fact to be optimizedfor many standards, which would result in many capacitance ratios. This leaves the choiceto the designer to:

. use variable capacitors that engage other capacitors in series/parallel,

. use one configuration, that complies best with all standards or

. use a combination of the two methods.

Variable capacitors decrease the precision of the pole-zero-placement, because the switchescontribute additional parasitic capacitance to the capacitor which leads to an uncertainty.Also, the layout is more complicated with many variable capacitors. They are a viablesolution, if the sensitivity of the system to the parameter is negligible. Unfortunately, thesystem is very sensitive to the feed-forward gains. Therefore, a vector a has to be found,which optimally satisfies all standards.

On the other hand, the system is very tolerant for variations in the input feed-forwardgain b, at least in the signal-band. The resonator g can be implemented with variablecapacitors, because it only slightly changes the attenuation performance.

This leaves the problem to optimize the vector a for the four standards. The idea is,that the feed-forward filter coefficients only affect the system poles. In this case, the polescan be calculated in order to fulfill the worst-case required DR (WLAN n), and then, thenotch can be moved to improve the attenuation for the other standards. Unfortunately,moving the notch also moves the poles of the system, as it is shown in fig. 2.11.

In fig. 2.11(a), the system was optimized for WLAN n. Now, when the notch is movedtowards zero for GSM-EDGE, the poles go towards the unit circle and lead to an unstablesystem. In the case where the system is optimized for GSM-EDGE and the poles are movedalong the unit circle to fulfill WLAN n, the required DR is not achieved.

One possibility to solve this problem is to change the optimization algorithm not to usepole-zero-configurations, but to use the vector a directly as a configuration. In fig. 2.11(b),a weighting of the different standards’ performance is necessary to be able to control whichstandard is optimized best. In this thesis, since only the attenuation of the WLAN n draftwas hard to achieve, the multi-standard optimization was done by optimizing the systemfor the different standards individually and then moving the roots from WLAN n towardsWLAN a/b/g, while all DRs were fulfilled and the system remained stable. This case isshown in fig. 2.11(c).

2.4 Hardware-Related Architecture-Transformations 17

−1 −0.5 0 0.5 1−1

−0.8

−0.6

−0.4

−0.2

0

0.2

0.4

0.6

0.8

1

Pole−Zero Map

Real Axis

Imag

inar

y A

xis

WLAN nWLAN a/b/gUMTSGSM−EDGE

(a) Pole-movement due to changing of the resonatorparameter g in the system optimized for WLAN n

−1 −0.5 0 0.5 1−1

−0.8

−0.6

−0.4

−0.2

0

0.2

0.4

0.6

0.8

1

Pole−Zero Map

Real Axis

Imag

inar

y A

xis

WLAN nWLAN a/b/gUMTSGSM−EDGE

(b) Pole-movement due to changing of the resonatorparameter g in the system optimized for GSM

−1 −0.5 0 0.5 1−1

−0.8

−0.6

−0.4

−0.2

0

0.2

0.4

0.6

0.8

1

Pole−Zero Map

Real Axis

Imag

inar

y A

xis

WLAN nWLAN a/b/gUMTSGSM−EDGE

(c) Pole-movement due to changing of the resonatorparameter g in the implemented system

Figure 2.11: Effects of the pole-zero-placement

2.4 Hardware-Related Architecture-Transformations

2.4.1 Limited Amplifier-Swing Compensation

A telescopic cascode-amplifier has been chosen to implement the integrators in the Σ∆-modulator because it is very power-efficient. The drawback is, that it has only a limitedswing of Vdd/3

To determine the system’s preliminary output-swing, the system is simulated with a sinewave. The integrator input-gains are then unity at first. The histogram of each amplifier’soutput is taken. The histograms in fig. 2.12 show how some swings exceed the possiblerange.

For the outputs to be bounded in a range of Vdd/3, they have to be scaled by certainfactors s. The s which scales the outputs correctly are noted inside the red circles andbecome the new input gains. The scaling-vector s can be either determined by visualinspection or statistical analysis. An optimized scaling factor maximizes the output swing,while not clipping too many output-values. Since the distribution of the values is not

18 2.4 Hardware-Related Architecture-Transformations

7 47 3

z−

1

1−

z−

1+

z−

11

1−

z−

1

G

2 5

z−

1

1−

z−

1

3 4

+z−

1

1−

z−

1

7 8

+

1 4

−

X(z

)

4

−

Y(z

)

7 10 7 40

1 11

1

1

1 6

4 6 4 6 4 6

Figure 2.12: Swing scaling by inspection of the output-histograms

2.4.2 Fractions of Small Integers for Path Gains 19

necessarily the same for all amplifiers, the use of statistical analysis is often less efficient.In order not to affect the pole-zero-configuration, the amplifier-scalings have to be com-

pensated for before the end of the modulator-loop. Fig. 2.13 shows the SFG-rule for com-pensating the swing-scaling correctly.

1

1−z−1

a

1

1−z−1

a

s

1

s

s

⇐⇒

Figure 2.13: SFG-rule for swing-scaling compensation

2.4.2 Fractions of Small Integers for Path Gains

All path gains, except for the quantizer gain s5, are realized in hardware by capacitor ratios.Although virtually any capacitance can be designed in the EDA-tools, when it comes tocapacitance ratios, the capacitors are layouted in an interleaved structure of equal unitcapacitors, as sketched in fig. 2.14, for good matching.

C1 C2

Dummy

Figure 2.14: Matching of two capacitors C1 and C2

This requires that path gains are fractions of preferably small integers. The problemin finding suitable fractions is that certain paths share capacitors. The denominators ofthese paths have to be the same, which raises the question for the optimal numerators anddenominators in the system. In this thesis, an algorithm was developed, that calculates fora set K of allowable denominators an optimized set of numerators for all n path gains aand swing-scaling factors s with respect to common capacitors. The input feed-forward andresonator capacitors are not considered, because the system is less sensitive to variationsin them.

The algorithm works for all signal flow graphs with integrator feed-forward paths andscaled amplifier inputs. The scaling factors have no common denominators with other pathsand can be chosen freely, but they influence the calculation of the other paths. They arerepresented by si = snum,i/sden,i. The effective gain of the feed-forward paths compensatesthe input scaling, so for a1, the effective gain is given by g1 = a1/s1, g2 = a2/(s1s2) andso on. If the scaling-factor must not be optimized by the algorithm, the corresponding flagfc,i can be set to zero.

The algorithm is presented in pseudo-code in alg. 1.

20 2.4 Hardware-Related Architecture-Transformations

Algorithm 1 Calculate fractions of small integers for path gainsinput: a, s, sc and Koutput: A, S

Ek1 ←∞ initialize k1-errorIterate through all possible denominators and determine the resulting error. Choose the commondenominator that causes the smallest relative deviation of a

for all denominators k1 ∈K dost ← s use a local copy of s for each k1

Iterate through all n path gains. Find the fittest denominator for the given denominator k2.for i = 1 to n do

gi ← aiiQ

j=1st,j

calculate the effective path gain after swing-scaling

gnum,i ← round(gi · k1)gden,i ← k1

Optimize the scale-factors, if allowed by the designer.if fc,i = 1 then

srat,i ← ai

gnum,igden,i

·i−1Qj=1

st,j

calculate the resulting scaling-factor for the given gi

Ek2 ←∞ initialize k2-errorIterate through all denominators, independently from k1 and find the optimum scale-factors.for all denominators k2 ∈K do

snum,i ← round(sfrac,i · k2)sden,i ← k2

if∣∣∣(srat,i − snum,i

sden,i

)∣∣∣ < Ek2 then

st,i ← snum,i

sden,i

Ek2 ←∣∣∣(srat,i − snum,i

sden,i

)∣∣∣end if

end forend if

end foraeff,i ←

gnum,i

gden,i·

n∏i=1

si for all i = 1 to n

ifn∑

i=1

∣∣∣aeff,i−ai

ai

∣∣∣ < Ek2 then

Ai ← gnum,i

gden,isave capacitance ratios for all i = 1 to n

Si ← st,i save capacitance ratios for all i = 1 to n

Ek2 ←n∑

i=1

∣∣∣aeff,i−aiai

∣∣∣end if

end forreturn A, S

2.5 Chosen Architecture 21

2.5 Chosen Architecture

2.5.1 Signal Flow Graph

The SFG of the system with the gain-factors calculated from the system optimization isshown in fig. 2.15.

Y (z)

a3a2

+

g

z−1

1−z−1

11−z−1

z−1

1−z−1

z−1

1−z−1+ +

a4a1

z−1

X(z)

−

−

a1 = 2.198

a2 = 1.762

a3 = 0.695

a4 = 0.180

GSM-EDGE g = 0UMTS g = 0.028WLAN a/b/g g = 0.049WLAN n g = 0.112

Figure 2.15: Optimal SFG

2.5.2 Scaled Signal Flow Graph

The SFG including the calculated swing-scaling, with optimized gain-factors that are frac-tions of small integers, is shown in fig. 2.16.

4

6

1

6z−1

1−z−1+z

−111−z−1

G

2

5z−1

1−z−1

3

4+

z−1

1−z−1

7

8+

1

4

−

X(z)

4

−

Y (z)

4

6

4

6

GSM-EDGE G = 0UMTS G = 0.093WLAN a/b/g G = 0.163WLAN n G = 0.373

Figure 2.16: Implementable SFG

22 2.5 Chosen Architecture

2.5.3 Results

In fig. 2.17, the ISR is determined by reading out the highest stable amplitude value. Thespectrum of the output signal for all standards is shown in fig. 2.18 and 2.19.

−200 −180 −160 −140 −120 −100 −80 −60 −40 −20 00

20

40

60

80

100

120

140GSM−EDGE

Amplitude [dBFS]

SN

DR

, DR

[dB

]

DRSNDR

−200 −180 −160 −140 −120 −100 −80 −60 −40 −20 0−20

0

20

40

60

80

100UMTS

Amplitude [dBFS]

SN

DR

, DR

[dB

]

DRSNDR

−200 −180 −160 −140 −120 −100 −80 −60 −40 −20 00

10

20

30

40

50

60

70

80

90WLAN IEEE 802.11a/b/g

Amplitude [dBFS]

SN

DR

, DR

[dB

]

DRSNDR

−200 −180 −160 −140 −120 −100 −80 −60 −40 −20 0−20

−10

0

10

20

30

40

50

60

70WLAN IEEE 802.11n

Amplitude [dBFS]

SN

DR

, DR

[dB

]

DRSNDR

Figure 2.17: Input range stability

The important results for each standard are summarized in tab. 2.2. Note that therequired DR for each standard includes the thermal noise while the measured DR from thesimulation does not.

Table 2.2: ResultsStandard DR [dB] requ. DR [dB] ISR [dBFS] ISR [%]GSM-EDGE 117.74 88 -1.59 83.3UMTS 92.50 79 -1.21 87.0WLAN a/b/g 75.61 71 -1.35 85.6WLAN n 66.12 64 -0.57 93.6

2.5.3 Results 23

10−3

10−2

10−1

100

101

−200

−180

−160

−140

−120

−100

−80

−60

−40

−20

0

GSM EDGE, fs=26MHz, OSR=130, Simulation

Frequency [MHz]

Mag

nitu

de [d

BF

S]

SNR = 115.28 dBSNDR = 115.28 dBTHD = −Inf dBDR = 117.74 dBfsig = 0.07 MHzP

sig = −6.00 dB= −3.00 dB

FS

65536 FFT

10−3

10−2

10−1

100

101

−200

−180

−160

−140

−120

−100

−80

−60

−40

−20

0

UMTS, fs=61.44MHz, OSR=16, Simulation

Frequency [MHz]

Mag

nitu

de [d

BF

S]

SNR = 89.72 dBSNDR = 89.12 dBTHD = −98.02 dBDR = 92.50 dBfsig = 0.48 MHzP

sig = −6.00 dB= −3.00 dB

FS

65536 FFT

Figure 2.18: Analyzed spectrum of the output signal, cellular standards

24 2.5 Chosen Architecture

10−2

10−1

100

101

102

−200

−180

−160

−140

−120

−100

−80

−60

−40

−20

0

WLAN IEEE802.11a/b/g, fs=240MHz, OSR=12, Simulation

Frequency [MHz]

Mag

nitu

de [d

BF

S]

SNR = 72.78 dBSNDR = 72.15 dBTHD = −80.81 dBDR = 75.61 dBfsig = 2.50 MHzP

sig = −6.00 dB= −3.00 dB

FS

65536 FFT

10−2

10−1

100

101

102

−200

−180

−160

−140

−120

−100

−80

−60

−40

−20

0

WLAN IEEE802.11n, fs=320MHz, OSR=8, Simulation

Frequency [MHz]

Mag

nitu

de [d

BF

S]

SNR = 63.24 dBSNDR = 62.96 dBTHD = −75.00 dBDR = 66.12 dBfsig = 5.00 MHzP

sig = −6.00 dB= −3.00 dB

FS

65536 FFT

Figure 2.19: Analyzed spectrum of the output signal, WLAN standards

Vgs

Vds

3Circuit Design

3.1 Main Circuit

3.1.1 Circuit Synthesis

The synthesis of the main circuit is based on the switched-capacitor technique (see [JM96]for more details). The implemented architecture is shown in fig. 3.1.

4

6

1

6z−1

1−z−1+z

−111−z−1

G

2

5z−1

1−z−1

3

4+

z−1

1−z−1

7

8+

1

4

−

X(z)

4

−

Y (z)

4

6

4

6

1st integration stage 2nd integration stage

non-delayed resonator

3rd integration stage

3rd integration stage

quantizer

sum. point A

sum. point Csum. point B

DAC

Figure 3.1: Implemented architecture

The integration stages in the z-domain are replaced by their circuit equivalent which isshown in fig. 3.2. Although the implemented circuit uses differential signaling, this circuitequivalent is given in single-ended notation for the sake of simplicity. The same notationalso holds for the circuit equivalents which follows next.

25

26 3.1 Main Circuit

CA

CB

Vi(z)Vo(z)

1

z−1

1−z−1

Vo(z)Vi(z)

1

2

2

CA

CB

Figure 3.2: Circuit equivalent for an integration stage

The summation point A is realized with a switched-capacitor DAC which is explainedin sec. 3.6 in more detail. The resonator with its summation point B is implemented bysharing the amplifier of the 2nd integration stage (see fig. 3.3). Note that the clock phaseshave to be interchanged in order to satisfy the correct timing.

CA

CB

Vi(z)Vo(z)

11

2 2

11−z−1

Vo(z)Vi(z) −

CA

CB

Figure 3.3: Circuit equivalent for the resonator

The summation point C is implemented as an active summation. An example of such asummation point with two inputs is shown in fig. 3.4.

CA

Vo(z)2

1

2

1

2

2

1

Vi,1(z)

+

CB

CC

−Vi,2(z)

CA

CC

CB

CC

−

Vo(z)

Vi,1(z)

Vi,2(z)

Figure 3.4: Circuit equivalent for the active summation point with two input signals

This last summation point leaves room for optimization because it is possible to mergethe 4th integration amplifier with the summation amplifier. Such an approach is importantwith respect to power consumption and area occupation.

The optimization process is explained in three steps in fig. 3.5. The initial situation isshown in step 1. Two amplifiers are shown: The left one is the integration amplifier whilethe right one represents the summation amplifier. The calculation of the transfer functionleads to the following expression:

Y (z) = −C1

C3X1(z)− C1

C3

z−1

1− z−1X2(z) (3.1)

3.1.1 Circuit Synthesis 27

Inverting this output by an inverting buffer circuit leads to the desired transfer function:

Y (z) =C1

C3X1(z) +

C1

C3

z−1

1− z−1X2(z) (3.2)

In step 2, the z-domain description is changed by relocating the integration block z−1

1−z−1

behind the summation point. The calculation of the transfer function leads to the followingexpression:

Y (z) = −C1

C3X1(z) +

C1

C3

z−1

1− z−1X2(z) (3.3)

This transfer function is very similar to eq. 3.2. However, the first term is still negative. Itcan be easily changed into a positive one by applying differential signaling. Step 3 shows theresults. The path from X1,+(z) is connected to the negative input while the path X1,−(z)is connected to the positive input of the amplifier. Therefore, the sign of the term C1

C3is

changed. This leads to the following transfer functions:

Y±(z) =C1

C3X1,±(z) +

C1

C3

z−1

1− z−1X2,±(z) (3.4)

∆Y (z) = Y+(z)− Y−(z) =C1

C3∆X1(z) +

C1

C3

z−1

1− z−1∆X2(z) (3.5)

These equations are identical to the required transfer function (see eq. 3.2). Therefore,fig. 3.5(c) represents the solution of the merging process.

The optimized main circuit is shown in fig. 3.6.

28 3.1 Main Circuit

C1

C2

X2(z)

Y (z)1

1

2

2

2

1

2

1

2

2

1

X1(z)

k1

k2z−1

1−z−1

X1(z)

X2(z) + Y (z)

C3

C3

C3

k1 = C2

C3

k2 = C1

C3

Y (z) = −C2

C3

X1(z)− C1

C3

z−1

1−z−1X2(z)

−

−

(a) Step 1

C1

C2

X2(z)Y (z)

1

1

2

2

X1(z)

k1

k2

1

1−z−1

X1(z)

X2(z) + Y (z)

C3

k1 = C2

C3

k2 = C1

C3

Y (z) = −C2

C3

X1(z) + C1

C3

z−1

1−z−1X2(z)

−

1− z−1

z−1

(b) Step 2

C1

C2

X2,+(z) Y+(z)

1

1

2

2

X1,+(z)

C3

k1 = C2

C3

k2 = C1

C3

∆Y (z) = C2

C3∆X1(z) + C1

C3

z−1

1−z−1∆X2(z)

C3

Y−

(z)21

C1

2

1

C2

X1,−(z)

X2,−(z)

k1

k2

1

1−z−1

X1,+−(z)

X2,+−(z) + Y+−(z)−

1− z−1

z−1

(c) Step 3

Figure 3.5: Circuit optimization: Merging of the summation and the 4th integration am-plifier

3.1.1 Circuit Synthesis 29

+ -

- +

C3

12

C3

1 2

C4

C4

+ -

- +

C5

12

C5

1 2

C6

C6

vcm

ivcm

i

vcm

ivcm

i

vcm

ovcm

o

vcm

ovcm

o

+ -

- +

C7

1

1d 2d

2

C7

1

1d2d

2

C8

C8

vcm

i

vcm

i

vcm

o

vcm

o

+ -

- +

121 2

C2

C2

vcm

i

vcm

i

C12

C12

C13

2

vcm

ivcm

i

A3

A2

A1

A4

1d

1d 2d

2d

1d

1d 2d

2d

1d2

d

1

C13

2

vcm

ivcm

i

1d 2

d

1 C11

C11

C10

C10

C9

C9

DW

A

C1,i

1

2d

SW

+〈i〉

vref

p

vref

n

〈6:0〉

C1,i

1

vref

p

vref

n

〈6:0〉

77

〈6:0〉

Quantize

rxD

O

SW−

〈i〉

DA

C〈i〉

SW

+〈i〉

SW−

〈i〉

SW−

〈i〉

SW

+〈i〉

Figure 3.6: Optimized main circuit

30 3.2 Capacitors

3.2 Capacitors

The ratios of the capacitances are defined in the architecture by the path-gains. However,the sizes of the individual capacitors are not. In a switched capacitor circuit, thermal noisefrom resistive components is sampled on the capacitors and enters the circuit as kT/C-noise. Since the sampled noise is inversely proportional to the capacitance, the capacitorshave to be chosen large enough that the thermal noise does not compromise the converter-performance. On the downside, a larger capacitance requires more current to be chargedin the same time and therefore, a larger amplifier is needed. The different noise-sources arepointed out and their effect on the output is calculated in order to find an optimal sizingwith regard to noise and capacitive load.

All calculations are performed on a single-ended circuit. For a differential circuit, thecalculations are identical, except, that the capacitor sizes have to be divided by two. Thisfactor arises from the fact, that in a differential circuit, the signal amplitude is doubledand hence the signal power multiplied by four, while the noise power on the two branchesonly doubles. Since the capacitance is reversely proportional to the noise power, it can bedivided by two for the same DR.

3.2.1 Thermal Noise Calculations

In Σ∆-modulator circuits there are two main sources of noise: quantization and thermalnoise.

It is important, that the thermal noise dominates in the standards with high resolutiondemands and high OSRs, because the quantization noise is very small there. In the stan-dards with low OSRs, the quantization noise dominates, because the same capacitors areused as in the low-OSR standards.

So, choosing a thermal noise floor that lies slightly below the required DR is favorable. Inthe rest of this section a mathematical description of the thermal noise is presented and anexpression for the minimally allowable capacitance is derived. The calculations are carriedout for a simple switched-capacitor single-ended integrator (see fig. 3.7).

Cs

Vi(z)Vo(z)

Figure 3.7: Switched capacitance Cs of an integration stage

The one-sided power spectral density (PSD) of the thermal noise caused by a resistor is:

Sth(f) = 4kbTR (3.6)

For high OSRs, a switched capacitor with a capacitance Cs can be approximated with anequivalent resistance of Req = 1

Csfs. Eq. 3.6 leads to the following expression for describing

3.2.2 Thermal Noise Transfer Functions 31

the noise sampled on a switched capacitor:

Sth,Cs(f) =4kbT

Csfs(3.7)

The total noise power PCs in the band of interest fb is:

PCs =∫ fb

0Sth,Cs(f)df =

4kbTfb

Csfs=

2kbT

Cs ·OSR(3.8)

Therefore, increasing the capacitance Cs leads to a lower thermal noise floor.

The DR required by a standard is the ratio of the maximal signal power Ps,max to thetotal noise power Pn. If thermal noise dominates over all other noise sources, the thermalnoise floor can be calculated to lie below the specified DR by ∆th dB which accounts forall other noise sources in the circuit. Pn,tot must be:

Pn,tot ≤ Ps · 10−DR10 (3.9)

Pn,th ≤ Ps · 10−DR+∆th

10 (3.10)

Therefore, the following condition holds for Cs:

Cs ≥2kbT

OSR · Pn,th(3.11)

3.2.2 Thermal Noise Transfer Functions

The thermal noise sampled on the switched capacitors is seen at the output of the circuitand therefore influences the performance of the whole circuit. Thermal noise sources mayhave different influences on the output because of different transfer functions from a specificsource to the output. This section calculates the contribution of every thermal noise sourceto the output. A good summary on this topic can be found in [YGS02].

z−1

1−z−1

+

E1(z)

a1z−1

1−z−1

+

E2(z)

a2z−1

1−z−1

+

E3(z)

a3z−1

1−z−1

+

E4(z)

a4 Y (z)

Figure 3.8: Simplified SFG for calculating the thermal noise propagation

The analysis is based on the simplified circuit description in fig. 3.8. The four switchedcapacitors before every amplifier sample the thermal noise from different sources and aremodeled as additive error inputs Ei(z). The additional feed-forward paths are not consid-ered here for the sake of simplicity. The general form of the transfer function Ti(z) froman input Ei(z) to the output Y (z) can be derived to:

Ti(z) =∏4

k=i [ak ·H(z)]1− a1 · a2 · a3 · a4 ·H(z)4

with H(z) =z−1

1− z−1(3.12)

32 3.2 Capacitors

For a high loop-gain (a1 · a2 · a3 · a4 · H(z)4 1), this transfer function can be furthersimplified to:

Ti(z) ≈∏4

k=i [ak ·H(z)]−a1 · a2 · a3 · a4 ·H(z)4

Ti(z) ≈ − 1H(z)i−1 ·

∏i−1j=1 aj

PCs,i denotes the noise power caused by the switched capacitor Cs of the ith integrator. Asthe capacitor Cs is switched with a frequency of fs, the noise power is equally spread overfs which leads to the following input PSD:

Sin,i(f) =PCs,i

fs(3.13)

So, for the filtered noise of each input Ei(z) holds:

Sout,i(f) = |Ti(z)|2 · Sin,i(f) (3.14)

The total output noise power in the band of interest fb is calculated as follows:

Pn,i =∫ fb

−fb

Sout,i(f)df =PCs,i

fs·∫ fb

−fb

|Ti(z)|2 df (3.15)

Solving eq. 3.15 with the transformation z = e2πfj

fs leads to the following result:

Pn,i =PCs,i

π(2i− 1)∏i−1

j=1 a2j

·( π

OSR

)2i−1= PCs,i · Fi (3.16)

Therefore, the total output referred noise power Pn,tot is1:

Pn,tot =4∑

i=1

Pn,i (3.17)

The filter coefficients F for the implemented system are listed in tab. 3.1.

Table 3.1: Filter coefficients FWLAN n WLAN a/b/g UMTS GSM-EDGE

F1 1 1 1 1F2 0.2 0.09 0.05 7.6e-4F3 0.055 0.011 3.5e-3 7.9e-7F4 0.053 4.7e-3 8.3e-4 2.9e-9

1The output referred noise is identical to the input referred noise.

3.2.3 Capacitor Sizes 33

3.2.3 Capacitor Sizes

Now that the effect of every sampling capacitor size on the output-noise is known, capacitorsizes can be calculated, that impose minimum loads on the amplifiers, and produce at mostthe allowed thermal noise. For high OSRs, the noise contribution by sampling capacitorsinside the loop is attenuated enough that it can be neglected in the calculation. Only theinput capacitor has to match the thermal noise requirements. With lower OSRs, the filterattenuation is smaller and the noise contribution sampled by the inner loop capacitors isno longer negligible. Hence, the problem to solve is:

Given Ci =2kbT

OSRFi

Pn,i, (3.18)

minimizen∑

i=1

Ci (3.19)

under the condition Pn,th ≥n∑

i=1

Pn,i. (3.20)

The MATLAB optimization-algorithm with a tolerance of 10fF leads to the optimizedset of minimal capacitances for the 4 amplifiers of the differential circuit:

Table 3.2: Optimization resultsStandard Cmin,s,1 Cmin,s,2 Cmin,s,3 Cmin,s,4

GSM-EDGE 928fF 4fF <1fF <1fFUMTS 949fF 239fF 16fF 4fF

WLAN a/b/g 201fF 90fF 11fF 5fFWLAN n 60fF 61fF 17fF 16fF

To guarantee a minimum matching, only capacitances are chosen that are larger thanCmin = 100fF. For interleaved capacitors, where the partitions physically lie close to eachother, the partial capacitances are chosen larger than Cmin,part = 50fF. Further, only mul-tiples of 10fF are allowed for the sake of simplicity.

The input scaling factor si, which was transformed into a ratio of small integers snum,i/sden,i

in sec. 2.4.2, is also the ratio Cs,i/Cf,i. Therefore, Cs,i is assembled out of snum,i partialcapacitances. To fulfill the requirements above, the following formula is used to calculateCs,i:

Cs,i = max(

Cmin,max(

Cmin,part,

⌈Cmin,s,i

snum,i · 10fF

⌉· 10fF

)· snum,i

)(3.21)

Once the sizes of the amplifier sampling capacitors are fixed, the remaining capacitors canbe calculated with the path-gains from the signal flow graph. The calculated capacitancesare summarized in tab. 3.3.

34 3.2 Capacitors

Table 3.3: Size of capacitorsCapacitor Amount of Parts Total Size

C1 7× 140fF 980fFC2 8× 140fF 1.12pFC3 3× 80fF 240fFC4 4× 80fF 320fFC5 2× 50fF 100fFC6 5× 50fF 250fFC7 2× 50fF 100fFC8 12× 50fF 600fFC9 3× 50fF 150fFC10 8× 50fF 400fFC11 8× 50fF 400fFC12 8× 50fF 400fFCsum 5.06pF

Ctot = 2 · Csum 10.12pF

3.2.4 Variable Capacitor C13

As the capacitance C13 depends on the chosen standard, it needs to be adjustable. The chipis assumed to provide two standard-select bits SelxS〈1 : 0〉. The sizes for the capacitor arelisted in tab. 3.4 for each standard. They can be realized in hardware with 6×80fF-resistorsaccording to the schematic in fig. 3.9.

Table 3.4: Capacitance of C13 for every standardStandard Calculated Size Effective size SelxS〈1 : 0〉GSM-EDGE 0.0fF 0.0fF 00UMTS 26.55fF 26.66fF 01WLANa/b/g 53.10fF 53.33fF 10WLANn 119.47fF 120.0fF 11

C+

C−

SelxS〈1〉

SelxS〈0〉

C = 80fF

C

C

C

C

C

C+

C−

⇐⇒

Figure 3.9: Schematic of the variable capacitor C13

3.2.5 Consequences for the Circuit-Scalability 35

3.2.5 Consequences for the Circuit-Scalability

Since the capacitors are the same for all standards, thermal noise would actually be toolow for some fast standards like e.g. WLAN. In fig. 3.10(a), the spectrum of the modulatoris sketched with the thermal noise (red shaded area) ∆th dB above the quantization noise(blue shaded area). Due to the capacitor optimization for another standard, the PSD ofthe thermal noise is reduced to the level of the red, dashed curve.

Since the amplifier output-swing is reduced for higher currents that are needed by thefaster standards, this can be turned into an advantage. If the quantizer reference-levelsare scaled together with the output-swing and the SQNR stays the same, the quantizationnoise also scales linearly with the swing (at least in an ideal quantizer). As it is shownin fig. 3.10(b), the input-swing, together with the quantization noise (blue shaded area),can be reduced to an extent, where the thermal noise is again only ∆th dB above thequantization noise.

log (ω)

‖N

TF‖

ωBW

[dB]

∆th

(a) Thermal noise reduction due to over-sized capacitor

log (ω)

‖N

TF‖

[dB]

∆th

(b) Swing reduction

Figure 3.10: Consequences of the capacitor choice for the circuit-scalability

The thermal noise sampled by the n amplifier input capacitors is filtered with the noisetransfer functions and the sum is taken. The minimally allowed fullscale signal power canbe calculated with the formula for the DR for the standard j:

Ps,min = Pn,th10DRj+∆th

10 =

(n∑

i=1

2kbT

Cs,iOSRFi

)10

DRj+∆th10 (3.22)

For the differential design, the calculated lowest possible voltage swings and the availableamplifier output swing are compared in tab. 3.5.

Table 3.5: Lowest possible input-swings, actually available amplifier swings and the choseninput-swings of the Σ∆-modulator

Standard Possible swing Amplifier swing Chosen swingGSM-EDGE 681mV 760mV 700mVUMTS 689mV 640mV 700mVWLAN a/b/g 317mV 470mV 350mVWLAN n 173mV 400mV 350mV

36 3.3 Quantizer

3.3 Quantizer

3.3.1 The Ideal Quantizer

The input-output relation for an ideal quantizer with slope 1 and step size ∆ is shown infig. 3.11. Its mathematical description is:

y(x) =

ymax x ≥ xmax...ymin + ∆ · i xmin + i ·∆ ≤ x < xmin + (i + 1) ·∆ with i =

⌊|x−xmin|

∆

⌋...ymin x < xmin

(3.23)An ideal quantizer is mostly described by its levels. When it has n levels, the step size canbe calculated as follows:

∆ =ymax − ymin

n− 1=

xmax − xmin

n− 2(3.24)

x

y(x)

0

∆

∆

ymin

ymax

xmaxxmin

Figure 3.11: Ideal quantizer

When the slope is not 1 but k instead, the y-axis is scaled by k. This scaling can be usedto amplify an incoming signal while quantizing its amplitude at the same moment.

3.3.2 Calculation of the Reference Voltages

As the output of the quantizer is converted back into an analog signal and subtracted fromthe input signal of the Σ∆-modulator on the feedback path, it must have the same swing as

3.3.3 Implementation 37

the input signal. The corresponding input signal swings for each standard are summarizedin tab. 3.5. As the quantizer has a slope that is not 1 but 4 instead because the path-gainfrom the last amplifier to the quantizer is 4, the input signal swing of the quantizer isdetermined by dividing the input signal swing of the Σ∆-modulator by four. As the inputof the quantizer is connected to the output of the 4th amplifier and its output (togetherwith the DAC of the input stage) to the input of the Σ∆-modulator, the common-modevoltage of the input and the output are the same. They are 600mV. Fig. 3.12 illustratesthe calculation for GSM-EDGE and UMTS. The same illustration can be drawn for WLANa/b/g and n by dividing the swings by two. As the quantizer has eight levels, the referencevoltages ∆Vref can be determined by dividing the total swings in tab. 3.5 by the slope gain4 and then by 7 because the quantizer has 7 reference levels (see eq. 3.24).

350mV

350mV

350mV

350mV

×4

×4

87.5mV

87.5mV

87.5mV

87.5mV

Input Output

0 50 100 150-50-100-150

100

300

500

700

∆vo [mV]

∆vi [mV]

-100

-300

-500

-700

∆vi = vi,+ − vi,- ∆vo = vo,+ − vo,−

600mV

600mV

Figure 3.12: Swing calculation for the quantizer (including the DAC in the feedback path):The calculations were illustrated for GSM-EDGE and UMTS.

3.3.3 Implementation

Every quantizer consists of a reference generation unit and some comparators. The referencegeneration unit is needed by the comparators for comparing the current input signal levelto the corresponding reference voltages. This reference unit is implemented with a resistiveladder. The output of a comparator with single-ended and a comparator with differentialinput signals can be described as follows:

for single-ended input signals: for differential input signals:if vi > vr then

vo = Vhigh

elsevo = Vlow

end if

if (vi+ − vi−) > (vr+ − vr−) thenvo = Vhigh

elsevo = Vlow

end if

38 3.3 Quantizer

An example for two three-level quantizers that use single-ended as well as differential sig-naling is shown in fig. 3.13. Furthermore, the example shows that for a n level quantizerthere are n− 1 comparators necessary.

vi

vo = vo1 + vo2

vr1

vr2

vo1

vo2

vi

vr1

vr2

vi

2 vo

vo2

vo1

vo2

vr+,12 vo

vr−,1

vr+,2

vr−,2

vi+

vo2

vi−

vi+vi−

∆vi

∆vr1

∆vr2

vo = vo1 + vo2

levels: n = 3

for single-ended signaling for differential signaling

Figure 3.13: Example of a three level quantizer for single-ended and differential signaling

The quantizer that is used in this Σ∆-design applies differential signaling and has eightlevels (see fig. 3.14). Therefore, seven comparators are needed. For establishing seven volt-age references, a resistive ladder with six resistors is needed. Each resistor has a resistanceof 621.81Ω in order to guarantee a good matching. The thermal noise that is caused byeach resistor is calculated for the standard with the highest bandwidth (fb = 20MHz) atroom temperature (T = 300K):

v =√

4kbTRfb (3.25)

The RMS voltage v is 14.35µV and is small in comparison to the resolution of the compara-tor of about 1.8mV (see sec. 3.4). The biasing of the resistive ladder is shown in fig. 3.15. Asthe reference voltages must be very accurate, a cascode current mirror was used. The quan-tizer was designed for the standard with the highest swing; hence for the GSM standard.Afterwards, the bias current of the ladder was scaled down for the remaining standards.These bias currents are summarized in tab. 3.6.

The clock signal for comparison Phi1DxC (active high) is delayed to the signal Phi1xCby approximately 0.8ns. This delay is necessary because the amplifiers need some time tosettle. The delay unit is currently implemented with a chain of inverters. Future imple-mentations should use a delay-locked loop (DLL) in order to keep the delay between thecontrol signals Phi1xC and Phi1DxC constant for temperature and process variations.

3.3.3 Implementation 39

Table 3.6: Bias current iquant and voltage drop ∆VR of the quantizer for each standardStandard iquant [µA] ∆VR [mV]GSM-EDGE 10 25UMTS 10 25WLAN a/b/g 5 12.5WLAN n 5 12.5

ResCmpxDO〈i〉

i com

p〈i〉

Comparator

1

2

3

4

5

6

7

icomp

icom

p〈0〉

icom

p〈6〉

w = 890nm

l = 180nm

w = 1.98µm

l = 420nm

1

2

3

4

i

5

6

7

Bias Currents for the Comparators

vin+

vin−

ResCmpxDO〈0 : 6〉

iquant

icomp

vin+

vin−

Phi1xCDelay

Phi1DxC

vin+

vin−

vref+

vref−

Phi1

DxC

Figure 3.14: Simplified schematic of the designed quantizer

40 3.3 Quantizer

C = 1pF

C = 1pF

C = 1pF

C = 1pF

C = 1pF

C = 1pF

C = 1pF

1

2

3

4

5

6

7

iquant

w = 8.42µm

l = 21µm

R = 621.81Ω

w = 8.42µm

l = 21µm

R = 621.81Ω

w = 8.42µm

l = 21µm

R = 621.81Ω

w = 8.42µm

l = 21µm

R = 621.81Ω

w = 8.42µm

l = 21µm

R = 621.81Ω

w = 8.42µm

l = 21µm

R = 621.81Ω

w = 3.25µm

l = 280nm

w = 10µm

l = 400nm

w = 5µm

l = 1.5µm

w = 5µm

l = 2µm

900mV

600mV

675mV

600mV

525mV

660mV

300mV

i b=

10µA

vcmo

1 : 4

1 : 4vin+

vin−

ResCmpxDO〈0 : 6〉

iquant

icomp

vin+

vin−

Phi1xCDelay

Phi1DxC

Figure 3.15: Resistive ladder

3.4 Comparator 41

3.4 Comparator

Resolution and speed of the quantizer strongly depend on resolution and speed of the un-derlying comparators. Therefore, it is important to design a comparator that copes withthe speed requirements of the system and that delivers a resolution which is high enoughin order not to degrade the system significantly.

The resolution of the comparator is determined by the minimally allowable input voltagefor a correct comparison. It is mainly influenced by mismatch which leads to an offsetvoltage and which in turn causes the minimally allowable input voltage to increase.

The speed of the comparator is determined by the timespan for carrying out a comparison.Bandwidth limitations due to parasitic capacitances limit the speed.

3.4.1 Categories of Comparators

Comparators may be categorized as follows:. open-loop comparators. regenerative comparators. combination of open-loop and regenerative comparators

Open-loop comparators are operational amplifiers (OpAmps) without feedback and hencethey do not need compensation. Regenerative comparators on the other hand use positivefeedback to pull the incoming signal either to the high or low rail according to the signallevel. These comparators mostly use the track-and-latch principle and have at least twocross-coupled transistors that form a positive feedback. They are clocked and work in twophases:Reset, Recovery or Track Phase The cross-coupled transistors are held in equilibrium by

a switch and steered slightly toward one side according to the input signal.Regeneration or Latch Phase The cross-coupled transistors perform a positive feedback

in accordance to their preset node voltages from the previous phase. The positivefeedback steers these node voltages towards the rail voltages.

As open-loop comparators are not clocked in comparison to regenerative comparators,they do not suffer from kickback noise. However, in general their speed is slower thanfor regenerative comparators. Therefore, regenerative comparators are very attractive forfast applications. The resolution of open-loop comparators can be increased by raising thegain of the amplifier. As the resolution of regenerative comparators depend on the mis-match and hence the offset voltage of the latch, the introduction of pre-amplification stagescan significantly raise the resolution because the input referred offset voltage is divided bythe gain of the pre-amplification stages (assuming that these stages are offset compensated).

As Σ∆-modulators impose high demands on the speed and the resolution of comparators,a regenerative comparator with one pre-amplification stage was implemented. The pre-amplification stage is necessary in order to perform a comparison of two differential signals.Further, the pre-amplification stage acts as barrier between the latch and the input circuitrywith respect to kickback noise. And finally the pre-amplification raises the resolution forthe reasons mentioned above.

42 3.4 Comparator

3.4.2 Implemented Comparator Design

The chosen design of the comparator is shown in fig. 3.17. It is a regenerative comparatorwith one pre-amplification stage that works according to the track-and-latch principle. Thetiming diagram is shown in fig. 3.16.

CompDxC

CompxC

CompxCB

Figure 3.16: Timing diagram

In the recovery phase (when CompxC is low), the differential pairs in unit A generate avoltage difference at their branches a and b which slightly steers the drain voltages v1,2 ofthe transistors M3,4 of the latch (unit D) towards one side. As the switch M8 is closed,these upper transistors represent a load for the differential input pairs. The generation ofthe branch voltages a and b can be thought of as follows: When vin+,in− > vref+,ref−, morecurrent flows through the input voltage transistor M2,15 than through the reference volt-age transistor M1,16. When more current flows through branch a or b, the correspondingbranch experiences a lower voltage because the bias transistors M11 and M12 in unit Blead to a larger voltage drop. Of course the same ideas also apply for vin+,in− < vref+,ref−.The transistors in unit B allows the biasing of the differential input pairs while keeping thecurrent in the latch small. Without these transistors, the bias current for these input pairsmust be delivered by the upper latch transistors M3,4.

In the regeneration phase (when CompxC is high), the differential pairs are disconnectedfrom the latch (unit D). The latch swings its node voltages v1,2 – according to its presetvalue – to the rail voltages Vss and Vdd. Unit F represents a SR-latch with the enable inputCompxC which stores the compared value for maintaining the value in the recovery phase.In order to hold the differential pairs at their bias voltages, while they are disconnectedfrom the latch, the switches M13,14 are closed.

For adjusting the comparator to the required performance for each standard, the biascurrent icomp and the on-resistance Ron of the switch M8 are changed respectively.

3.4.3 Design Considerations

The implemented comparator design with its transistor sizes and the bias voltages forWLAN n is shown in fig. 3.19. Fig. 3.18 shows the implementation of the tunable on-resistance Ron of the switch M8.

3.4.3 Design Considerations 43

Com

pxC

Com

pxC

BP

hi1

DxC

I

Com

pD

xC

Com

pxC

vin

+

vin−

vref−

vref+

Cw

=10fF

Cw

=10fF

Com

pxC

Com

pD

xC

Com

pxC

BC

om

pxC

B

Res

Cm

pxD

O

Com

pxC

vin

+

vin−

vref+

vref−

Phi1DxC

Vb

conn

1

conn

2

conn

2

conn

1

A

B

C

D

E

F

ab

M1

M2

M3

M4

M5

M6

M7

M8

M9

M10

M11

M12

M13

M14

M15

M16

v1

v2

Figure 3.17: Comparator design

44 3.4 Comparator

CompxC

SelxS〈0〉

SelxS〈1〉

v+ v−

CompxC

v−

v+

w = 120nm

l = 60nm

w = 120nm

l = 120nm

×18

Figure 3.18: Tunable on-resistance for the switch M8

Recovery Time, Regeneration Time and Gain

The recovery time τrec and the regeneration time τreg of a latch (see unit D in fig. 3.17) canbe calculated with the following equations:

τrec = 2RonCL (3.26)

τreg =CL

gm3,4 + gm5,6(3.27)

The overall load capacitance of the latch CL is assumed to be 15fF. CL includes the wire ca-pacitance Cw which is shown in fig. 3.17. It is assumed to be 10fF. Ron is the on-resistanceof the switch M8. In order to have a short recovery and regeneration time, the load ca-pacitance CL and the on-resistance Ron of the switch M8 need to be low. Further, thetransconductance of the latch transistors (M3,4 and M5,6) needs to be large.

The calculated regeneration and recovery times for each standard are summarized intab. 3.7. Tab. 3.7 also shows the required phase time Tph and the transconductance of thelatch transistors M3,4 and M5,6. The corresponding sizes of these transistors are summa-rized in fig. 3.19.

Table 3.7: Design parameters for the implemented comparator, part 1Standard Ron [kΩ] gm3,4 [µS] gm5,6 [µS] τrec [ns] τreg [ps] Tph [ns]GSM-EDGE 46.9 7.4 603.9 1.41 24.5 19.131UMTS 46.9 7.4 603.9 1.41 24.5 8.038WLAN a/b/g 30.3 14.6 497.2 0.91 29.3 1.983WLAN n 23 18.9 452.3 0.69 31.8 1.462

The gain of the comparator in fig. 3.17 can be calculated as follows:

A =Rongm1

2−Ron(gds1,2 + gds3,4 + gds5,6 + gm5,6)(3.28)

3.4.3 Design Considerations 45

Com

pxC

Com

pxC

BP

hi1

DxC

I

Com

pD

xC

×2

×4

×7

×13

×18

vb

=300m

V

i com

p

Com

pxC

vin

+

vin−

vref− vref+

vb

300m

V

300m

V300m

V

w=

2.7

5µm

l=

420nm

m=

3

w=

2.7

5µm

l=

420nm

m=

3

w=

1.2

µm

l=

200nm

w=

3.5

5µm

l=

300nm

w=

3µm

l=

60nm

w=

1.5

µm

l=

60nm

600m

V

600m

V600m

V

600m

V

w=

3.5

5µm

l=

300nm

×2

×2

Cw

=10fF

Cw

=10fF

w=

2.6

2µm

l=

420nm

600m

Vw

=1.9

5µm

l=

120nm

w=

2.7

5µm

l=

420nm

Com

pxC

Com

pD

xC

Com

pxC

BC

om

pxC

B

w=

1µm

l=

140nm

w=

1µm

l=

140nm

RC

1xD

w=

0.1

2µm

l=

60nm

w=

6.2

µm

l=

120nm

×4

×9

Res

Cm

pxD

O

×2

×2

RC

2xD

RC

1xD

RC

2xD

Com

pxC

vin

+

vin−

vref+

vref−

Phi1DxC

icomp

Figure 3.19: Comparator

46 3.4 Comparator

A high gain is achieved by increasing the transconductance of the input transistors M1,2

and M15,16 (unit A) while decreasing the upper transistors M5,6 of the latch (unit D).

The calculated gains as well as the achieved unity-gain-bandwidths (UGBWs) and thebias currents icomp for each standard are summarized in tab. 3.8. Tab. 3.8 also shows thetransconductance of the input input transistors M1,2 and M15,16 respectively. The sizes ofthese transistors are shown in fig. 3.19.

Table 3.8: Design parameters for the implemented comparator, part 2Standard icomp gm1,2 [µS] UGBW [GHz] AGSM-EDGE 6 168.9 0.750 4.8UMTS 6 168.9 0.750 4.8WLAN a/b/g 14 302.6 1.27 5.9WLAN n 20 381.9 1.53 5.6

Offset Voltage

Mismatch is mainly caused by the input transistor pairs (unit A) and the upper latchtransistors (unit D). A mismatch of these transistor pairs leads to an offset voltage thatdegrades the resolution of the comparator because the minimally allowable input voltagemust be increased for a correct comparison (see sec. 3.4.3).

The mismatch of two identical NMOS or PMOS transistors can be described by thefollowing equation (see [Bal04]):

σ∆Vgs =1√WL

√(α1(Vgs − Vth)

2

)2

+ α22 (3.29)

σ∆Vgs is the standard deviation of the gate source voltage Vgs of the transistors. α1 and α2

are two process technology parameters. For α1 α2 and when Vgs − Vth is small, eq. 3.29can be simplified to:

σ∆Vgs =α2√WL

(3.30)

Knowing this process related parameter α2, it is possible to derive the input referred totaloffset voltage σtot of the implemented comparator design (see fig. 3.17). For calculatingσtot, only the input transistor pair M1,2 and the upper latch transistor pair M3,4 are con-sidered. Offset voltages of the remaining parts are assumed to be negligible. Further, onlythe recovery phase is considered because mismatch play an important role there.

Fig. 3.17 shows that the offset voltage caused by the transistors M3 and M4 needs to bereferred back to the input. The switch transistors M7 and M8 can be omitted because theiroffset voltage contribution is small. The offset current that is produced at the transistorsM3,4 is calculated to gm3,4 · σ∆Vgs3,4 . This current flows into the transistor pair M1,2 andproduces a voltage deviation of gm3,4

gm1,2· σ∆Vgs . Therefore, the total offset voltage of the

comparator is:

σ2off,tot = σ2

∆Vgs1,2+(

gm3,4

gm1,2· σ∆Vgs3,4

)2

(3.31)

3.4.3 Design Considerations 47

Assuming that all PMOS and all NMOS transistors have the same standard deviation ofthe offset voltage, leads to the following simplification:

σoff,tot =

√σ2

diff. pair +(

gm3,4

gm1,2· σlatch

)2

(3.32)

In this equation σdiff. pair is the standard deviation of the differential input transistor pairand σlatch the standard deviation of the upper two latch transistors.

An offset voltage σoff,tot in the comparator leads to a reduced performance which canbe measured as SNDR degradation. This degradation can be calculated by the followingequation that was derived in [Her04]:

SNDRdeg,off = 10 · log(

1 + 6 ·(σoff,tot

∆

)2)

(3.33)

∆ is the input step size of the quantizer. The calculated SNDR values for each standardare shown in tab. 3.9. The total offset voltage σoff,tot is about 3.3mV.

Table 3.9: Design parameters for the implemented comparator, part 3Standard ∆ [mV] SNDRdeg,off [dB]GSM-EDGE 25 0.43UMTS 25 0.43WLAN a/b/g 12.5 1.52WLAN n 12.5 1.52

For establishing a good matching of the input transistors M1,2 as well as M15,16 andthe upper latch transistors M3,4, these transistors must be chosen large enough. The sizeof these transistors have already been chosen in the previous section. If the size of thesetransistors is still not large enough in order to guarantee a certain mismatch, they mustbe increased and the corresponding gain, recovery and regeneration time recalculated andanalyzed whether the values are acceptable (see previous sec. 3.4.3).

Resolution: Minimally Allowable Input Signal Difference

The resolution of the comparator is defined by the minimally allowable input signal differ-ence ∆Vin,min so that a correct comparison is possible. This minimal input signal differenceleads to a reduced performance of the comparator which can be measured as SNDR degra-dation. This degradation can be calculated with eq. 3.33 that was used for the calculatingthe SNDR degradation due to offset voltages:

SNDRdeg,comp = 10 · log

(1 + 6 ·

(∆Vin,min

∆

)2)

(3.34)

For increasing the resolution of the comparator, the signal CompxC is delayed applied tothe switches M9 and M10. This can be explained as follows: When the recovery phaseends, the voltage difference caused by the differential input pairs should be applied slightly

48 3.4 Comparator

longer to the latch (unit D) in order to have more control on it when the switch M8 isabout to open. It is important to see that such an approach also increases the kickbacknoise.

The calculated SNDR degradation values are shown in tab. 3.10. ∆Vin,min was deter-mined by an overdrive test (see sec. 3.4.4 for more details).

Table 3.10: Design parameters for the implemented comparator, part 4Standard ∆ [mV] ∆Vin,min SNDRcomp,deg [dB]GSM-EDGE 25 1.8 0.13UMTS 25 1.7 0.12WLAN a/b/g 12.5 1.7 0.46WLAN n 12.5 1.7 0.46

Kickback Noise Reduction

Kickback noise – as its name already suggests – is noise that influences back to the input.It is caused by rapid voltage changes at the drain of the input transistors (see unit A infig. 3.17). As every transistor has a finite gate drain capacitance Cgd, the voltage changesare translated into current peaks (i = C · v) that propagate to the input and hence tothe output of the circuit before the comparator. The relevance of kickback noise stronglydepends on its strength and the circuit that is connected to the input of the comparator.The strength of the kickback noise may vary in a huge range between some µA and a fewmA. It is in the order of 20µA for the designed comparator. The input of the compara-tor that is used in the designed Σ∆-modulator is connected to the resistive ladder of thequantizer and to the output of the last amplifier. A peak current that enters the resistiveladder leads inevitably to a disturbance of the reference voltages. The time span of thisdisturbance is important. If the disturbance vanishes before another comparison is carriedout, it does not influence the result of the comparison. In order to trap the peak current,a capacitance of 1pF is placed at the output of each voltage reference (see fig. 3.15). Thiscapacitance smooths the voltage variation of the resistive ladder due to kickback noise. It isalso possible to decrease the kickback noise effect by increasing the current in the resistiveladder. However, as the reference voltages must be the same, the value of the resistors inthe resistive ladder decreases. This method leads on one hand to less thermal noise but onthe other hand also to a higher static power consumption. Therefore, a trade-off betweenthe value of the mentioned absorber capacitor, the value of the resistors in the resistive lad-der and the static power consumption is necessary. A further place where the peak currentharms the performance of the Σ∆-modulator is at the output of the last amplifier. Thefeedback capacitors of this amplifier integrate the current peak that leads to a settling error.

In order to reduce kickback noise, two methods were followed:Disconnection of the Latch During the Regeneration Phase The switches M9 and M10

disconnects the latch (unit D) from the differential input pairs (unit A) during theregeneration phase. However, when these switches are about to open, the branches aand b are vulnerable to rapid voltage changes which cause kickback noise.

Small Input Transistors Therefore, it is absolutely necessary to keep the input transistors

3.4.4 Simulation Results 49

small so that Cgd of the transistors are small. However, as the input transistors haveto match in order to keep the SNDR degradation low (see sec. 3.4.3), a trade-off forthe size of these input transistors must be searched.

A good introduction to kickback noise and a summary of kickback noise reduction tech-niques can be found in [FV06].

3.4.4 Simulation Results

Transfer Function

The transfer function from vin+,− to v1,2 was evaluated for each standard by keeping thecontrol signal CompxC constantly at low. The result is shown in fig. 3.4.4.

100kHz 1MHz 10MHz 100MHz 1G 10GHz−10

−5

0

5

10

15

20

frequency

gain

[dB

]

Transfer Function of the Comparator

GSM−EDGE / UMTSWLAN IEEE 802.11a/b/gWLAN IEEE 802.11n

Figure 3.20: Transfer function of the comparator from vin+,- to v1,2

Overdrive Test

For evaluating the resolution of the comparator, a so called overdrive test was used (see also[Raz97] for more details). The idea of the test is to apply the highest possible input voltagefollowed by the lowest possible input voltage that leads to a correct contrary comparison.Fig. 3.21 shows the overdrive test for WLAN n. vref+ and vref− as well as vin− wereconstantly kept at 600mV while the overdrive sequence was applied to vin+. The transientbehavior of the control signals are shown in fig. 3.22.

50 3.4 Comparator

0 2 4 6 8 10 12 14 16−0.2

0

0.2

0.4

0.6

0.8

1

1.2

time [ns]

ampl

itude

[V]

Signals vinp, vin

n, vref

p, vref

n and CompDxC

0 2 4 6 8 10 12 14 16−0.2

0

0.2

0.4

0.6

0.8

1

1.2

time [ns]

ampl

itude

[V]

Signals va, v

b and CompDxC

va

vb

CompDxC

CompDxCvin

pvref

p / vref

n / vin

n

Figure 3.21: Comparator signals for the overdrive test (WLAN n)

0 2 4 6 8 10 12 14 160

0.5

1

time [ns]

ampl

itude

[V]

CompxC

0 2 4 6 8 10 12 14 160

0.5

1

time [ns]

ampl

itude

[V]

CompDxC

0 2 4 6 8 10 12 14 160

0.5

1

time [ns]

ampl

itude

[V]

CompxCB

Figure 3.22: Control signals for the overdrive test (WLAN n)

3.5 Amplifier 51

3.5 Amplifier

The main amplifier used in this design is a telescopic regulated-cascode amplifier. A tele-scopic amplifier saves the copied branch current used in a folded amplifier, but has a nar-rower swing. In the system design, the reduced output-swing has already been taken careof. A regulating-cascode amplifier increases the DC-gain to reduce the integrator leakagewhich causes a pole error. It is shown in fig. 3.23.

ib

vin+ M1+

+ -

- +

ib

2

ib

2

M1−

M2+ M2−

vin−

vout− vout+

Figure 3.23: Concept drawing of a regulated-cascode telescopic amplifier

This amplifier structure and the involved gain-boosting technique with the regulatingamplifiers has been analyzed in detail, e.g. in [KB90], and will therefore only be discussedhere to an extent necessary to understand the dimensioning process.

The gain of a cascode with steady cascode-biasing is given as the product of the gainsA1 and A2 of the single stages:

∆vout

∆vin= A2 ·A1 (3.35)

Ai = gm,i · rout,i (3.36)

The concept of a regulating cascode amplifier is to multiply the small-signal-voltage atthe drain of M1 by a factor of Areg and to apply this voltage at the gate of the cascodetransistor. This loop gain regulates the drain voltage of M1 and boosts the gain of thewhole amplifier which now is:

∆vout

∆vin= A2 · (Areg + 1) ·A1 (3.37)

3.5.1 Design-Parameter Calculation

The main objective of the amplifier is to swap the charge from the input capacitor to theoutput capacitor when the circuit is clocked. The bandwidth of the amplifier has be large

52 3.5 Amplifier

enough to charge the load-capacitance to a level that meets the precision-requirements. Itcan be calculated with help of the settling time, which is the time during which the samplecapacitor Cs is connected to the input of the amplifier:

Tsettl = Tclock/2− Tnovl − Tdelay (3.38)

The precision of the settling is determined by the specified DR of the entire converter.In order to achieve it, the noise contribution of the amplifiers must not exceed LSB/2. Thesettling error can be regarded as noise and like any noise in the loop, it is filtered with thecoefficients that have been computed in eq. 3.16. A local ENOB can be calculated for everyamplifier-output with these coefficients F :

ENOBloc = ENOBsys + log2(F ) (3.39)

With the exponential formula for the linear settling process, the required τ can now bedetermined, which guarantees a sufficient settling:

vout

vin= 1− e

Tsettlτ = 1− 1

2 · 2ENOBloc(3.40)

τ =Tsettl

ln (2) (ENOBloc + 1)(3.41)

The bandwidth and the transconductance of the amplifier can now easily be calculated:

fBW =1

2πτ(3.42)

gm =Csettl

τ(3.43)

Csettl is the effective capacitance seen by the amplifier during the charging process. Itcan be calculated with the model in fig. 3.24, that was derived in [Bal04].

Cgs Cds

Id(s) = gm · Vg(s)Vg(s) Vd(s)Vii(s)CfCs

Co

Figure 3.24: Equivalent circuit during the settling-phase of the amplifier

The settling capacitance is given by:

Csettl =Cs · (Co + Cf) + Cf · Co + Cgs · (Co + Cf)

Cf(3.44)

A high gm can efficiently be achieved, if the input diff-pair is operated in moderate-inversion. Given the thermal voltage VT = kbT

q and the process-dependant factor n =Cox+Cjs

Cox, which can be found among others in [Pau01], the DC current for the calculated

gm is found to be:

Id = gmnVT (3.45)Ib = 2 · Id = 2 · gmnVT (3.46)

3.5.2 Main Amplifier Design 53

Id is the minimum current to load Csettl in the given time. Since both amplifier brancheshave Csettl connected to them, Ib must deliver twice this current. In these calculations,slewing was not discussed, because it is not an issue for such small voltage steps. If amplifierswith larger swings are employed, a more detailed calculation considering slewing is presentedin app. D.

Results

This calculation has to be done not only for every amplifier, but also for every standardwhich leads to different values for the same parameter. Since all standards have to befulfilled, the worst-case value has to be chosen. Some parameters depend on the devicecurrent, so they first have to be referred to a common current before the choice can bemade. Tab. 3.11 shows the resulting parameter values for the presented design.

Table 3.11: Amplifier design-parametersEntity Id [µA] gm [mS] SR [V/ns] UGBW [MHz]

Amplifier 1 2450 19.1 2.0 986Amplifier 2 1247 9.7 1.4 785Amplifier 3 589 4.6 0.7 623Amplifier 4 2137 16.6 4.0 618

3.5.2 Main Amplifier Design

The transconductance of the entire amplifier gm is given by the transconductance of theinput transistor. The current was increased by 25% compared to the calculations to havea safety-margin for process and temperature variations. The latter is important, because,according to eq. 3.45, gm linearly depends on the thermal voltage and therefore on theabsolute temperature. Transistor M1 is copied m = 30 times to multiply the low chip-levelreference-current of Iref = 25µA to a total of Ib = 750µA.

To set the remaining operating points, a few concepts have to be considered. TransistorM1 acts as a current mirror and should therefore have a high rout to be able to deliver aconstant current even if its drain-source voltage varies. Because the headroom is limited,a low vdsat has to be used.

As stated in sec. 3.5.1, the input common-mode is set to a voltage in the weak-inversionregion of the input transistor M2. Although a higher gain would result from long devices,the capacitance of the input-transistors has to be kept small in order not to increase theparasitics too much. The transistor has therefore almost minimum length and the gain isincreased later with the regulating amplifiers instead.

The cascoded current-mirrors M4,5 are connected in parallel with the input diff-pair.Hence, their output resistance has to be at least as large as the output resistance of theinput-cascode in order not to degrade the gain too much.

Fig. 3.25 shows the schematic diagram of the main amplifier for the third integratorstage with its operating points and transistor dimensions. Since the Ib-currents from thecalculation are almost integer multiples of 600µA, the same amplifier can basically be usedin all 4 integrators. E.g., the first amplifier needs 2450.33µA≈ 4 · 600µA. With a totalnumber of m = 4 · 30 = 120 parallel devices in M1, the total calculated current with a 25%margin is achieved.

54 3.5 Amplifier

800mV

900mV

575mV

600mV

300mV

200mV

300mV

900mV

675mV

500mV

200mV

300mV

1.2V

gm = 9.5mS

gds = 261µS

vdsat = 123mV

Vbcp

Iref

Vin+ Vin−

Vout− Vout+

vcom

,in

vcom

,ou

t

Id = 375µA

I = 25µA

- -

CMFB

W4 = 11.5µm

L4 = 180nm

m = 15

W5 = 6.8µm

L5 = 600nm

m = 15

W4

L4

W3

L3

W3 = 2.85µm

L3 = 180nm

m = 15

W1 = 5.4µm

L1 = 600nm

m = 30

W2

L2

W1

L1

gm = 6.2mS

gds = 1.2mS

vdsat = 80mV

gm = 5.7mS

gds = 337µS

vdsat = 91mV

gm = 6.6mS

gds = 350µS

vdsat = 92mV

gm = 3.7mS

gds = 75µS

vdsat = 193mV

W2 = 4.55µm

L2 = 160nm

m = 15

W5

L5

W2

L2

W4

L4

W5

L5

W4

L4

Figure 3.25: Main amplifier schematic of the 3rd integrator

3.5.3 Regulating Amplifier Design

The additional gain from the regulating amplifiers boosts the main amplifier gain. Since nodifferential amplifier is needed for this purpose, a single-ended telescopic cascode-amplifieris used.

The speed-requirements for the regulating amplifiers are not very high. In fact, systeminstability can occur if they are too fast. A detailed analysis can be found in [KB90].The core statement of the analysis is to choose the unity-gain bandwidth for the regulatingamplifier between the corner-frequency and the unity-gain bandwidth of the main amplifier:

ωmain,3dB < ωreg,UGBW < ωmain,UGBW (3.47)

This can also be seen in the Bode-plot of the implemented regulating amplifier in fig. 3.26.The low bandwidth also reduces the required amplifier current, which is a convenient side-effect. In this design, the main amplifier current is chosen 15× higher than the regulatingamplifier current. High gain is mainly achieved by drawing long transistors to get a highrout. The n-side and p-side amplifiers are shown in fig. 3.27 and fig. 3.28.

3.5.4 Common-Mode Feedback

In a differential amplifier, the output impedance is very high, which allows the output-voltage to drift. To prevent this effect, a common-mode feedback circuit is employed tosense the output common-mode and apply a regulative voltage to either the branch current-sources M5 or the base current-source M1. In the circuit in fig. 3.29, the target voltage

3.5.4 Common-Mode Feedback 55

102

104

106

108

1010

−40

−20

0

20

40

60

80

100

120Bode−Plot

frequency [Hz]

gain

[dB

]

Main amplifiern−Boosterp−Booster

ωreg,UGBW

ωmain,UGBW

ωmain,3dB

Figure 3.26: Magnitudes of the regulating and the main amplifier

difference Vtar = Vref−Vb between a reference voltage Vref and the designed bias-voltage Vb

is controled. The charges during ϕ2 are:

2Q1 + Q2+ + Q2− = 2C1Vtar + C2(vin+ − vout) + C2(vin- − vout) (3.48)

Vref

Vb

vin+ vin−

Vout

ϕ2

ϕ1

C2

ϕ2

ϕ2ϕ2

ϕ1

ϕ1

ϕ1

C2 = C1C1 = 350fF C1

Figure 3.29: Common-mode feedback circuit

Then, in ϕ1, the inner and outer capacitors are connected between the differential inputnodes and the output. Assuming that the input load is much higher than the output load(in fact, the CMFB-input is the main-amplifier output with a large capacitive load and theCMFB-output is the main-amplifier M1 transistor), the input can be replaced by a voltagesource. The output voltage in the next time-step voutN is then:

2Q1 + Q2+ + Q2− = (C1 + C2) ((vin+ − voutN) + (vin- − voutN)) (3.49)

voutN =C2

C1 + C2vout +

C1

C1 + C2

(vin+ + vin-

2− Vtar

)(3.50)

Now, if the common-mode is increased, voutN will be increased, too. The increase rate isdetermined by the ratio of C1 and C2. From the main amplifier’s point of view, the outputcommon-mode is in feedback with the base-transistor. This feedback system is subject tostability issues, that have been discussed in detail in [OC90]. The essence is that the loopgain should be as high as possible to assure an accurate common-mode. On the other hand,the bandwidth has to be high enough to suppress the highest frequency disturbances.

56 3.5 Amplifier

800mV

575mV

500mV

420mV

200mV

300mV

140fF

Vout+

Vin+ Vin−

900mV

1.2V

Vout−

I = 25µA

W4

L4

W1 = 5.42µm

L1 = 600nm

W2

L2

W1

L1

W2 = 26µm

L2 = 600nm

W5

L5

W4

L4

W5

L5

Transistors M4 and M5 have the same

size as M4 and M5 in the main amplifier.

Figure 3.27: Regulating amplifier (n-side)

900mV

575mV

675mV

600mV

420mV

200mV

300mV

200fF

Vout− Vout+

Vin+ Vin−

900mV

1.2V

I = 25µA

W4

L4

W3 = 26.9µm

L3 = 600nm

W2

L2

W1

L1

W4 = 24.3µm

L4 = 600nm

W3

L3

Transistors M1 and M2 have the same size

as M1 and M2 in the main amplifier.

W2

L2

W1

L1

Figure 3.28: Regulating amplifier (p-side)

3.5.5 Amplifier Bias-Circuit 57

3.5.5 Amplifier Bias-Circuit

The amplifier bias-circuit is responsible for distributing the chip reference currents tothe different amplifiers and to generate the cascode-voltages, the input- and the output-common-mode voltages. One crucial point is that the generated voltages have to scale withthe different reference currents applied for the different standards. One has to guarantee,that for all standards, the transistors are operated in saturation.

M11

W1/L1

M111

W1/L1

M112

W1/L1

M11m

W1/L1

M23

A · W2/L2

M13

A · W1/L1

M23

W2/L2

M13

W1/L1

M22

W2/L2

Ib Ib Ib A · Ib

vb2

vb1

vb2

Figure 3.30: vdsat asserting bias-circuit

Fig. 3.30 shows the circuit, that is used to keep the base transistors of the amplifiers insaturation for all bias currents. Using standard transistor equations, the following formulawas derived in [Mur]:

VDS13

VDSAT13=

21m

(1 +

√1 + 2m + 4m V∆t

VDS11x

) (3.51)

≈ 2m

1 +√

1 + 2m(3.52)

To be on the safe side, VDS of the transistor was decided to be at least 50% higher thanVDSAT, therefore m = 3 was used in the design which yields a ratio of

VDS13

VDSAT13

∣∣∣∣m=3

≈ 1.65 (3.53)

The transistors M11x and M13 have the same size as the base transistor in the mainamplifier, M23 is equally sized as the cascode transistor in the amplifier. The m = 3transistors M11x can be replaced by one longer transistor with the length of 3× L1.

The generated cascode-voltages are constant and can be distributed over the chip tothe various amplifiers and there be locally supported by large capacitors. As long as itis constant, the precise DC voltage is not so important. This is not true for the basetransistors whose bias voltage is generated by local current-mirrors.

The current consumption of the bias circuit mainly depends on the matching requirementsand the minimum power-up time. With given transistor sizes of the main amplifier, thebias-circuit can use transistors with same lengths but smaller widths. With smaller devices,

58 3.5 Amplifier

matching problems start showing up. With many cascode transistor-gates connected overlong distances to the bias-circuit, it also takes more time to charge this large capacitiveload with the resulting, smaller current.

Reference current input p-side Stabilization n-side Stabilization

Iref

W3 = 11.5µm

L3 = 180nm

W4

3 · L4

W4 = 6.8µm

L4 = 600nm

W4

L4

W4

L4

W4

L4

W4

L4

W3

L3

W3

L3

W3

L3

W3

L3

W2

L2

W1

L1

W2 = 2.85µm

L2 = 180nm

W1 = 5.4µm

L1 = 600nm

W2

L2

W2

L2

W2

L2

W2

L2

W2

L2

W1

L1

W1

L1

W1

L1

W1

L1

Vbcp

Vbp

Vbcn

Vbn

Vrefcn

Vrefn

Vrefcn

Vrefn

Vrefcn

Vrefn

Vbcp Vbcp Vbcp

Vbp VbpVbp

Figure 3.31: n-side and p-side of the bias-circuit

The circuit is used both on the n-side and the p-side. On the p-side, complementarydevices have to be used, of course. Both implemented sides of the bias-circuit togetherwith their dimensioning are shown in fig. 3.31.

The scalable input common-mode is realized with a diode-connected cascode. The tran-sistors are designed to scale together with the remaining operating points when the currentis changed. The output common-mode is implemented with a self-biased circuit that pro-vides a voltage around Vdd/2.

Since the Σ∆-modulator is fully differential, the common-mode should not be loaded, sothe current can be kept reasonably small. These circuits are presented in fig. 3.32.

3.5.6 Overall Amplifier Performance

The Bode-plot of the entire amplifier in fig. 3.33 shows, that with the regulating amplifiers,a gain of almost 100dB is achieved with enough phase margin.

In fig. 3.34, the gain is plotted as a function of the output voltage for the WLAN n case.The required output swing of 350mV lies in a region, where the gain is very linear. The3dB reduction does not occur before a swing greater than 400mV.

The settling behavior with the WLAN n options is shown in fig. 3.35. The settling timeof Tsettl = 1.46ns is pointed out with dashed lines. The plot shows the step-response to a20mV input-step, with vout,∞ = vin ·Cs/Cf = 17.5mV. The relative difference of the outputsignal to the end-value is shown in the lower plot logarithmically. According to eq. 3.40,the amplifier has to settle to (1 + 10.3 + log(0.2)) = 9bit =dB 55.8dB and effectively settlesto 20 log(εset) = 57dB.

3.5.6 Overall Amplifier Performance 59

vcom,in

W2 = 20.77µm

L2 = 400nm

W1 = 3.23µm

L1 = 600nm

W4

L4

W5

L5

Transistors M4 and M5 have the same

size as M4 and M5 in the main amplifier.

800mV

350mV

150mV

900mV

675mV

1.2mV

vcom,in

W1 = 2.02µm

L1 = 1µm

600mV

W2 = 6.92µm

L2 = 1µm

Figure 3.32: Generation of the common-mode and local copies of the current mirror

102

104

106

108

1010

−40

−20

0

20

40

60

80

100

120Bode−Plot

frequency [Hz]

gain

[dB

]

DC−gain: 97.36dB

UGBW: 1.32GHz

102

104

106

108

1010

−300

−250

−200

−150

−100

−50

0

50

frequency [Hz]

phas

e [°

]

Phase margin: 77.4°

Figure 3.33: Bode-plot of the amplifier

60 3.5 Amplifier

−0.8 −0.6 −0.4 −0.2 0 0.2 0.4 0.6 0.820

30

40

50

60

70

80

90

100

110Gain−Variation of the Amplifier

output voltage [V]

gain

[dB

]

Figure 3.34: Gain reduction of the amplifier at higher output voltages

0 2 4 6 8 10

x 10−9

−5

0

5

10

15

20x 10

−3Settling Curve for v

in=20mV, C

s/C

f=7/8

time [ns]

outp

ut s

igna

l [m

V]

0 2 4 6 8 10

x 10−9

−8

−7

−6

−5

−4

−3

−2

−1

0

1

Settling Error for vin

=20mV, Cs/C

f=7/8

time [ns]

log(

ε set)

Figure 3.35: Settling error of the amplifier

3.6 Input-Stage 61

3.6 Input-Stage

To acquire the quantization error at the modulator-input, the digital output value needs tobe converted back into an analog signal and has then to be subtracted from the input signal.Both operations are elegantly combined in the input-stage. In the following sections, thesub-circuits are shown for a single-ended design. In a differential design, inverse signalinghas to be applied at the negative branch.

3.6.1 DAC

+

-

vcom,in

vin

vref−vref+vref−vref+ vref−vref+

ϕ2

ϕ1ϕ1

ϕ1

ϕ1

ϕ2

SWi+

DACi

SWi−DACi

SW

i+

SW

i−

SW

n+

SW

n−

SW

1+

SW

1−

CDAC

CDAC

CDAC

Figure 3.36: D/A-conversion with a passive averaging unit

The (n+1)-level-DAC is implemented with n capacitors that form a charge-redistributionswitched-capacitor DAC. As shown in fig. 3.36, during ϕ1, the input-voltage with thecommon-mode vcom,out of the amplifier output2 is sampled on the input-capacitors thatare connected in parallel towards the amplifier input common-mode vcom,in. A charge ofnCDAC(vin−vcom,in) is loaded on the capacitors. In ϕ2, the parallel capacitors are connectedtogether between the amplifier input and on the other side separately to the correspondingDAC reference levels vref+ or vref-. For m DAC high-bits, the charge-equation, solved forthe resulting voltage vres at the output of an inverting amplifier, is:

nCDACvin = mCDAC(vref+ − vres) + (n−m)CDAC(vref- − vres) (3.54)

vres = vin −(m

nvref+ +

(1− m

n

)vref-

)(3.55)

The choice of the reference levels is determined by the specified input voltage swing. Itis specific for the different standards as described in tab. 3.5. For the chosen input-swingvs, it can easily be verified, that vref+ = vcom,out + vs

2 and vref- = vcom,out − vs2 yields the

correct result.

3.6.2 Dynamic Element Matching

The digital quantizer output comes in the so called thermometric code. Like in a mercury-thermometer, a certain comparator can only output a high-bit if all comparators below arehigh, too. Like in any other DAC, the problem in this DAC-architecture combined with the

2The amplifier output common-mode of Vdd/2 is chosen as the Σ∆-input common mode because it allowsthe high swing necessary for the operation.

62 3.6 Input-Stage

thermometric quantizer output is, that a mismatch in the capacitors leads to a systematicerror of the D/A-conversion.

To solve this problem, dynamic element matching (DEM) is applied, which pseudo-randomly interlinks a comparator/DAC-bit pair following a certain algorithm. Accordingto a prior thesis [Jia06], the data weighting averaging algorithm (DWA) was chosen toimplement the DEM. Functionally, it transforms the systematic error into an offset-freerandom DAC noise signal, distributes the DAC noise power from the harmonics over thespectrum and performs a shift of the DAC noise out of the signal band.

The algorithm basically stores the position of the first selectable DAC-high-bit Ppi and,starting from this bit, activates the following h DAC-switches, when h is the number ofquantizer-high-bits. Logarithmic bit-shifters are commonly employed for this mechanism.In this thesis, an approach with digital logic is suggested, that takes advantage of the specialcoding of the quantizer-output.

7

1

0

111

00

Pp0 = 1

Pn4 = 1 DAC0−3 = 1

QuantizerxDO DAC0:6

DAC4−6 = 0

Figure 3.37: DWA algorithm

The illustration of the DWA in fig. 3.37 shows a state of the DWA with the positionpointer at the first bit and a quantizer output of four high-bits. Depending on the quantizeroutput, two things need to be computed:

. The next position of the pointer Pni, which is a register state and may take some time,and

. the DAC-switch-setting DACi, which needs to be as fast as possible to prevent reducingthe amplifier’s settling time too much.

An analysis for the third DAC-bit DAC2 in tab. 3.12 points out the conditions that haveto be met in order that DAC2 = 1 in fig. 3.36:

Table 3.12: Analysis for DAC-Bit DAC2

Present pointer Quantizer outputPp0 Th2, Th3, Th4, Th5, Th6

Pp1 Th1, Th2, Th3, Th4, Th5, Th6

Pp2 Th0, Th1, Th2, Th3, Th4, Th5, Th6

Pp3 Th6

Pp4 Th5, Th6

Pp5 Th4, Th5, Th6

Pp6 Th3, Th4, Th5, Th6

3.6.2 Dynamic Element Matching 63

Since the quantizer has a thermometric output, the conditions for the quantizer-outputprinted in bold letters are sufficient for the decision. The logic equation for bit 3 is accordingto de Morgan’s law:

DAC2 = (Pp0 ∩ Th2) ∪ (Pp1 ∩ Th1) ∪ . . . ∪ (Pp6 ∩ Th3) (3.56)

= (Pp0 ∪ Th2) ∩ (Pp1 ∪ Th1) ∩ . . . ∩ (Pp6 ∪ Th3) (3.57)

In hardware, this can be implemented with 2-input NORs and 3-input NANDs. If theinverted pointer is stored in a register, too, one gate-cascade can be saved, because thethermometric output from the comparator-latch comes inverted and non-inverted anyway.Thus, for a n-output quantizer, the longest path leads through a cascade of 1 + dlog3(n)egates.

The next pointer position is calculated very similarly. The difference to tab. 3.12 is,that only one pointer bit, the one after the last thermometric quantizer-bit shifted by thecurrent pointer position, can be active at once. To determine this bit, tab. 3.13 is of gooduse:

Table 3.13: Analysis for next pointer position Pn2

Active pointer Quantizer outputPp0 Th1 ∩ Th2

Pp1 Th0 ∩ Th1

Pp2 Th6 ∪ Th0

Pp3 Th5 ∩ Th6

Pp4 Th4 ∩ Th5

Pp5 Th3 ∩ Th4

Pp6 Th2 ∩ Th3

The exception printed in bold letters accounts for the case, that the pointer position staysthe same, if either all quantizer bits are set, or none. The logic function can be assembledas in the DAC-bit case.

The general form of the logic equations is given below. It can be coded in a HDL tosynthesize the DEM-block. i denotes the coded bit, and n the number of thermometricquantizer-bits. All calculations are modulo n:

DACi =n−1⋃k=0

(Ppi+k ∩ Th−k

)(3.58)

Pni =(Ppi ∩ (Thn ∪ Th0)

)∪

n−1⋃k=1

(Ppi+k ∩ Th−(k+1) ∩ Th−k

)(3.59)

64 3.7 Bootstrap Switch

3.7 Bootstrap Switch

In Σ∆-modulators the input switches must be linear because otherwise higher harmonicsare introduced into the circuit which leads to distortion of the input signal (see fig. 3.38). Aswitch is linear if its on-resistance does not depend on the input signal level. But switchesthat are designed as t-gates or as single NMOS or PMOS have the disadvantage that theiron-resistance depends on the input signal level. This behavior is especially harmful forhigh swing input signals. Therefore, a special switch is needed that keeps its on-resistanceconstant even for high changes of the input signal. A possible solution is a bootstrapswitch. The working principle and implementation of the bootstrap which is presented inthis section is based on [AG98] and [YNI91].

3.7.1 Working Principle

The working principle of the bootstrap switch is shown in fig. 3.39(a). All switches areassumed to be active high. The basic idea is to keep the gate-source voltage vgs of theswitching transistor constant at a voltage difference of ∆Vb = Vdd−Vss in on-mode. There-fore, the on-resistance is also kept constant and hence the switch behaves linearly. Theboosting of vgs is achieved by a capacitance C3 that is precharged in the off-mode to ∆Vb.

In the off-mode, when the clock signal is low, switch F is closed and sets the signal switchto ground. Therefore, the main switch E is closed. At the same time, the switches C andD are open and the switches of unit B are closed for charging the capacitance C3 up toapproximately ∆Vb. The open switches C and D avoid the discharging of the capacitanceC3. Unit A is responsible for shifting its input signal from Vdd to 2Vdd. Therefore, theupper switch of unit B experiences a control voltage that is approximately at 2Vdd. Thismethod is necessary in order to charge the capacitance C3 up to approximately ∆Vb.

In the on-mode, the capacitance C3 acts as battery for the gate source voltage vgs of theswitch E transistor. Therefore, the switches C and D are closed and switch F is open. Theswitches of the unit B are open in order to avoid the decharging of the capacitance C3.

3.7.2 Design Considerations

The implementation of the bootstrap switch is shown in fig. 3.39(b). The circuit wasdesigned in order to minimize the size of the capacitors as well as the transistors. Themotivation was to keep the circuit, the currents and the parasitic capacitances small.

Main Switch

The main switch consists of the NMOS M1. As there are seven input switches for eachDAC capacitor (with a capacitance of 140fF) that must be switched simultaneously, sevensingle NMOSs are controlled by only one bootstrap circuit. The size of M1 was chosen inorder to achieve an on-resistance Ron so that the linear settling time is fast enough (seefig. 3.40(a)).

3.7.2 Design Considerations 65

0 20 40 60 80 100 120 140 160−180

−160

−140

−120

−100

−80

−60

−40

−20

0

N−Switch

frequency [MHz]

ampl

itude

[dB

]

(a) N-Switch

0 20 40 60 80 100 120 140 160 180−180

−160

−140

−120

−100

−80

−60

−40

−20

0

P−Switch

frequency [MHz]

ampl

itude

[V]

(b) P-Switch

0 20 40 60 80 100 120 140 160−180

−160

−140

−120

−100

−80

−60

−40

−20

0

T−Gate−Switch

frequency [MHz]

ampl

itude

[dB

]

(c) T-Gate-Switch

0 20 40 60 80 100 120 140 160−180

−160

−140

−120

−100

−80

−60

−40

−20

0

Bootstrap Switch

frequency [MHz]

ampl

itude

[dB

]

(d) Bootstrap-Switch

Figure 3.38: Comparison of the linearity of switches: A sine wave with an amplitude of350mV at a DC voltage of 600mV and a frequency of 20MHz is fed to the inputof a n-switch, a p-switch, a t-gate and a bootstrap switch that is connectedto a capacitance of 1.19pF which is precharged at 250mV. The switches wereswitched on and off with a clock frequency of 320MHz for the first 16 cyclesand afterwards set to constantly on. The spectra were generated using a Kaiserwindow with a width of 20. The plots show that the third-order harmonicsare suppressed by 100dB for the bootstrap switch, but only by 20dB / 25dB /50dB for a n-switch / p-switch / t-gate-switch. (The second-order harmonicscancel each other out in differential signaling.)

66 3.7 Bootstrap Switch

Parasitic Capacitances

The key idea of the bootstrap is to keep the gate-source voltage vgs of the switch M1

constantly at ∆Vb. However, parasitic capacitances Cp leads to a lower voltage differenceas the following formula shows (see [AG98]):

vgs =C3

C3 + Cp︸ ︷︷ ︸f

·∆Vb (3.60)

Therefore, in order to keep vgs at ∆Vb, the parasitic capacitance Cp must be small incomparison to the capacitance C3. The factor f was determined by simulations. It isapproximately 0.943. As C3 was chosen to be 600fF, Cp is 36fF.

Voltages at 2Vdd

Unit A generates a control voltage that lies approximately at 2Vdd. Fig. 3.39(b) shows theimplementation of this unit. The capacitors C1 and C2 are charged from cycle to cycle.While they are charged, the voltage drop ∆VC1,2 increases and hence the transistors M11

and M12 deliver less and less current because they are put further into cutoff region. Finally,the capacitors are charged up to approximately Vdd and therefore the control signals v1 andv2 reaches approximately 2Vdd (see also fig. 3.40(c)).

3.7.3 Simulations

The bootstrap switch was simulated as follows:. input signal: sine wave at 600mV DC, amplitude: 350mV, frequency: 20MHz. switch signal: clock with 320MHz. bias voltages: Vdd = 1.2V, Vss = 0V

Fig. 3.40(a) shows the input voltage vi and the gate voltage vg. It can be observed thatthe gate voltage vg follows the input voltage vi. vg is approximately vi + Vdd. Fig. 3.40(b)shows the voltage difference ∆vC3 over the capacitance C3. It is approximately at Vdd.Fig. 3.40(c) shows the voltages v1 and v2 of unit A. They toggle from Vdd to 2Vdd.

3.7.3 Simulations 67

CLK

xC

B

vout

vin

sCLKxC CLKxCB

CLKxCB

s

voutvin

C3

A

B

C

D

E

F

CLKxC

Working Principle

switch : ON

vin vout

vin vout

switch

switch : OFF

(a) Basic scheme

CLKxC

CLK

xC

B

vout

vin

C1,2 = 100fF

sCLKxC CLKxCB

CLKxCB

s

voutvin

C3

=600fF

M1M2

M3

M4 M5

M6

M7 M8

M9

M10

M11 M12

A

B

C

D

E

F

\footnotesizeF

v1 v2

∆vC3

vg

vi

vh

×2

×22

w = 2µm

l = 60nm

w = 120nm

l = 60nmw = 2µm

l = 60nm

w = 10µm

l = 60nm

N = 7

Ron = 18.89Ω

w = 4µm

l = 60nm

w = 120nm

l = 60nm

w = 4µm

l = 60nm

w = 4µm

l = 60nm

w = 120nm

l = 60nm

w = 10µm

l = 60nm

(b) Implementation

Figure 3.39: Working principle and implementation of the bootstrap switch

68 3.7 Bootstrap Switch

0 5 10 15 20 25 30 35 40 45 50−0.5

0

0.5

1

1.5

2

time [ns]

ampl

itude

[V]

Voltages vg and v

i

Voltage v

i

Voltage vg

(a) Voltages vin and vg

0 5 10 15 20 25 30 35 40 45 500

0.2

0.4

0.6

0.8

1

1.2

1.4

Voltage ∆VC

3

time [ns]

ampl

itude

[V]

(b) Voltage difference ∆vC3

0 5 10 15 20 250

1

2

3

time [ns]

ampl

itude

[V]

Voltage v1

0 5 10 15 20 250

1

2

3

time [ns]

ampl

itude

[V]

Voltage v2

0 5 10 15 20 250

1

2

3

time [ns]

ampl

itude

[V]

Clock CLKxC

(c) Voltages v1 and v2 of unit A

Figure 3.40: Behavior of the bootstrap circuit

3.8 Clock Generator 69

3.8 Clock Generator

3.8.1 Timing

Fig. 3.41 shows the timing scheme for the clocking scheme with its derived two non-overlapped clock signals. Further, the following timing parameters are drawn:

. clock rise and fall time: Trise, Tfall

. clock period: Tclk

. clock phase time: Tph

. non-overlapped time: Tno

As the clock has a finite rise and fall time (here Trise,fall ≈ 20ps), the switches do not closeor open instantaneously. For avoiding charge-sharing between capacitors when a switch isabout to close and another is about to open, a non-overlapped time is necessary. Further,as the clock is exposed to skew3 and jitter4, an additional margin is needed. Therefore, forthe non-overlapped time Tno and for the clock phase time Tph hold:

Tno ≥ Trise + Tfall + max(Tskew, Tjitter) (3.61)

Tph =Tclk

2− Tno (3.62)

The non-overlapped time Tno was set to 100ps which gives a head room of about 60ps forclock skew and clock jitter.

Trise TfallTclk

CLKxC

Phi1xC

Phi2xC

Tno Tph

Figure 3.41: Timing diagram for the clock signals: For WLAN n the clock period Tclk is3.125ns. With a non-overlapped time of Tno = 100ps and a rise and fall timeof Trise,fall = 20ps, the clock phase time Tph is 1.4625ns.

3Clock skew is the maximal difference in path delays between a clock input and its final destinations.4Clock jitter is a parasitic effect that leads to an arbitrary difference in path delays from a clock input to

a certain destination between subsequent clock periods.

70 3.8 Clock Generator

3.8.2 Implementation

The clock generator used in this design is a standard non-overlapping clock generator. Thecircuit realization is shown in fig. 3.42.

CLKxCI

CLKxCBI

Phi1xCO

Phi1xCBO

Phi2xCBO

Phi2xCO

Phi2DxCO

Phi1DxCO

CLKxCI

CLKxCBI

Phi1xCO

Phi1xCBO

Phi2xCBO

Phi2xCO

Phi2DxCO

Phi1DxCO

×4

×4

×4 ×4

×4

×4×4

×4×4×4

×4

×4

×4

×4

×4

×4

×9

×9

×9

×9

×13

×13

×13

×13

×18

×18

×18

×18

×22

×22

×22

×22

×27

×27

×27

×27

×27

×27

×4

×4

Figure 3.42: Clock generator

4Results

In fig. 4.1, the implemented Σ∆-modulator is compared in terms of the DR and the band-width to other Σ∆-modulators that were published in [ISS]. The diagram shows that thedifferent standards of the designed Σ∆-modulator cover a wide bandwidth range in theupper middle part of the diagram. It also shows that there are only a few Σ∆-modulatorsthat have a maximal bandwidth of 20MHz. Further, it should be noticed that many of thechosen Σ∆-modulators are single-standard designs.

100kHz 1MHz 10MHz50

55

60

65

70

75

80

85

90

95

100

Bandwidth

DR

[dB

]

Comparison of Implemented Σ∆−Modulators

DT Σ∆−ModulatorCT Σ∆−Modulatorimplemented Σ∆−Modulator

Tim Piessens650nm, 5V

Yves Geerts650nm CMOS, 5V

Lucien J. Breems90nm CMOS, 1.2V

Yves Geerts650nm, 5V

Figure 4.1: The implemented Σ∆-modulator in comparison to others (2007) [ISS]

71

72 4.1 Dynamic Performance

4.1 Dynamic Performance

The output spectra of the Σ∆-modulator are shown in fig. 4.2-4.5 for each standard. Thesimulation was carried out with a sine input wave with an amplitude of 0.5FS. The signalfrequency was 0.75fb for GSM-EDGE and 0.25fb for all other standards. Tab. 4.1 show theresults for the same simulations with an amplitude of 0.8FS.

Thermal noise was not simulated in the circuit simulator. The calculated noise floor isindicated with the red line in the spectrum and allows an estimation of the effective circuitperformance.

Tab. 4.1 and the spectra show, that for all standards, the required DRs, are fulfilled.

Table 4.1: DR and SNDR for an input amplitude of 0.8FSStandard required DR [dB] DR [dB] SNDR [dB]GSM-EDGE 88 96 97UMTS 79 90 84WLAN a/b/g 71 78 75WLAN n 64 64 62

10−2

10−1

100

101

−200

−180

−160

−140

−120

−100

−80

−60

−40

−20

0

GSM−EDGE, fs=26MHz, OSR=130

Frequency [MHz]

Mag

nitu

de [d

BF

S]

SNR = 100.35 dB

SNDR = 100.35 dB

THD = −Inf dB

DR = 103.62 dB

fsig = 0.08 MHz

Psig = −9.03 dB

= −6.03 dBFS

8192 FFT

Figure 4.2: Analyzed spectrum with an input amplitude of 0.5FS (GSM-EDGE)

4.1 Dynamic Performance 73

10−2

10−1

100

101

−200

−180

−160

−140

−120

−100

−80

−60

−40

−20

0

UMTS

Frequency [MHz]

Mag

nitu

de [d

BF

S]

SNR = 82.20 dB

SNDR = 81.49 dB

THD = −89.72 dB

DR = 87.29 dB

fsig = 0.48 MHz

Psig = −9.02 dB

= −6.02 dBFS

8192 FFT

Figure 4.3: Analyzed spectrum with an input amplitude of 0.5FS (UMTS)

10−1

100

101

102

−200

−180

−160

−140

−120

−100

−80

−60

−40

−20

0

WLAN IEEE 802.11a/b/g

Frequency [MHz]

Mag

nitu

de [d

BF

S]

SNR = 73.69 dB

SNDR = 72.82 dB

THD = −80.19 dB

DR = 79.00 dB

fsig = 2.49 MHz

Psig = −9.00 dB

= −6.00 dBFS

8192 FFT

Figure 4.4: Analyzed spectrum with an input amplitude of 0.5FS (WLAN a/b/g)

74 4.2 Temperature and Process Variations

10−1

100

101

102

−200

−180

−160

−140

−120

−100

−80

−60

−40

−20

0

WLAN IEEE 802.11n

Frequency [MHz]

Mag

nitu

de [d

BF

S]

SNR = 59.63 dB

SNDR = 59.12 dB

THD = −68.69 dB

DR = 65.16 dB

fsig = 5.00 MHz

Psig = −8.97 dB

= −5.97 dBFS

8192 FFT

Figure 4.5: Analyzed spectrum with an input amplitude of 0.5FS (WLAN n)

4.2 Temperature and Process Variations

To confirm stable operation under different operating conditions, the circuit was simulatedin a temperature range from 0C-100C. The simulation results of WLAN n are shown infig. 4.6.

A corner analysis was also performed on the circuit with the WLAN n settings. The fastand the slow corners are simulated for 3σ-process variations. The results are summarizedin tab. 4.2.

Table 4.2: DR and SNDR for different corners (WLAN n)Corner DR [dB] SNDR [dB]Fast Corner 61.88 55.98Typical Corner 65.16 59.12Slow Corner 62.28 56.49

In the Monte Carlo simulation, the device-parameters were randomly varied with a 3σ-process variation. The statistics are carried out for 75 simulation runs. With these extremeprocess variations, 85.3% of the circuits still operated stable. The mean DR-value of thestable circuits was = 62.9dB with a standard deviation of σ = 2.0. The histogram is shownin fig. 4.7.

4.2 Temperature and Process Variations 75

0 10 20 30 40 50 60 70 80 90 10052

54

56

58

60

62

64

66

Temperature [°C]

DR

, SN

DR

[dB

]

Temperature Variation for WLAN IEEE 802.11n

DRSNDR

Figure 4.6: Temperature variation for WLAN n

10 20 30 40 50 60 700

5

10

15

20

25

DR [dB]

#sim

poi

nts

Monte Carlo Simulation Results

Figure 4.7: Monte carlo simulation results

76 4.3 Total Power Consumption and Conversion Energy

4.3 Total Power Consumption and Conversion Energy

For measuring the total power consumption, the circuit was simulated for each standardwith a sine input wave with an amplitude of 0.5FS. The results are shown in tab. 4.3.

The conversion energy – or figure of merit (FOM) – is defined as the energy that isneeded for the conversion of 2ENOB bits at a conversion rate that is equal to the Nyquistrate 2fb, where fb is the bandwidth for each standard:

Econv =Ptot

2 · fb · 2ENOB(4.1)

The simulation was performed with an ideal voltage buffer circuit for the DAC referencevoltages and with an ideal clock generator. The digital DWA unit was also not included inthe simulation. The result of the simulated power measurement is shown in tab. 4.3.

Table 4.3: Measured power consumption and calculated conversion energy for each standardGSM-EDGE

total power Ptot : 2mWbandwidth fb : 100kHzENOB : 14.3bitsconversion energy Econv : 0.5pJ/conv

UMTStotal power Ptot : 3mWbandwidth fb : 1.92MHzENOB : 12.8bitsconversion energy Econv : 0.1pJ/conv

WLAN a/b/gtotal power Ptot : 10mWbandwidth fb : 10MHzENOB : 11.5bitsconversion energy Econv : 0.2pJ/conv

WLAN ntotal power Ptot : 15mWbandwidth fb : 20MHzENOB : 10.3bitsconversion energy Econv : 0.3pJ/conv

4.4 Summary 77

4.4 Summary

The summarized results are shown in tab. 4.4. Note that the required DR includes thethermal noise, while the simulations do not.

Table 4.4: Summarized resultsProperties GSM-EDGE UMTS WLAN a/b/g WLAN nrequired DR [dB] 88 79 71 64DR [dB] 104 87 79 65SNDR [dB] 100 81 73 59Noise Floor [dB] 97 105 109 111Bandwidth [MHz] 0.1 1.92 10 20Input Stable Range stable up to 0.8FSOperating Condition tested for T = 0 . . . 100C and for different cornersPower Consum. [mW] 2 3 10 15Conv. Energy [pJ/conv] 0.5 0.1 0.2 0.3

78 4.4 Summary

5Conclusion and Outlook

This master thesis demonstrated a working wideband Σ∆-modulator for the cellular stan-dards GSM-EDGE and UMTS as well as for the WLAN standards IEEE 802.11a/b/g withthe proposal draft n. The modulator has a bandwidth that reaches from 100kHz up to20MHz. It has a input stable-range of 0.8FS at a bias voltage of 1.2V. The over-samplingratio varies from 8 to 130, which allows a dynamic range from 65.16dB for the fastest spec-ification (WLAN n) up to 103.62dB for the highest required resolution in the specifications(GSM-EDGE).

First, a new design methodology was developed for the system design, that allows asystem optimization combining the purely analytical approach with simulation results fromthe system. A solution was found, that achieved a high dynamic range and still has a highinput stable-range. It was possible to satisfy the specifications for all standards by usingonly one variable element, namely the resonator capacitor.

The circuit design was done in a state-of-the-art 65nm CMOS technology. Differentcomponents were analyzed and optimized in terms of power consumption, while the overallsystem performance was not declined. Problems with the low supply voltage and short-channel effects, that come along with the technology used, were addressed and successfullymastered.

The simulations of the circuit were performed for different standards under various op-erating conditions and affirmed the stable operation of the circuit for temperatures from0C to 100C and for the 3σ-process corners.

The Σ∆-modulator can compete in every standard with single standard devices that werepublished in ISSCC and JSSC up to the time of writing. In the low-bandwith sector, theresolution is positioned in the upper third, while in the segment of Σ∆-modulators withbandwidths of 20MHz, no discrete-time implementation was found by the authors.

79

80 CHAPTER 5. CONCLUSION AND OUTLOOK

The timespan of the project was too short for carrying out all tasks that would havebeen necessary in order to design a manufacturable chip. Therefore, the following thingsremain to be done:

Design of the voltage reference buffer The voltage reference buffer is used in the DACon the feedback path for delivering reference voltages that are strong enough in orderto supply the input capacitors with enough current for achieving the required settlingaccuracy. The design is additionally complicated by the fact that the reference volt-ages are close to the rail voltages. Therefore, there might be a head room problem forcertain reference buffer circuits. A study on voltage reference buffers can be found in[CY06].

Synthesis of the DWA The DWA unit was designed in VHDL and functionally tested, butit has not yet been sythesized. It has to be integrated into the circuit. The timing ofthe logic approach has to be compared to the timing of the logarithmic bit-shifters.

Clock Generator The clock generator was designed and tested. However, it has not beenintegrated into the circuit yet.

Layout In order to design a manufacturable chip, the layout of the whole circuit must bedrawn.

Further Simulations The integration of the components listed above necessitates furthersimulations of the whole Σ∆-modulator in order to verify their influence on the per-formance. When the layout is drawn, back-annotated simulations are necessary inorder to estimate the performance degradation due to parasitic effects.

Appendix Contents

A Design Flow 83

B Figures of Merit for Describing the Performance of Σ∆-Modulators 89B.1 SNR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89B.2 SQNR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89B.3 SNDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89B.4 THD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90B.5 DR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90B.6 Peak SNDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90B.7 Remarks and Pitfalls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

C Mathematical Reference for certain Σ∆-Architectures 93C.1 4th order Σ∆-modulator with 1 delayed resonator . . . . . . . . . . . . . . 94C.2 4th order Σ∆-modulator with 1 non-delayed resonator . . . . . . . . . . . . 96

D Settling and Slewing Behavior of Amplifiers 99D.1 The Basic Circuit for Amplifier Analysis . . . . . . . . . . . . . . . . . . . . 100D.2 Modeling the Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100D.3 Describing the Linear Settling Behavior . . . . . . . . . . . . . . . . . . . . 101D.4 Describing the Slewing Behavior . . . . . . . . . . . . . . . . . . . . . . . . 103D.5 Adjusting the Settling Bahavior . . . . . . . . . . . . . . . . . . . . . . . . . 104

E The Simulation Framework in Matlab 105E.1 Installation and Run . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105E.2 Development State of the Framework . . . . . . . . . . . . . . . . . . . . . . 106E.3 Using the Framework . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

E.3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106E.3.2 Available Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

F Schematics 109

G List of Abbreviations 117

81

82 Appendix Contents

ADesign Flow

Fig. A.1-A.4 show a possible design flow for a Σ∆-modulator. The design flow can beroughly divided into three major parts:

. system design

. circuit design

. layout designEvery part consists of milestones which act as final points of previous steps. But it is alsothe moment for documenting the steps so far. It is good practice to document the resultsin a notebook or in the form of presentation slides. Such a documentation is not only veryuseful for further design steps, it also helps finding design errors and making older designdecisions traceable.

The design starts with the specification of the circuit that should be implemented. Typ-ical design targets are:

. SNR and SNDR

. DR

. ISRThe next step encompasses the evaluation of possible Σ∆-architectures that can be de-scribed by a signal flow graph (SFG). The signal flow description serves as starting pointfor high-level simulations in Simulink or alike. It is good practice to build a testbench forsimulating and comparing different Σ∆-architectures. In general, there are two approachesfor searching an optimal solution for a given Σ∆-architecture meeting the specified designtargets:

. variation of coefficients (gain-factors) in the time domain

. variation of poles and zeros and hence of the STF and NTF in the Laplace- or z-domainThe description in the Laplace- or z-domain delivers a very compact view of the system.However, as Σ∆-systems are non-linear1, the classical stability theorems cannot be appliedto these systems because these theorems are only valid for linear time-invariant (LTI)systems.

1Σ∆-systems are non-linear because they include a quantizer which is a non-linear component.

83

84 APPENDIX A. DESIGN FLOW

Changing poles and zeros also changes the coefficients of the system. So, meeting therequirements for a single standard with a given pole-zero-configuration does not necessarilymean that the same coefficients are also applicable to another standard. However, it ispossible to elaborate pole-zero-configurations for each standard in order to limit the searchscope for the coefficients.

The other approach is the direct search of the coefficients in the time domain. For ap-plying this method, the search scope must be somehow limited. The pole-zero approachmay serve as preparing method for limiting this search scope.

The second part consists of the circuit design. For designing the circuit properly, designparameters must be calculated. Some important design parameters are:

. amplifiers: bandwidth, bias current, settling or slewing time, gain

. capacitors: minimally allowable size, size, type

. switches: type, size

. quantizer: levels

. comparator: resolution, mismatch, SNDR degradationWhile digital components are described by hardware description languages (HDLs), ana-log components are described by their schematics. However, it is also possible to describeanalog components by ideal models (for example in VHDL-A, Verilog-A, etc.). An idealtestbench serves as starting point for iteratively replacing the remaining ideal models bytheir real counterparts. Such an approach has the advantage, that the location of the errorcan be kept small.

Process and temperature variations make circuit design a delicate task. Circuit designmeans design for manufacturability and therefore circuit simulations have to address theseeffects. The process variations of design parameters (like the size of transistors, etc.) arecharacterized by the fabs and are described by statistical distributions. There are twoapproaches for accounting these process variations.

The first one consists of simulating the circuit with a systematic process error. For exam-ple, all transistors have a lower threshold voltage than they should have. These systematicprocess errors are called process corners; and the simulations corner simulations respec-tively. The other approach is to simulate the circuit for several runs by inserting randomprocess errors. These simulations are called Monte Carlo simulations. For example, acircuit is simulated 50 times by varying randomly the widths of the transistors accordingto a statistical distribution. The temperature variations are addressed by simulating thecircuit at different operating temperatures. In contrast to digital circuits where there arego/no-go tests, analog designs need human inspection of the signals of interest which is avery laborious task.

The final part encompasses the drawing of the layout. Digital components are layoutedautomatically by dedicated layout generation tools. These components are only placed andtheir terminals are connected. Analog components are layouted by hand. The drawn layoutis checked by design rule checks (DRC) to verify that the drawing rules are fulfilled. Thelayout versus schematic (LVS) test is necessary to verify that the drawn layout is identicalto the schematic. An extraction of parasitic capacitances and resistances helps to estimatethe quality of the layout. It also serves as starting point for layout improvements.

85

Milestone 1:

Architectural design fulfilling the proposed design specifications

Design Specifications

for Each Standard

Choosing an

Architecture

Architectural Design

Circuit Design

Are

design specifications

fulfilled?

yes

no

Are there other

architectures?

Possible Design Specifications:

− ISR

− DR

− SNDR

− and othersEvaluation of

Possible Architectures

yes

Optimization of Design Parameters

in the Time−Domain

Pole−Zero Optimization

in the z−Domain

Optimization

Set of Common Design Parameters

for All Standards

Simulation of Each Standard

Analysis of Results

no

Estimation of

Circuit Design Parameters

Milestone 2:

Set of circuit design parameters for all standards

System Design

Figure A.1: Σ∆-design flow, part 1

86 APPENDIX A. DESIGN FLOW

Milestone 3:

Runnable and verified ideal circuit

Implementation of Ideal Circuit Blocks

Using Verilog−A, VHDL−A or Ideal Circuit Elements

Implementation of Runnable

Testbench

Are

the results comparable

to the architectural

simulations?

Simulation of Each Standard

Analysis of Results

Milestone 2:

Set of circuit design parameters for all standards

Debug

yes

no

Architectural Design

Circuit Design

System Design

Figure A.2: Σ∆-design flow, part 2

87

Replacement of an Ideal Circuit Block

By Its Real Counterpart

Milestone 4:

Runnable and verified real circuit

Design for Manufactorability

Temperature Variations:

Simulation at Different

Temperatures

Process Variations:

− Monte Carlo Simulations

− Corner SimulationsAre

the results comparable

to the simulations with the

ideal circuit block?

Debugno

Simulation and Analysis of

Results

yes

Are

all ideal blocks

replaced?

yes

no

Exhaustive Simulations and

Analysis of Results

Are

the results in an

acceptable target

range?

yes

Improvementsno

Milestone 3:

Runnable and verified ideal circuit

Architectural Design

Circuit Design

System Design

Digital Blocks:

Small blocks are implemented by hand.

Medium and large blocks are simulated and

verified in dedicated tools using VHDL or

Verilog.

Figure A.3: Σ∆-design flow, part 3

88 APPENDIX A. DESIGN FLOW

Milestone 4:

Runnable and verified real circuit

Milestone 5:

Verified layout

Hand−Layouting and Placement

of Existing Layout Blocks

Layout Generation

for Digital Blocks

DRC and LVS

Routing

Error? Debugyes

Layout Extraction

of Parasitic Resistances and Capacitances

Architectural Design

Circuit Design

System Design

Final Simulation and

Analysis of Results

Layout

Improvement

Are

the results in an

acceptable target

range?

yes

no

Figure A.4: Σ∆-design flow, part 4

BFigures of Merit for Describing the

Performance of Σ∆-Modulators

B.1 SNR

The signal to noise ratio (SNR) is the ratio of the RMS signal power Ps to the RMS noisepower Pn integrated over the band of interest:

SNR =Ps

PnSNRdB = 10 log10

(Ps

Pn

)(B.1)

B.2 SQNR

The signal to quantization noise ratio (SQNR) is the ratio of the RMS signal power Ps tothe RMS quantization noise power Pq:

SQNR =Ps

PqSQNRdB = 10 log10

(Ps

Pq

)(B.2)

The RMS quantization noise power for a sine input wave can be approximated with whitenoise:

Pq =π2L∆2

12 · (2L + 1) ·OSR2L+1(B.3)

L describes the order of the NTF, OSR represents the oversampling ratio and ∆ is the stepsize of the quantizer.

B.3 SNDR

The signal to noise and distortion ratio (SNDR) is the ratio of the RMS signal power Ps tothe RMS noise power Pn together with the RMS power of higher harmonics Phd integrated

89

90 B.6 Peak SNDR

over the band of interest:

SNDR =Ps

Pn + PhdSNDRdB = 10 log10

(Ps

Pn + Phd

)(B.4)

B.4 THD

The total harmonics distortion (THD) is the RMS power ratio of all harmonics of an inputsignal Ph to the input signal Ps itself:

%THD =√

Ph

Ps· 100 THDdB = 10 log10

(Ph

Ps

)(B.5)

B.5 DR

The dynamic range (DR) is the RMS power ratio of the fundamental signal at maximalamplitude Ps,FS to the RMS noise power Pn integrated over the band of interest:

DR =Ps,FS

PnDRdB = 10 log10

(Ps,FS

Pn

)(B.6)

The definition of the DR is illustrated in fig. B.1.

SNDR [dB]

Peak SNDR

amp [dBFS]

DR 0dBFS

0dB

DR

Figure B.1: Definition of DR

B.6 Peak SNDR

The peak SNDR indicates the highest achievable SNDR value of the system. Fig. B.1 showsthat for ever growing input amplitudes, the SNDR starts decreasing again. Therefore, theDR is always higher than or equal to the peak SNDR.

B.7 Remarks and Pitfalls 91

B.7 Remarks and Pitfalls

Different Definitions for the PSD

The power spectral density (PSD) can be either be defined for a one-sided or a two-sidedspectrum. For example, the integration over the band of interest fb for a thermal noisesource may be defined in the following ways:

. for a one-sided spectrum: Sn(f) = 4kbTR⇒ Pn =∫ fb

0 Sn(f)df = 4kbTRfb

. for a two-sided spectrum: Sn(f) = 2kbTR⇒ Pn =∫ fb

−fbSn(f)df = 4kbTRfb

Note, that both descriptions are common.

Filtering of stochastic continuous Signals

Given is a transfer function H(jω) of a filter in the Fourier domain. When Si(jω) describesthe PSD of the input signal, the PSD of the output signal So(jω) can be calculated asfollows:

So(jω) = |H(jω)|2 · Si(jω) (B.7)

It is also common to write the above equation in the following way:

So(f) = |H(f)|2 · Si(f) (B.8)

92 B.7 Remarks and Pitfalls

CMathematical Reference for certain

Σ∆-Architectures

This chapter delivers a quick mathematical reference for the following architectures:. 4th order Σ∆-modulator with feed-forward structure and with 1 delayed resonator. 4th order Σ∆-modulator with feed-forward structure and with 1 non-delayed resonator

Every reference consists of the SFG in the z-domain, the NTF, the location of the zerosn1, n2, ..., nn and the equations for calculating the corresponding parameter vectors a andb. The components of these vectors are expressed in terms of the poles p1, p2, ..., pn andthe components of the resonator parameter vector g in order to set the STF to 1.

The definition of the Noise Transfer Function (NTF) and the Signal Transfer Function(STF) are repeated here for convenience:

STF =Y (z)X(z)

NTF =Y (z)E(z)

X(z) : signal input function of the Σ∆-modulatorE(z) : noise input function of the Σ∆-modulator (for modeling the quantizer)Y (z) : output function of the Σ∆-modulator

These transfer functions can be derived either by hand calculations or by applying Mason’srule. There are also software tools available which are able to apply Mason’s rule to apredefined SFG automatically. A useful tool which was also used here is the MATLAB toolflowg. It is available for free from http://www.mathworks.com/matlabcentral/.

93

94 C.1 4th order Σ∆-modulator with 1 delayed resonator

C.1 4th order Σ∆-modulator with feed-forward structure andwith 1 delayed resonator

Signal Flow Graph

Quantizer

Y (z)

a3a2

+ E(z)

+

g

z−1

1−z−1

z−1

1−z−1

z−1

1−z−1

z−1

1−z−1

+ + +

a4a1

+

b4 b5b3b2b1

X(z)

−

−

Figure C.1: SFG of a 4th order Σ∆-modulator with feed-forward structure and with 1delayed resonator

Noise Transfer Function

NTF = ND

N = z4 − 4z3 + (6 + g)z2 + (−4− 2g)z + 1 + g

D = z4 + (a1 − 4)z3 + (a2 − 3a1 + g + 6)z2 + (−2a2 + a3 − 4 + . . .

ga1 + 3a1 − 2g)z + 1 + a2 − ga1 − a3 + a4 + g − a1

The Location of the Zeros

n1,2 = 1±√g (C.1)n3,4 = 1 (C.2)

The zeros are located on the imaginary axis at 1.

C.1 4th order Σ∆-modulator with 1 delayed resonator 95

The Parameter Vectors a and b

a1 = −p2 − p1 − p4 − p3 + 4a2 = p1p2 + p2p4 + p2p3 + p1p4 + p1p3 + p3p4 − 3p3 − 3p2 − 3p1 − 3p4 + 6− g

a3 = 4− 3p1 − 3p2 − 3p3 − 3p4 − 4g + 2p1p2 + 2p3p4 + 2p2p4 + 2p2p3 + 2p1p4 + . . .

2p1p3 − p1p2p3 − p2p3p4 − p1p3p4 − p1p2p4 + gp3 + gp2gp1 + gp4

a4 = 1− p1 − p2 − p3 − p4 + p1p2p3p4 + p1p2 + p3p4 + p2p4 + . . .

p2p3 + p1p4 + p1p3 − p1p2p3 − p2p3p4 − p1p3p4 − p1p2p4

a = [a1, a2, a3, a4] (C.3)

b = [1, 0, 0, 0, 1] (C.4)

The components of the parameter vector a are real, if the poles are either real or if theybuild complex conjugate pole pairs.

96 C.2 4th order Σ∆-modulator with 1 non-delayed resonator

C.2 4th order Σ∆-modulator with feed-forward structure andwith 1 non-delayed resonator

Signal Flow Graph

Quantizer

Y (z)

a3a2

+ E(z)

+

g

z−1

1−z−1

1

1−z−1

z−1

1−z−1

z−1

1−z−1

+ + +

a4a1

+ z−1

b4 b5b3b2b1

X(z)

−

−

Figure C.2: SFG of a 4th order Σ∆-modulator with feed-forward structure and with 1non-delayed resonator

Noise Transfer Function

NTF = ND

N = z4 + (g − 4)z3 + (6− 2g)z2 + (g − 4)z + 1 = (z − 1)2 · (z2 + 1− 2z + gz )D = z4 + (a1 − 4 + g)z3 + (a2 − 3a1 + ga1 + 6− 2g)z2 + . . .

(a3 − 2a2 − 4 + 3a1 − ga1 + g)z + 1 + a2 − a3 + a4 − a1

The Location of the Zeros

n1,2 = 1− g ±√

g2 − 4g

2(C.5)

n3,4 = 1 (C.6)

The zeros are located on the unit circle.

C.2 4th order Σ∆-modulator with 1 non-delayed resonator 97

The Parameter Vectors a and b

a1 = 4− p2 − p1 − p4 − p3 − g

a2 = p1p2 + p2p4 + p2p3 + p1p4 + p1p3 + p3p4 − 3(p1 + p2 + p3 + p4) + 6 + . . .

+g(p1 + p2 + p3 + p4 − 5 + g)a3 = 4− 3(p1 + p2 + p3 + p4) + 2p1p2 + 2p3p4 + 2p2p4 + 2p2p3 + 2p1p4 + . . .

2p1p3 − p1p2p3 − p2p3p4 − p1p3p4 − p1p2p4 + g(p1 + p2p3 + p4 + g − 4)a4 = 1− p1 − p2 − p3 − p4 + p1p2p3p4 + p1p2 + p3p4 + p2p4 + p2p3 + p1p4 + . . .

p1p3 − p1p2p3 − p2p3p4 − p1p3p4 − p1p2p4

a = [a1, a2, a3, a4] (C.7)

b = [1, 0, 0, 0, 1] (C.8)

The components of the parameter vector a are real, if the poles are either real or if theybuild complex conjugate pole pairs.

98 C.2 4th order Σ∆-modulator with 1 non-delayed resonator

DSettling and Slewing Behavior of Amplifiers

Every amplifier is only able to deliver a maximal output current. But applying an inputstep to an amplifier with a large load, may consume more current than the amplifier is ableto supply. In this case the amplifier can only deliver its maximal available output current.This mode of operation is called slewing. The timespan of slewing is called slewing timeTslew. When the amplifier is able to supply enough current, the mode of operation is calledlinear settling and the corresponding timespan is called linear settling time Tsettle. Hence,the total settling time is the sum of the slewing and the linear settling time. Fig. D.1shows an ideal settling behavior of an amplifier with the corresponding slewing and linearsettling time.

This chapter derives mathematically the slewing and settling time for a simplified am-plifier model. The calculations are based on [Bal04].

TsettleTslew

t

vo(t)

Figure D.1: Slewing and linear settling time for an amplifier

99

100 D.2 Modeling the Amplifier

D.1 The Basic Circuit for Amplifier Analysis

The basic circuit for amplifier analysis is a switched-capacitor integrator circuit (see fig.D.2) whose transfer function can be derived as follows:

H(z) =Cs

Cf· z−1

1− z−1(D.1)

Cs

Cf

Vo

Vi

Ci

1 2

2 1

1

Co

Vd

VgVii

Figure D.2: Switched-capacitor implementation of the transfer function D.1

As this analysis does not account for parasitic effects, parasitic components are not drawnin fig. D.2. As in every switched-capacitor circuit, there are two phases of operation. Fordescribing the slewing and the settling behavior of the amplifier, only phase 2 is importantbecause only in this phase the amplifier is connected to the largest load.

D.2 Modeling the Amplifier

Fig. D.3 shows the circuit for modeling the amplifier in linear settling mode. The outputcurrent id is a linear function of the transconductance gm and the input voltage vg.

Cgs Cds

id = gm · vg

vg vdvg

vd

Figure D.3: Simplified amplifier for modeling the linear settling behavior

Fig. D.4 shows the circuit for modeling the amplifier in slewing mode. The outputcurrent id is constant and does not depend on the input voltage vg.

D.3 Describing the Linear Settling Behavior 101

Cgs Cdsid = ib

vg vdvg

vd

Figure D.4: Simplified amplifier for modeling the slewing behavior

D.3 Describing the Linear Settling Behavior

The circuit for calculation is shown in fig. D.5 below. This circuit can be obtained byreplacing the amplifier in fig. D.2 with the model in fig. D.3 and by considering phase 2only.

Cgs Cds

Id(s) = gm · Vg(s)Vg(s) Vd(s)Vii(s)CfCs

Co

Figure D.5: Circuit for calculating the linear settling behavior

The transfer function H(s) from the input to the output voltage of the circuit in fig. D.5can be derived to:

H(s) =Vd(s)Vi(s)

=Cs · (Cf · s− gm)

s · Cs · (Co + Cf ) + s · Cf · Co + s · Ci · (Co + Cf ) + Cf · gm(D.2)

The general form of the transfer function H(s) is:

H(s) = A · κ · s− 1τ · s + 1

(D.3)

Comparing the eq. D.2 and D.3 leads to the following parameters:

κ =Cf

gm(D.4)

τ =Cs · (Co + Cf ) + Cf · Co + Cgs · (Co + Cf )

Cf · gm=

Csettle

gm(D.5)

A =Cs · gm

Cf · gm=

Cs

Cf(D.6)

In order to describe the settling behavior, a step response is applied to H(s):

Vi(s) = vsettle ·1s

(D.7)

102 D.3 Describing the Linear Settling Behavior

vsettle is the final value of the step response. Multiplying this step response with the transferfunction H(s) leads to the following expression:

Vd(s) = H(s) · vsettle ·1s

(D.8)

Taking the inverse Laplace transform of Vd(s) results in:

vd(t) = −vsettle ·A ·(

1− κ + τ

τ· e−

tτ

)+ vinit (D.9)

vinit is the initial value. It is important to see that the factor 1/τ in the exponential functiondetermines the settling time. A large τ corresponds to a slow settling, while a small τ meansa fast settling. Therefore, τ is called settling constant. It is often used to characterize thesettling time. As 1/τ is exactly the location of the first pole, a pole closer to the originmeans a higher τ and hence a slower settling while a pole farther away from the origin meansa slower τ and hence a faster settling. The fact that the location of the poles has an in-fluence on the settling behavior is sometimes also referred to in terms of fast and slow poles.

As −1/τ corresponds to the pole location of the transfer function H(s) (see eq. D.3),the bandwidth of the amplifier can be calculated as follows:

fBW ≈1

2πτ(D.10)

The settling time Tsettle strongly depends on the achievable settling error. For example asettling error of zero needs – at least theoretically – an infinite settling time. The settlingerror esettle can be calculated as follows:

esettle = −vsettle ·A− vd(t = Tsettle) = vsettle ·A ·κ + τ

τ· e−

Tsettleτ (D.11)

It is common practice to express the resolution of the settling in terms of n bits:

esettle

vsettle= 2−n (D.12)

This leads directly to the question about the tolerable settling error. How many bits ofresolution are necessary? – If the whole ADC has a resolution of m bits, then the settlingerror of the amplifiers need to be smaller than 2m/2 or LSB/2 respectively. That means ifthe minimal error of the ADC is LSB/2 then the settling error must be smaller than LSB/2so that the settling error esettle does not affect the resolution of the circuit. Therefore, thefollowing equation holds:

esettle

vsettle<

2−m

2(D.13)

The DR of an ideal quantizer with k bits is:

DRquant = 1.76dB + 6.02k (D.14)

Comparing the DR of the whole ADC with the DR of an ideal quantizer with k bits (eq.D.14) leads to the definition of the effective number of bits (ENOB):

ENOB =DR− 1.76dB

6.02dB(D.15)

D.4 Describing the Slewing Behavior 103

Putting eq. D.14 into eq. D.13 leads to the following expression:

Tsettle

τ> (n + 1) · ln(2) + ln(A) + ln

(τ

κ + τ

)(D.16)

It was observed that this expression can be approximated to the following expression:

Tsettle

τ> (ENOB + 1) · ln(2) (D.17)

This equation states that for a given settling time Tsettle and a given ENOB, there is amaximal value for the settling constant τ .

D.4 Describing the Slewing Behavior

The circuit for calculation is shown in fig. D.6 below. This circuit can be obtained byreplacing the amplifier in fig. D.6 with the model in fig. D.4 and by considering phase 2only.

Cgs CdsId(s) = ib

VgVd(s)Vii(s)

CfCs

Co

Figure D.6: Circuit for calculating the slewing behavior

In comparison to the circuit in the settling mode (fig. D.5), the amplifier delivers a con-stant current ib. The slewing behavior can be described by the following transfer function:

Vd(s) =CsCf

Cf · (Cs + Ci) + Co · (Cs + Cf + Ci)· Vii(s) . . . (D.18)

−Cs + Cf + Ci

Cf · (Cs + Ci) + Co · (Cs + Cf + Ci)· Id

s

Id(s) is the input current, Vii(s) the input voltage and Vd(s) the output voltage of the circuit.

The slewing time is the timespan for that the output current of the amplifier is at itsmaximal level. A further increase of this current is not possible. This condition correspondsto the requirement that the slope of the slewing curve is less than the slope of the linearsettling curve. The point where the slope of the slewing and linear settling curve are equal,corresponds to the end point of slewing because the amplifier can exactly deliver a currentof ib for correct linear settling there (see fig. D.7).

104 D.5 Adjusting the Settling Bahavior

TsettleTslew

t

vo(t) Settling BehaviorSlewing Behavior

SLslew = SLsettle

SLslew < SLsettle SLslew > SLsettle

t1 t2 = t1

Figure D.7: Linear settling and slewing behavior

Therefore, the slewing time is calculated by equalizing the slopes of the linear settlingand the slewing curve. The slope of the linear settling curve is the derivative of eq. D.9:

SLsettle(t) =dVd(t)

dt= −vsettle ·A ·

κ + τ

τ2· e−

tτ (D.19)

The slope of the slewing curve is the derivative of eq. D.18:

SLslew(t) =dvd(t)

dt= − ib

Cslew(D.20)

Cslew =Cf · (Cs + Ci) + Co · (Cs + Cf + Ci)

Cs + Cf + Ci(D.21)

The slope of the slewing curve is also called slew rate (SR) and is often given as characteristicparameter for amplifiers. Equalizing eq. D.19 and D.20 leads to the following equation:

− vsettle ·A ·κ + τ

τ2· e−

tτ = − ib

Cslew(D.22)

Solving for t leads to the slewing time Tslew:

Tslew = τ · ln(

(κ + τ) · vsettle ·A · Cslew

ib · τ2

)(D.23)

D.5 Adjusting the Settling Bahavior

The total settling time Ttot,settle is the sum of the slewing and the linear settling time:

Ttot,settle = Tslew + Tsettle (D.24)

In switched-capacitor circuits the settling time depends on the phase time Tph of a clocksignal. The total settling time Ttot,settle is usually expressed as a fraction p of the phasetime Tph. Therefore, it holds:

p · Tph ≥ Tslew + Tsettle (D.25)

EThe Simulation Framework in Matlab

This chapter describes a simulation framework for designing and simulating Σ∆-modulatorsthat was developed throughout this project.

Figure E.1: Simulation framework in Matlab

E.1 Installation and Run

The framework is installed by executing the shell script install.sh. For starting the frame-work, start MATLAB and enter the command run adctest.

105

106 E.3 Using the Framework

E.2 Development State of the Framework

The framework was mainly written for the design of a 4th order Σ∆-modulator with 1non-delayed resonator (see model ciff 4th 1res comp2.mdl). Therefore, this model shouldwork properly with all available tools. But it was also the idea that the framework shouldbe flexible enough for simulating every Σ∆-modulator model. At the time of writing, notall tools are able to cope with all models. It is necessary that the user adapts the sourcecode to her or his needs.

E.3 Using the Framework

E.3.1 Overview

The framework comes with a graphical user interface (GUI) that should ease the dailyusage. The main window is shown in fig. E.2. It consists of a menu bar (1) for accessingthe tools, an execute bar (15) for starting the simulation, updating the fields with the storedvariables in the workspace and for closing all figures and a body for configuring the model.All available models are listed in the combo box (2). For every model the following partsmust be set up:Quantizer Levels see (3)Input Mode The transfer functions NTF and STF can be either inserted by poles and

zeros or by coefficients. Use the radio buttons (4) for switching between the twoinput modes. In the input mode by Poles, the application calculates the correspondingcoefficients so that STF is 1 automatically. In the input mode by Gains, the applicationcalculates the corresponding poles and zeros automatically.

NTF Definition The NTF is defined according to the input mode:. by Poles: defined by the poles (5) and the resonator parameters gi (6). by Gains: defined by the coefficients ai (7) and the resonator parameters gi (6)

STF Definition The STF only needs to be defined if its transfer function is not 1. It isdefined according to the input mode:

. by Poles: defined by the poles (5) and the resonator parameters gi (6)

. by Gains: defined by the coefficients ai (7) and bi (8)Scaling Factors The scaling factors si (9) are only needed for scaled models.Input Signal The sine input signal (10) has an amplitude which is referred to the full-scale

value (FS) and a frequency which is referred to the bandwidth fb.Dynamic Element Matching (DEM) This feature (11) is only available if the Simulink

model contains a DEM-block. In order to simulate the model, the size of the inputcapacitance and the type of mismatch has to be chosen. For the type of mismatchholds:

. no mismatch: The DEM block is deactivated.

. fab figures: The standard deviation and mismatch equations of the correspondingfabs are used for calculations.1

. custom mismatch: Enter the standard deviation in the field below.Standard Selection The standards are set by the sampling frequency fs and the OSR. The

bandwidth fb is calculated automatically. The standards can be selected by clicking

1Edit the file dem.m in the folder DEM.

E.3.2 Available Tools 107

the right mouse button.Simulation Mode There are three possible simulations (13):

. NTF: This simulation uses the model in the z-domain (without the quantizer)for plotting the NTF and the pole-zero map.

. Simulink: This simulation uses the Simulink model and generates an analyzedspectrum.

. Approximation: This simulation uses the model in the z-domain with added whitenoise for simulating the quantizer. It generates an analyzed spectrum.

For the simulations Simulink and Approximation, it is necessary to define the totalnumbers of DFT points (in powers of two) for generating the spectra. By clicking theright mouse button, two common number of DFT points can be selected.

The main window also contains a status control console (14) which protocols the actions.These messages are also printed at the MATLAB console.

Figure E.2: The main window

E.3.2 Available Tools

The tools can be accessed from the tab Tools in the menu bar. A short description of thesetools follows next:Root Locus This tool performs a root locus analysis of the current model. It can be used

for all models.Pole-Zero Estimation with Filter Design This tool estimates the location of poles and

zeros for the NTF by the help of a high pass Chebyshev filter and a high pass Butter-worth filter. These calculated poles and zeros may serve as starting point for further

108 E.3 Using the Framework

investigations. The calculated poles and zeros can be copied from the clipboard (seemenu Edit > clipboard). This tool can be used for all models.

Polefinder This tool performs a brute force search for two conjugate complex pole pairson a circular area with a predefined radius and a predefined raster. It only works fora 4th order feed-forward structure with 1 resonator.

ProveStab This tool performs a quick stability analysis for the given model. It varies theDFT points, the amplitude and the OSR in order to check whether the DR and SNDRvaries in a predefined tolerance range. This tool can be used for all models.

Poleranger This tool allows the sweeping of two conjugate complex pole pairs and of oneresonator parameter g. It only works for a 4th order feed-forward structure with 1resonator.

Ceteris Paribus Polewalker This tool optimizes two conjugate complex pole pairs and 1resonator parameter g. It only works for a 4th order feed-forward structure with 1resonator.

SD Toolbox of Thomas This toolbox was developed by Thomas Christen. It containsdedicated Simulink blocks for Σ∆-design.

Report Generation This tool gathers all open figures and relevant simulation data in orderto generate a report. The content of this report can be edited in the menu Edit >Edit Report Style and Content.

Plot SNR vs. Input Range This tool performs a SNR vs. input range plot. It can be usedfor all models.

Plot Swings This tool plots the swings of five measurement points placed inside the Simulinkmodel. The name of these data saving points are swing1 to swing5. The plot allowsthe drawing of individual or multiple swings. This tool can be used for all Simulinkmodels that include these saving points.

Analytical Pole Optimization This tool tries to find optimal pole-zero placements by ana-lytical methods. It only works for a 4th order feed-forward structure with 1 resonator.

Design Visualization Studio This tool visualizes the cost functions for a 4th order feed-forward structure with 1 resonator.

Montevideo This tool performs a Monte Carlo simulation with the coefficients ai, bi andgi. It can be used for all models.

FSchematics

CompxC

SelxS〈0〉

SelxS〈1〉

v+ v−

CompxC

v−

v+

w = 120nm

l = 60nm

w = 120nm

l = 120nm

×18

(a) Adjustable switch

C+

C−

SelxS〈1〉

SelxS〈0〉

C = 80fF

C

C

C

C

C

C+

C−

⇐⇒

(b) Variable capacitor

Figure F.1: Variable passive components

109

110 APPENDIX F. SCHEMATICS

800mV

900mV

575mV

600mV

300mV

200mV

300mV

900mV

675mV

500mV

200mV

300mV

1.2V

gm = 9.5mS

gds = 261µS

vdsat = 123mV

Vbcp

Iref

Vin+ Vin−

Vout− Vout+

vcom

,in

vcom

,ou

t

Id = 375µA

I = 25µA

- -

CMFB

W4 = 11.5µm

L4 = 180nm

m = 15

W5 = 6.8µm

L5 = 600nm

m = 15

W4

L4

W3

L3

W3 = 2.85µm

L3 = 180nm

m = 15

W1 = 5.4µm

L1 = 600nm

m = 30

W2

L2

W1

L1

gm = 6.2mS

gds = 1.2mS

vdsat = 80mV

gm = 5.7mS

gds = 337µS

vdsat = 91mV

gm = 6.6mS

gds = 350µS

vdsat = 92mV

gm = 3.7mS

gds = 75µS

vdsat = 193mV

W2 = 4.55µm

L2 = 160nm

m = 15

W5

L5

W2

L2

W4

L4

W5

L5

W4

L4

(a) Main circuit

Vref

Vb

vin+ vin−

Vout

ϕ2

ϕ1

C2

ϕ2

ϕ2ϕ2

ϕ1

ϕ1

ϕ1

C2 = C1C1 = 350fF C1

(b) CMFB

Figure F.2: Amplifier

111

900mV

575mV

675mV

600mV

420mV

200mV

300mV

200fF

Vout− Vout+

Vin+ Vin−

900mV

1.2V

I = 25µA

W4

L4

W3 = 26.9µm

L3 = 600nm

W2

L2

W1

L1

W4 = 24.3µm

L4 = 600nm

W3

L3

Transistors M1 and M2 have the same size

as M1 and M2 in the main amplifier.

W2

L2

W1

L1

(a) p-side regulating amplifier

800mV

575mV

500mV

420mV

200mV

300mV

140fF

Vout+

Vin+ Vin−

900mV

1.2V

Vout−

I = 25µA

W4

L4

W1 = 5.42µm

L1 = 600nm

W2

L2

W1

L1

W2 = 26µm

L2 = 600nm

W5

L5

W4

L4

W5

L5

Transistors M4 and M5 have the same

size as M4 and M5 in the main amplifier.

(b) n-side regulating amplifier

Reference current input p-side Stabilization n-side Stabilization

Iref

W3 = 11.5µm

L3 = 180nm

W4

3 · L4

W4 = 6.8µm

L4 = 600nm

W4

L4

W4

L4

W4

L4

W4

L4

W3

L3

W3

L3

W3

L3

W3

L3

W2

L2

W1

L1

W2 = 2.85µm

L2 = 180nm

W1 = 5.4µm

L1 = 600nm

W2

L2

W2

L2

W2

L2

W2

L2

W2

L2

W1

L1

W1

L1

W1

L1

W1

L1

Vbcp

Vbp

Vbcn

Vbn

Vrefcn

Vrefn

Vrefcn

Vrefn

Vrefcn

Vrefn

Vbcp Vbcp Vbcp

Vbp VbpVbp

(c) Bias circuit

Figure F.3: Amplifier

112 APPENDIX F. SCHEMATICS

ResCmpxDO〈0〉

vin+

vin−

A

C = 1pF

C = 1pF

C = 1pF

C = 1pF

C = 1pF

C = 1pF

C = 1pF

1

2

3

4

5

6

7

iquant

Phi1xC

icomp

icom

p〈0

〉

icom

p〈6〉

vin+

vin−

ResCmpxDO〈0 : 6〉

iquant

icomp

Bias Currents for the Comparators

Resistive Ladder

i com

p〈0

〉

B

i com

p〈1

〉

Comparators

ResCmpxDO〈1〉

C

ResCmpxDO〈2〉

1

7

i com

p〈2

〉

D

ResCmpxDO〈3〉

i com

p〈3

〉

ResCmpxDO〈4〉

E

i com

p〈4

〉

ResCmpxDO〈5〉

ResCmpxDO〈6〉

i com

p〈5

〉i c

om

p〈6

〉

F

G

1

7

2

6

6

2

3

3

5

5

4

4

w = 8.42µm

l = 21µm

R = 621.81Ω

w = 890nm

l = 180nm

w = 1.98µm

l = 420nm

w = 8.42µm

l = 21µm

R = 621.81Ω

w = 8.42µm

l = 21µm

R = 621.81Ω

w = 8.42µm

l = 21µm

R = 621.81Ω

w = 8.42µm

l = 21µm

R = 621.81Ω

w = 8.42µm

l = 21µm

R = 621.81Ω

w = 3.25µm

l = 280nm

w = 10µm

l = 400nm

w = 5µm

l = 1.5µm

w = 5µm

l = 2µm

900mV

600mV

675mV

600mV

525mV

660mV

300mV

i b=

10µA

vcmo

DelayPhi1DxC

1 : 4

1 : 4

vin+

vin−

vref+

vref−

Phi1

DxC

vin+

vin−

vref+

vref−

Phi1

DxC

vin+

vin−

vref+

vref−

Phi1

DxC

vin+

vin−

vref+

vref−

Phi1

DxC

vin+

vin−

vref+

vref−

Phi1

DxC

vin+

vin−

vref+

vref−

Phi1

DxC

vin+

vin−

vref+

vref−

Phi1

DxC

Figure F.4: Quantizer

113

Com

pxC

Com

pxC

BP

hi1

DxC

I

Com

pD

xC

×2

×4

×7

×13

×18

vb

=300m

V

i com

p

Com

pxC

vin

+

vin−

vref− vref+

vb

300m

V

300m

V300m

V

w=

2.7

5µm

l=

420nm

m=

3

w=

2.7

5µm

l=

420nm

m=

3

w=

1.2

µm

l=

200nm

w=

3.5

5µm

l=

300nm

w=

3µm

l=

60nm

w=

1.5

µm

l=

60nm

600m

V

600m

V600m

V

600m

V

w=

3.5

5µm

l=

300nm

×2

×2

Cw

=10fF

Cw

=10fF

w=

2.6

2µm

l=

420nm

600m

Vw

=1.9

5µm

l=

120nm

w=

2.7

5µm

l=

420nm

Com

pxC

Com

pD

xC

Com

pxC

BC

om

pxC

B

w=

1µm

l=

140nm

w=

1µm

l=

140nm

RC

1xD

w=

0.1

2µm

l=

60nm

w=

6.2

µm

l=

120nm

×4

×9

Res

Cm

pxD

O

×2

×2

RC

2xD

RC

1xD

RC

2xD

Com

pxC

vin

+

vin−

vref+

vref−

Phi1DxC

icomp

Figure F.5: Comparator

114 APPENDIX F. SCHEMATICS

CLKxCI

CLKxCBI

Phi1xCO

Phi1xCBO

Phi2xCBO

Phi2xCO

Phi2DxCO

Phi1DxCO

CLKxCI

CLKxCBI

Phi1xCO

Phi1xCBO

Phi2xCBO

Phi2xCO

Phi2DxCO

Phi1DxCO

×4

×4

×4 ×4

×4

×4×4

×4×4×4

×4

×4

×4

×4

×4

×4

×9

×9

×9

×9

×13

×13

×13

×13

×18

×18

×18

×18

×22

×22

×22

×22

×27

×27

×27

×27

×27

×27

×4

×4

Figure F.6: Clock generator

CLKxC

CLK

xC

B

vout

vin

500fF

100fF100fF

sCLKxC CLKxCB

CLKxC

s

voutvin

×2

×22

w = 120nm

l = 60nm

w = 120nm

l = 60nm

w = 120nm

l = 60nm

w = 2µm

l = 60nm

w = 2µm

l = 60nm

w = 4µm

l = 60nm

w = 4µm

l = 60nm

w = 10µm

l = 60nm

w = 120nm

l = 60nm

w = 4µm

l = 60nmw = 10µm

l = 60nm

N = 7

Ron = 18.89Ω

Figure F.7: Bootstrap switch

115

+ -

- +

C3

12

C3

1 2

C4

C4

+ -

- +

C5

12

C5

1 2

C6

C6

vcm

ivcm

i

vcm

ivcm

i

vcm

ovcm

o

vcm

ovcm

o

+ -

- +

C7

1

1d 2d

2

C7

1

1d2d

2

C8

C8

vcm

i

vcm

i

vcm

o

vcm

o

+ -

- +

121 2

C2

C2

vcm

i

vcm

i

C12

C12

C13

2

vcm

ivcm

i

A3

A2

A1

A4

1d

1d 2d

2d

1d

1d 2d

2d

1d2

d

1

C13

2

vcm

ivcm

i

1d 2

d

1 C11

C11

C10

C10

C9

C9

DW

A

C1,i

1

2d

SW

+〈i〉

vref

p

vref

n

〈6:0〉

C1,i

1

vref

p

vref

n

〈6:0〉

77

〈6:0〉

Quantize

rxD

O

SW−

〈i〉

DA

C〈i〉

SW

+〈i〉

SW−

〈i〉

SW−

〈i〉

SW

+〈i〉

Figure F.8: Main schematic

116 APPENDIX F. SCHEMATICS

GList of Abbreviations

ADC : A/D-ConverterCMFB : Common Mode FeedbackDAC : D/A-ConverterDEM : Dynamic Element MatchingDFT : Discrete Fourier AnalysisDR : Dynamic RangeDWA : Data Weighted AveragingENOB : Effective Number of BitsFOM : Figure of MeritFS : Full ScaleISR : Input Stable-RangeLSB : Least Significant BitNMOS : n-Channel MOSFETNTF : Noise Transfer FunctionOpAmp : Operational AmplifierOSR : Over-Sampling RatioPMOS : p-channel MOSFETPSD : Power Spectral DensityRMS : Root Mean SquareSFG : Signal Flow GraphSNR : Signal to Noise RatioSNDR : Signal to Noise and Distortion RatioSQNR : Signal to Quantization Noise RatioSR : Slew RateSTF : Signal Transfer FunctionTHD : Total Harmonic DistortionUGBW : Unity Gain Bandwidth

117

118 APPENDIX G. LIST OF ABBREVIATIONS

Bibliography

[AG98] A.M. Abo and P.R. Gray.A 1.5 V, 10-bit, 14 MS/s CMOS Pipeline Analog-To-Digital Converter.In VLSI Circuits, 1998. Digest of Technical Papers. 1998 Symposium on, pages

166–169, 11-13 June 1998.

[Bal04] Pio Balmelli.Broadband Sigma-Delta A/D Converters.PhD thesis, ETH Zurich, 2004.

[Bla06] Tobias Blaser.Design of a Multi-bit Sigma Delta ADC for UMTS.2006.

[CY06] Zhiheng Cao and Shouli Yan.A Study on Voltage Reference Buffers for Low Voltage Switched Capacitor Data

Converters.In Circuits and Systems, 2006. MWSCAS ’06. 49th IEEE International Midwest

Symposium on, volume 2, pages 502–506, 6-9 Aug. 2006.

[Dev] Analog Devices.Analog-Digital Conversion, Data Converter History.

[FV06] P.M. Figueiredo and J.C. Vital.Kickback Noise Reduction Techniques for CMOS Latched Comparators.In IEEE Transactions on Circuits and Systems - II, Express Briefs, volume 53,

July 2006.

[Her04] Jurgen Hertle.Folding and Interpolating A/D Converters for Communications Applications.PhD thesis, ETH Zurich, 2004.

[ISS] JSSC ISSCC.Data Material for Implemented Σ∆-Modulator Designs.

[JGK93] L. Richard Carley John G. Kenney.Design of Multibit Noise-Shaping Data Converters.Analog Integral Circuits and Signal Processing, pages pp. 259–272, 1993.

[Jia06] Xiaozhuo Jiang.Design of a Sigma Delta ADC for UMTS Using DEM.2006.

[JM96] David Johns and Ken Martin.Analog Integrated Circuit Design.John Wiley & Sons, 1996.

119

120 Bibliography

[KB90] Govert J. G. M. Geelen Klaas Bult.A Fast-Settling CMOS Op Amp for SC Circuits with 90-dB DC Gain.IEEE Journal of Solid-State Circuits, pages pp. 1379–1384, 1990.

[Mur] Boris Murmann.Lecture Notes: Analog Integrated Circuit Design.

[OC90] L. Richard Carley Ojas Choksi.Analysis of Switched-Capacitor Common-Mode Feedback Circuit.IEEE Transactions on Circuits and Systems, pages pp. 1379–1384, 1990.

[Pau01] Paul R. Gray, Paul J. Hurst, Stephen H. Lewis, Robert G. Meyer.Analysis and Design of Analog Integrated Circuits.John Wiley & Sons, 2001.

[Raz97] Behazad Razavi.Delta-Sigma Data Converters and Principles of Data Conversion System Design

Set.IEEE, April 1997.

[RS05] Gabor C. Temes Richard Schreier.Understanding Delta-Sigma Data Converters.Wiley-Interscience, 2005.

[Sen06] Christian Senning.Design of a Multi-Bit Sigma Delta ADC for UMTS.2006.

[YGS02] Michiel Steyaert Yves Geerts and Willy Sansen.Design of Multi-Bit Delta-Sigma A/D Converters.Kluwer Academic Publishers, 2002.

[YNI91] Kan Takeuchi Eiji Kume Yasushi Watanabe Toru Kaga Yoshifumi KawamotoFumio Murai Ryuichi Izawa Digh Hisamoto Teruako Kisu Takashi NishidaEiji Takeda Yoshinobu Nakagome, Hitoshi Tanaka and Kiyoo Itoh.

An Experimental 1.5-V 64-Mb DRAM.In IEEE Journal of Solid-State Circuits, volume 26, pages 465–471, April 1991.

Index

AADC, 3– performance, 4amplifier, 51, 109– bandwidth, 52– bias circuit, 57– Bode-plot, 58– design parameters, 53– gain reduction, 58– input swing scaling, 17– main amplifier, 53– moderate inversion, 52– output swing scaling, 35– performance, 58– regulated cascode, 51– regulating cascode, 54– settling, 52, 58– transconductance, 52architecture– simulation results, 21– transformations, 17

Bboostrap switch– design, 64bootstrap switch, 64, 109

Ccapacitors, 30– circuit scaling, 35– settling capacitance, 52– sizing, 33– variable capacitor, 34clock generator, 69, 109– implementation, 70– timing, 69CMFB, 54common mode– common mode feedback, 54– input common mode, 58

– output common mode, 58comparator, 41, 109– categories, 41– design, 42– kickback noise, 48– offset voltage, 46– recovery time, 44– regeneration time, 44– resolution, 47cost function, 13

DDAC, 61DR, 90– goal function, 12DWA, 62dynamic element matching, 61

EENOB, 4

Ffiltering– stochastic continuous signals, 91framework, 105

Ggoal function, 12– reshaping, 14– scaling, 14– weighting, 14

Iinput stage, 61ISR, 4– goal function, 12

LLSB, 3

M

121

122 Index

multi-standard– system optimization, 16

Nnoise shaping, 5notch, 9NTF, 4

OOSR, 3

Ppeak SNDR, 90pole-zero placement, 8PSD, 91

Qquantizer, 36, 109– ideal quantizer, 36– implementation, 37– quantization error, 3– quantization noise, 3– reference voltages, 36

Rrational path gains, 19receiver system, 1results, 71– corner analysis, 74– Monte Carlo simulation, 74– power consumtion, 76– spectra, 72– temperature variation, 74

SΣ∆-modulator, 3– importance, 5– topology, 7Σ∆-modulators– design flow, 83settling time, 99slewing time, 99SNDR, 89– peak SNDR, 90SNR, 4, 89SQNR, 3, 89STF, 4swing scaling factors, 17

switched-capacitor design, 25switches– bootstrap, 64– linearity, 64system optimization, 15

TTHD, 90thermal noise, 30– transfer functions, 31thermometric coding, 61transfer function, 7– optimization, 10