A 1.1V 150GHz Amplifier with 8dB Gain and +6dBm Saturated Output Power pin Standard Digital 65nm CMOS

Using Dummy-Prefilled Microstrip Linesg y p

M. Seo1, B. Jagannathan2, C. Carta1, J. Pekarik3, L Ch 1 C P Y 1 d M R d ll1L. Chen1, C. P. Yue1 and M. Rodwell1

1Dept. of Electrical and Computer Engineeringp p g gUniversity of California, Santa Barbara

2IBM, Burlington, VT

1

3IBM, Crolles, France

Outline

• Introduction• “Dummy-Prefilled” Microstrip Line

– Structure and Modeling• Design and Simulation• Measurement Results

2

Beyond 100GHz: What Applications?

15

20

atio

n m

)O2

H O

94GHz 140GHz 220GHz

0

5

10

Atte

nua

(dB

/km

O2

H2OH2O

0 50 100 150 200 250 300 3500

Frequency (GHz)

C i ti• Communication– Outdoor, indoor

• Imaging (Passive active)• Imaging (Passive, active)– Security– All-weather radar

3– Medical

Beyond 100GHz: Why CMOS?

• Low-costL• Low-power

• Large-scale Integration → ParallelismLarge monolithic phased array imager– Large monolithic phased array, imager.

• RF/mm-wave, IF/analog, DSP on a same die.– System-on-chipSystem on chip– Digital calibration of RF/analog circuit imperfections,

process variations.– Reconfigurability and adaptability

4

What Challenges in 150GHz CMOS Amp?

• Low available FET gain, Low Supply Voltage– Careful FET layout & sizingCareful FET layout & sizing– Multi-stage Common-Source

• Modeling uncertaintiesg– Simple matching topology with microstrip (MS) lines

• Automatic “dummies” alter MS-line characteristics– Propose “Dummy-prefilled” MS-line

• Characterization– Full 2-port on-wafer TRL calibration

5

FET Layout

8

(dB

)

Parallel

5

6

7

e G

ain

( Parallel gate feed (PGF)

DSG

3

4

5

m S

tabl

e

G

0

1

2

Max

imum Series

gate feed (SGF) S D

10x1um/65n0

Frequency (GHz)100 200 300

M

G

6• Finger design: Reduce Rg,ext and Cgd (WF=1um)• Wiring multiple fingers: Parallel versus Series

“Microstrip Line” in Nanoscale CMOS

• “Automatic” dummies/holes to meet metal density rules

Ground plane

• Automatic dummies/holes to meet metal density rules.• Line capacitance increases

– ΔC depends on E-field orientation → Anisotropic

7

ΔC depends on E field orientation → Anisotropic• Direct E/M simulation nearly impossible

Possible Shapes of Dummy Pre-fillers

• “LINE” dummiesLINE dummies• Parallel to current flow

dummies

• “LINE” dummiesP di l fl• Perpendicular to current flow

• “SQUARE” dummies• No preferred direction of

8

No preferred direction of current flow

Reducing Complexity in E/M Sim

E/M simulation feasibleby significantly reducing

W SDummy

Signal Signal

y g y g# of dummiesPre-fillers

D f if di l t iDummy-free uniform dielectricwith adjusted diel. constant

E-fieldlines

ε ε’

9Successive dummy-layer substitutionby parallel-plate capacitor simulation

Line Inductance/Capacitance vs Fill Ratio

40

ge 25% FillL per unit length

(317nH/m w/o fillers)

-200

20

% c

hang

25% FillW:S = 1:1

(317nH/m w/o fillers)

-400 10 20 30 40 50 60

%

+32%

02040

hang

e 56% FillW:S = 3:1+17%

+32%

-40-20

0 10 20 30 40 50 60

% c

h C per unit length(103pF/m w/o fillers)

10

0 10 20 30 40 50 60

Fill Ratio (%)

Ground Plane Construction

• Solid GND plane not allowedS G p• Put holes, and strap M1 & M2 +

M1M2via

Where current flow is uniform Where current flow is not uniform

11

(e.g. under MS-line) (e.g. under bends, T-junction,radial stubs)

THRU-REFL-LINE (TRL) Calibration

(1) THRU

Half THRU

(1) THRU

450um Referenceplane

(2) REFL

ΔL

(Open, short, etc)

(3) LINE

A lifi

ΔL(ΔL= 90 deg @center freq)

AmplifierTest

REFL & LINE d t b t l k12

• REFL & LINE need not be accurately known• Measurements normalized to the line impedance

3-Stage 150GHz Amplifier: SchematicV2 V3

All TL’s: Z0= 51.2 W=10uRadial

TL1 TL2 TL3 TL4

W=10u(25% fill)

stub

M1 M2 M3V1V4

Half THRU Half THRUAmplifier30u/65n 30u/65n 30u/65n

N DC bl k F V V f M1 & M2 b t• No DC block: Forces VGS=VDS for M1 & M2, but eliminates loss and modeling uncertainties associated with DC-block cap

13• FET size is chosen for low matching loss• Radial stub for lower loss than quarter-wave TL

FET Sizing

constant-gi l (20 S)circle (20mS) S22* (g22≈ g11)

constant QS11

Z0

constant-Q circle

S11

Small FET

Large FET FETFET

C j t i t/ t t/i t t t h14

Conjugate input/output/inter-stage match with shunt tuning stubs only.

Simulated 150-GHz Amplifier Gain

7

5

6

B)

Radial stub(45deg opening) 0.65V 1.1VAC

short

PDC= 25mW

3

4

S21

(dB

Open-stubZ0=34, W=20u¼λ

1

2Open-stub

Z0=51, W=10u¼λ

0140 150 160 170 180 190 200

Frequency (GHz)15

Frequency (GHz)

Die Photograph

Dummy-prefilled radial stub

• Area= 0.4mm2 (w pads)

640μm( p )

= 0.16mm2 (w/o pads)

• Stack: 9 Cu + 1 Al

Dummy-prefilled MS-lines

ReferenceplanesAutomatic

16640μm

Automaticdummies

S-parameter Measurement Setup

Probe 140-220GHz 8510CW/G CoaxOML Inc. AgilentGGB Probes

Station mm-wave heads VNAWR05 IF/LO

17

Can we trust the calibration?

0 2

0.4

)

S11THRU < -40dB|S21THRU| < 0.1dB

-0.2

0

0.2

S21

(dB

) |S21THRU| < 0.1dB

-0.4140 150 160 170 180 190 200

Frequency (GHz)

|S11OPEN| < 0.2dB

S11LINE < -35dB

q y ( )

• Probe coupling < -40dBR t bilit i• Repeatability issues– Probe placement– Probe contact resistance

18

– Probe contact resistance

Prefilled MS-Line: Measurement

-1

0E/M Sim.

/mm

) 1mm-long Line

-4

-3

-2

-2.0dB/mm @140GH

-2.8dB/mm S21|

(dB

/

-5

4

0 20 40 60 80 100 120 140 160 180 2000

@140GHz @200GHz|Sg)

-60-40-20

0

E/M Sim (8% error)ase

(deg LINE standard

-120-100-8060 E/M Sim (8% error)

S21

Pha

19

1200 20 40 60 80 100 120 140 160 180 200

Frequency (GHz)

S

Measured Amp. S-Parameters

10S21 Meas

Sim

Peak |S21|= 8.2dB

0

5

r (dB

)

Sim

0.65V 1.1VPDC= 25.5mW3dB BW= 27GHz

10

-5

aram

ete

S11meas

-15

-10

S-pa S22

-20140 150 160 170 180 190 200

Frequency (GHz)

S11sim

20

Frequency (GHz)

S21 versus Current Density

8 60

7

4050

mW

)

5

6

304

21 (d

B)

ower

(m

V

0.5~0.9V

4

5

020

S2

DC

PoV

3

4

010

21

100 200 300 400 500 600 700Drain Current Density (uA/um)

S21 @Higher Drain Bias (M3)

9

678

B) V1=V2=V3<V4

3456

S21

(dB

V V V1.1V

V1=V2=V3<V4

0.5~0.9V

123S

00 10 20 30 40 50 60

22DC power (mW)

Amplifier Stability Factor

5

3

4

acto

rs

K > 1

1

2

abili

ty F

a

B1 > 0

0

1

140 150 160 170 180 190 200

Sta

140 150 160 170 180 190 200

Frequency (GHz)

23• Unconditionally stable over 140-200GHz.

Large-Signal Setup

WR05

20 GHzSignal

x12Freq.

WR05Variable Power

MeterWR05-WR10

0.2dB lossGGB probes

gSource

qMultiplier Attenuator MeterWR10

Virginia Diode Inc.

EriksonInstruments.

On-wafer DUT

PIN= -20dBm ~ +15dBmFreq= 153GHz ~175GHz

• Power correction: Insertion calibration using W/G

24

THRU & On-wafer THRU

Large-Signal Characteristics

25 10

%) P = +6 3dBm

20 5

n (d

B)

ienc

y (% Psat= +6.3dBm

oP1dB= +1.5dBm

freq= 153GHzPDC= 25.5mW

10

15

-5

0

Bm

),G

ai

ed E

ffici

Peak PAE= 8.4%

oP1dB 1.5dBm0.65V 1.1V

5

10

-10

5

P out

(dB

wer

Add

e Peak PAE 8.4%

0-20 -15 -10 -5 0 5

-15Pow

25

Pin (dBm)

Comparison of Measured S21

10S21 from VNA Meas.

6

8

1 (d

B)

S21 from VNA Meas.S21 from Power Meas.

2

4S21

0140 150 160 170 180 190 200

F (GH )Frequency (GHz)

• VNA Measurement: Full 2-port TRL calibration26

VNA Measurement: Full 2 port TRL calibration• Power Measurement: Insertion calibration

Performance Summary

Technology 65nm digital CMOSTopology 3-stage Common-sourceCenter freq 150GHz3dB BW 27GHzPeak Gain 8.2dBI t RL 7 4dBInput RL -7.4dBOutput RL -13.6dBDC P 25 5 WDC Power 25.5mWP1dB +1.5dBmP +6 3dBm

27

Psat +6.3dBm

Conclusion

• Minimalistic Circuit Design StrategyC g S gy• “Design-rule Compliant” Transmission Line

Structure and Modeling• Linear/Power measurement up to 200GHz• Highest frequency CMOS amplifier reported to date

28

Acknowledgement

• IBM for chip fabrication and supportp pp• OML Inc.• This work was supported by the NSF under grants

CNS-0520335 and ECS-0636621

29