A Linear Regulator with Fast Digital Control for Biasing of Integrated DC-DC Converters A-VLSI class...

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A Linear Regulator with Fast Digital Control for Biasing of Integrated DC-DC Converters A-VLSI class presentation Adopted from isscc Presented by: Siamak Mehrnami

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  • A Linear Regulator with Fast Digital Control for Biasing of Integrated DC-DC ConvertersA-VLSI class presentationAdopted from issccPresented by:Siamak Mehrnami

  • Outline Integrated DC-DC convertersLinear regulator with digital controlImplementation detailsmeasurementsConclusions

  • Integrated DC-DC ConvertersDemonstrated at 100MHz, =87.7%Ref.: [3]

  • Problem: Low Input VoltageThe CMOS process limits the DC-DC converter input voltage to 1.2-1.4V Ref: [1]

  • Doubling of Input Voltage RangeVIN is across two transistors in seriesNeed a -rail linear regulator Ref.: [4]

  • High tension power delivery through implicit voltage conversion ref:[2] 2VDD system3VDD system

  • Auxiliary Regulator RequirementsCalculate Figure of Meritsingle value to measure performance Ref:[1]

  • Auxiliary Regulator Figure of MeritBest known regulator had FOM=22psRajapandian, et al., 2005 ISSCC, p. 298Need same speed at 3X lower power ref:[1]

  • Traditional Linear RegulatorsClass-A buffer has poor slew rateClass-AB buffer degrades stability ref:[1]

  • Regulator with Digital ControlDigital buffers (inverters) are perfect class-AB circuits, fast and low power ref:[1]

  • Push-Pull -Rail Regulatorref:[1]

  • Template Cell Design for Matchingref:[1]

  • Customized Inverter Cellsref:[1]

  • Floorplan of Matched Invertersref:[1]

  • Regulator Test Chip in 90nm CMOSref:[1]

  • Input-Output DC Characteristicref:[1]

  • Output DC Characteristicref:[1]

  • Load Step Response (5ns/div)ref:[1]

  • Performance Comparisonref:[1]

  • ConclusionsDigital buffers (inverters) are more power-efficient than analog buffersAchieved 3.64X lower quiescent current at 28% slower responseFOM is 2.84X better than the prior artThe power bottleneck moved from the analog buffer to the error amplifiermatching requirements influence transistor sizes and the quiescent currentref:[1]

  • References:1-P.Hazucha, A Linear Regulator With Fast Digital Control For Biasing Integrated DC-DC Converters ISSCC dig. tech. papers 29.2 feb.2006 2-S. Rajapandian, et al., High-Tension Power Delivery- Operating 0.18m CMOS Digital Logic at 5.4v, ISSCC dig. Tech. papers,pp.298299,Feb., 2005 [page 6] 3- Hazucha, et al., 2004 VLSI Symposium, p. 256.4-Xiao, et al., 2004 ISSCC, p. 280.

    Thank you for introduction Mr. Chairman.Good afternoon, ladies and gentlemen. Today I will present work on behalf of our design team from Circuit Research Lab at Intel Corporation and Saravanan who is now with Silicon Laboratories at Austin, Texas.

    This is the outline of my talk.First I will briefly describe integrated DC-DC converters.I will show you why we need a high-performance linear regulator.Next I will describe the concept of digital control, share the implementation details and measurements on a regulator test chip.And finally, I will conclude my presentation.

    In 2004, we demonstrated a DC-DC converter built on a 90nm CMOS process that operates at 100s of MHz with efficiency between 80 and 87.7%.You may wonder why would anybody want to run a converter at 100s of MHz especially since the switching losses increase with frequency.The main reason is that as the frequency goes up the the values of inductors and capacitors decrease and so does their physical size.For example, the inductors in this converter were between 3.6 and 36 nH in 0402 footprint and they did not use any magnetic core.Unfortunately this converter has a serious limitation.

    This is a schematic of one of the phases of the converter shown on the previous slide.The input voltage VIN is used for biasing of the bridge drivers as well as the bridge transistors connected to the inductor.To prevent damage of the gate oxide the input voltage must be less than 1.2 to 1.4V in this 90nm CMOS process.Hence the range of applications of such a converter is severely limited.

    One way to alleviate this problem is to cascode the bridge transistors and stack the drivers as was shown in an ISSCC paper two years ago.This scheme enables doubling of the converter input voltage while limiting the stress across the gate oxide.For this scheme to work the drivers and the inner bridge transistors have to be biased in the middle between VIN and ground.The bridge transistors are large to reduce resistive loss. When the drivers switch they produce huge currents on the center rail.This paper describes a linear regulator that generates the center rail from the input voltage that can be up to twice the process voltage.The regulator has to be of a push-pull type because the bridge drivers can both sink and source current.Let us derive the specifications on the linear regulator.

    In the chip described in this paper, we implemented two systems, one that stacks two domains of logic, delivering power at 2Vdd, and a second that stacks three domains of logic, delivering power at 3Vdd. The bottom multiplier in the 2vdd system has logic running between vdd and 0, the top multiplier has logic running between 2vdd and vdd. For the two multipliers to communicate, we need level shifters to translate logic between domains. In the 3Vdd system, similar level shifters are required to interface between the three stacked domains. We now consider the design of the level shifter and linear regulators in more detail.Consider a DC-DC converter with 2.4V input voltage, 1.2V output voltage and 10A of output current.After optimizing the bridge transistor sizes for best efficiency we found that the drivers produced current spikes of up to 16A in a single-phase configuration.In a 16-phase configuration with staggered switching times the current spikes dropped down to 1A.Now let us look at the linear regulator that should bias these bridge drivers.The input voltage is 2.4V. The regulator always generates of VIN which is 1.2V in this case.It has to support current of the bridge drivers in the 16-phase mode of 1A.The variations on the center rail should be limited to 10% or 0.12V.The quiescent-current of the linear regulator should not degrade the DC-DC converter efficiency by more than a percent.For a 1.2V/10A converter considered here the quiescent current should be 25mA or less.Mainly due to oxide leakage the available decoupling capacitance was 2.4nF.What are the implications on the design of such a linear regulator.In the past, we have used a figure of merit that is a product of the normalized quiescent current and the response time.The lower the figure of merit the better the regulator performance.Often times same circuit can be sized for either high quiescent current and fast response or low quiescent current and slow response.To the first order this figure of merit removes the dependency on sizing and serves as a single performance metric of a given regulator topology.Normalized quiescent current is the ratio of the quiescent current divided by the rated maximum output current.Response time is given by the charge that needs to be stored on the output decoupling capacitor divided by the applied current step.By using the specification from the previous slide we found that the required figure of merit is 7.2ps.The best figure of merit that we could find was 22ps and this indicated a 3X performance gap between what we needed and what was available.Let us look at speed-power limitations of prior linear regulator topologies.

    Traditional linear regulators use a single large output device.The output current is adjusted by gate voltage driven by an analog buffer or sometimes directly by the error amplifier.When the load changes the response time depends on how fast the analog buffer can charge and discharge the gate.For class A buffers the speed is proportional to the quiescent current of the buffer and therefore the quiescent current of the regulator.A class AB buffer improves the slew rate for a given quiescent current. Unfortunately, analog class AB buffers utilize a local feedback loop which degrades the overall stability and ultimately limits the achievable response time.

    We propose a topology that alleviates the speed bottleneck due to driving of the output device.It is well known that digital inverters can rapidly charge or discharge load capacitance.Yet they consume little power when idle.Since the output of a digital inverter has only two levels it cannot be used to modulate the gate voltage of the output device.We replaced the single large output device by 16 smaller devices in parallel effectively building a thermometer-code D/A converter.To produce the thermometer code we added a simple flash A/D converter after the error amplifier.If the output voltage drops, the A/D converter will produce a code proportional to the error and the D/A converter will supply output current proportional to the error voltage.

    This slide shows a complete schematic of the half-rail push-pull linear regulator.The upper and the lower domain accomplish pull-up and pull-down operation, respectively.On the left, you can see two self-biased inverters connected in a cascode.The voltage on the link between the inverters is one half of the input voltage and serves as the reference for the output.The actual references for the domains are set by the trip points of either of the two inverters.Since the two domains are similar let us focus on the operation of the pull-down domain.The error amplifier contains two inverters with controlled gain.One of the inverters is skewed which is eqivalent to adding an offset voltage to the input.The skew between the amplifiers produces a 240mVdrop across the resistive network.The supply voltage of the amplifier inverters is derived from the output and not from the reference.Fluctuations in VOUT will vary the trip points of the inverters. Amplified fluctuations are coupled to the resistive network and the comparator inverters.The higher the common-mode voltage on the resistor network the larger the number of comparators that trip and the larger the output current.More details on the operation can be found in the paper.Note that this circuit relies on good matching of trip points of the inverters used in the reference generator, amplifiers and the A/D converter comparators.To guarantee that the inverters are matched we designed a simple template cell with one PMOS and one NMOS transistor.This cell is complete with interconnects in metal 1 and 2.By adding a few short connections to this cell we can impement any of the inverters shown in the previous schematic.At the same time we guarantee that the layout differences are minimal.

    This slides shows the various types of inverter cells.Cell A is an inverter with its input and output shorted such as the one used in the reference generator.Cell B is an inverter with its input connected to the bottom metal 1 segment.Cell C is similar to cell B only the input is connected to the top metal 1.Cell D contains separate PMOS and NMOS devices that are used for skewing of the amplifier inverters.Cell E is used for skewing of the inverters that control gain of the amplifiers.Apparently, the cells look nearly identical.

    This slide shows the floorplan of the small-signal portion of the linear regulator that requires inverter matching.Each row of cells corresponds to one of the 16 taps.The various types of inverters are indicated by different fill patterns.Some of the inverters were built out of many inverter cells in parallel.Those cells were spatially interleaved with the cells of other inverters.

    The linear regulator was manufactured on a 90nm CMOS process.The test chip contained an on-die load circuit to facilitate measurements of step response.The regulator occupies 506 times 60 microns.The layout shows the small signal section in the middle and the D/A converters for pull-up and pull-down domains on either side.At 1A load the average current density is 33A/mm2 but since only one of the domains is active at any given time, the current density in the active domain is as high as 66A/mm2.

    This slide shows the measured input-output characteristic.The output voltage would ideally be 50% of the input voltage but due to NMOS body bias of the pull-up domain this is not the case.As explained in the paper our application actually benefits from this slight mismatch.

    This slide shows the measured output characteristic.As the regulator is loaded by up to 1A in either direction, the output voltage drops proportionately but remains within 100mV of the unloaded value.A small dead-band guarantees that the pull-up and pull-down domains do not activate at the same time.

    The step response was measured under 1A load steps generated by the on-chip load.The regulator maintains the center rail within 120mV.Resistive response guarantees that the droop window is met for any load current waveform within 1A.

    We compared performance of our regulator to a regulator published at this conference last year.The current efficiency for this converter is 97.5% resulting in 3.64X better quiescent current for same output rating.The response time is 28% worse for this work resulting in the overall figure of merit improvement of 2.84 times.

    Digital buffers are more power efficient than analog buffers.Improvement in the figure of merit by nearly 3X was necessary in order to meet the requirements of the DC-DC converter.With digital buffering of the output device the bottleneck has moved from the analog buffer to the error amplifier.In this topology the quiescent current is dictated more by matching requirements rather than speed.