A Linear Regulator with Fast Digital Control for Biasing of Integrated

DC-DC Converters

A-VLSI class presentationAdopted from isscc

Presented by:

Siamak Mehrnami

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Outline

● Integrated DC-DC converters

● Linear regulator with digital control

● Implementation details

● measurements

● Conclusions

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Integrated DC-DC Converters

● Demonstrated at 100MHz, η=87.7%

Ref.: [3]

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Problem: Low Input Voltage

● The CMOS process limits the DC-DC converter input voltage to 1.2-1.4V

Ref: [1]

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Doubling of Input Voltage Range

● VIN is across two transistors in series

● Need a ½-rail linear regulator

Ref.: [4]

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High tension power delivery through implicit voltage conversion ref:[2]

16-by-16multiplier

16-by-16multiplier

Linearregulator

1 to 3levelshift

3 to 1levelshift

3VDD

Vhigh

Vlow

1-logic 3-logic 3-logic 1-logic

16-by-16multiplier

1 to 2levelshift

2 to 1levelshift

1-logic 2-logic 2-logic 1-logic

Linearregulator

Vhigh

Vlow

1-logic 1-logic

2VDD

VDD

2VDD system 3VDD system

16-by-16multiplier

16-by-16multiplier

Linearregulator

1 to 2levelshift

2 to 1levelshift

2VDD

Vhigh

Vlow

1-logic 2-logic 2-logic 1-logic

VDD

1-logic 1-logic

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Auxiliary Regulator Requirements

● Calculate Figure of Merit– single value to measure performance Ref:[1]

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Auxiliary Regulator Figure of Merit

● Best known regulator had FOM=22ps– Rajapandian, et al., 2005 ISSCC, p. 298

● Need same speed at 3X lower power ref:[1]

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Traditional Linear Regulators

● Class-A buffer has poor slew rate● Class-AB buffer degrades stability ref:[1]

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Regulator with Digital Control

● Digital buffers (inverters) are perfect class-AB circuits, fast and low power

ref:[1]

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Push-Pull ½-Rail Regulatorref:[1]

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Template Cell Design for Matching

ref:[1]

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Customized Inverter Cells

ref:[1]

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Floorplan of Matched Invertersref:[1]

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Regulator Test Chip in 90nm CMOSref:[1]

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Input-Output DC Characteristicref:[1]

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Output DC Characteristicref:[1]

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Load Step Response (5ns/div)ref:[1]

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Performance Comparisonref:[1]

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Conclusions

● Digital buffers (inverters) are more power-efficient than analog buffers

● Achieved 3.64X lower quiescent current at 28% slower response– FOM is 2.84X better than the prior art

● The power bottleneck moved from the analog buffer to the error amplifier– matching requirements influence

transistor sizes and the quiescent current ref:[1]

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References:● 1-P.Hazucha, “A Linear Regulator With

Fast Digital Control For Biasing Integrated DC-DC Converters” ISSCC dig. tech. papers 29.2 feb.2006

● 2-S. Rajapandian, et al., “High-Tension Power Delivery- Operating 0.18µm CMOS Digital Logic at 5.4v,” ISSCC dig. Tech. papers,pp.298299,Feb., 2005 [page 6]

● 3- Hazucha, et al.,2004 VLSI Symposium, p. 256.

● 4-Xiao, et al.,2004 ISSCC, p. 280.