A 3–10 GHz Ultra Wideband Receiver LNA in 0.13 $$\mu $$ μ m CMOS

$: A 3–10 GHz Ultra Wideband Receiver LNA in 0.13 $$\mu $$ μ m CMOS$
Circuits Syst Signal ProcessDOI 10.1007/s00034-013-9726-9

A 3–10 GHz Ultra Wideband Receiver LNA in 0.13 µmCMOS

Xubo Wang · Anh Dinh · Daniel Teng

Received: 03 May 2013 / Revised: 09 December 2013© Springer Science+Business Media New York 2014

Abstract A fully integrated low-power, low-complexity ultra wideband (UWB) 3–10 GHz receiver front-end in standard 130 nm CMOS technology is proposed forUWB radar sensing applications. The receiver front-end consists of a full UWB bandlow-noise amplifier and an on-chip diplexer. The on-chip diplexer has a 1 dB insertionloss and provides a −30 dB isolation. The diplexer switch was co-designed with thereceiver input matching network to optimize the power matching while simultane-ously achieving good noise matching performance. The receiver low-noise amplifierprovides a 3–10 GHz bandwidth input matching and a power gain of 17 dB. Theoverall receiver front-end consumes an average power of 13 mW. The core area of thetransceiver circuit is 500 μm by 700 μm.

Keywords Ultra wideband · Low-noise amplifier · UWB receiver front-end ·Diplexer.

1 Introduction

In recent years, ultra wideband (UWB) research has shown great potential forshort-range communications and radar-sensing applications, driven by the persistentdemand for inexpensive, low-complexity, and highly integrated System-on-Chip (SoC)

Xubo Wang (B) · Anh Dinh · Daniel TengDepartment of Electrical and Computer Engineering, University of Saskatchewan, 57 Campus Drive,Saskatoon, SK, Canadae-mail: [email protected]

Anh Dinhe-mail: [email protected]

Daniel Tenge-mail: [email protected]

Circuits Syst Signal Process

designs. The free UWB spectrum allocated by the Federal Communications Commis-sion (FCC) in February 2002 has made UWB systems more easily compatible withtheir various applications [6]. Also, the evolutionary trend of CMOS technology tendstoward rapid reduction in supply voltage and dynamic power consumption for RFintegrated circuits. The unique features of the UWB signal, such as millimeter rangewavelength, high resistance to multipath fading, fine time resolution, and low powerconsumption, make it a popular technique for small target detection and sensor com-munications [7,13,17,18].

Among many building blocks in the UWB radar and UWB sensor systems, theUWB low-noise amplifier (LNA) plays a vital role because the quality of the signalthat is received and pre-amplified is a critical factor in the overall system performance[1]. A UWB LNA must operate with an acceptable gain and have an input matchingto a 50 � antenna over the UWB frequency band. A truly integrated UWB SoCsolution requires the seamless integration between the transmitter, the antenna, andthe receiver. Implementation in a standard CMOS process allows integration of the RFfront-end with the baseband digital blocks. The most recently reported UWB CMOSradar transceivers in [4,5,20] employ a simple common-gate amplifier as the first-stage LNA in the receiver without wideband impedance matching. The receiver LNAsin [4,5] covers only the lower UWB band with a low forward gain and [20] has ahigh noise figure. The reported receivers use two different ports for one transmittingantenna and one receiving antenna or separated diplexer built on a different substrate.To date, none of the reported UWB receivers have been fully integrated with a diplexeron the same chip to achieve the complete seamless integration.

In a UWB system, the separated LNA and diplexer laminates and the bondingwires between them may cause large distortion and loss to the signals. To reduce thesignal path loss between two separate laminates or substrates and improve the receiversystem performance margin, integration of the diplexer and the receiver front-endonto the same chip is becoming an inevitable trend in the SoC era. A co-designedantenna diplexer and LNA on the same substrate with a careful UWB frequencyimpedance matching not only increases the integration level and reduces costs, butalso greatly improves the overall receiver system performance. This paper proposes aUWB receiver front-end that integrates a diplexer with a full-band LNA to pre-selectand pre-amplify the received UWB signals. Figure 1 shows the block diagram of aUWB radar transceiver. The UWB transmitter and receiver share the same antenna

Mixer/Baseband

UWBTransmitter

UWBAntenna

UWBLNA

UWBDiplexer

Fig. 1 Block diagram of the receiver front-end in a UWB radar transceiver


load

R

loadRfb

load

VinVin

Vin

VoutVoutVout

load

(a) (b) (c)

(d)

Z0 Z0 Z0

delay

Vin

Vout

load

Ls

Vin

Vout

WidebandNetwork

(e)

bias

Z0

Z0 Z0Z0 Z0

Fig. 2 Different UWB LNA topologies

through a UWB band diplexer. The received UWB signal is then processed by thebaseband energy detection circuits in the receiving path.

The paper focuses on the design and implementation of an integrated UWB receiverfront-end in the standard 130 nm CMOS technology and is organized as follows. InSect. 2, the design topology is discussed. In Sect. 3, the receiver front-end circuit designapproach and the design issues are analyzed and discussed. The design implementationis presented in Sect. 4. Measurement results from the fabricated receiver front-end arepresented and discussed in Sect. 5. Comparisons with previously published works arealso presented in Sect. 5 and the conclusions are drawn in Sect. 6.

2 Receiver Front-End LNA Design Topology

There is a number of recently published works on CMOS UWB LNAs using differentcircuit topologies for UWB receiver first-stage amplifier design [2,3,8–12,14–16,19].These include distributed, resistive feedback, balanced, common gate, and inductivedegeneration structures. Each topology has its own advantages and disadvantages fora specific application. This section reviews each of the topologies and then introducesthe proposed receiver front-end.

The resistor-terminated amplifier, as shown in Fig. 2a, is the simplest circuit topol-ogy that can achieve wideband input matching while providing simultaneous wideband


gain. The major drawback of this topology is that the termination resistor R introducesan additional 3 dB of noise. In addition, as the frequency increases, both noise per-formance and gain are badly deteriorated. Figure 2b shows the circuit structure fora resistive shunt-feedback amplifier. This configuration, when applying a feedbackresistor Rfb, has the same input impedance and output impedance when the sourceimpedance Rsource and the load impedance Rload are equal. Both good input and outputmatching are achieved in a very wideband [3,14,15]. At RF frequencies, the Millereffect from the gate-drain capacitance Cgd, together with Rfb, moves the dominantpole to a lower frequency and significantly degrades the gain. This dominant polecan be reduced by a neutralization technique at the cost of an additional complexcircuit and some noise and power headroom. In terms of noise performance, thistopology is not the best candidate because Rfb and a possible degeneration resis-tor contribute a large amount of noise. The design in [15] uses a transformer inthe feedback loop to reduce noise figure at the cost of increasing circuit complex-ity. Another drawback of the shunt-resistive feedback topology is that the feedbackloop is highly sensitive to the resistor value and to the parasitic capacitances Cgdand Cgs. Since the shunt feedback controls the bias, the gain, and the input/outputimpedances, the feedback loop values must be precisely controlled. The on-chip resis-tor process variation can greatly affect the performance of the shunt-resistive feedbackamplifier.

Another very attractive UWB LNA topology is the common-gate configuration, asshown in Fig. 2c. The real part of the input impedance of the common-gate structure,seen at the source, is approximately constant at 1/gm. This configuration can easilyachieve a wideband input matching if 1/gm is adjusted to match the signal sourceimpedance RS. However, special techniques must be employed to increase gm in [8]in order to have a high amplification gain at the cost of a large die area. The majordrawback is the degraded noise figure at frequencies in the GHz range with a moderategain [11].

The distributed amplifier structure, as shown in Fig. 2d, can achieve high gain fora high bandwidth [10,19]. This topology embeds the input capacitance at the gate ofeach transistor into a LC network that corresponds to a transmission line. Since thecharacteristic impedance Z0 is equal to the source impedance, the input signal sees eachnode as a matched load rather than as a frequency pole. Ideally, as the transmission linehas an infinite bandwidth, an extremely high bandwidth is achieved and the output polealone dominates the bandwidth. However, this structure uses the lumped LC networkswhich is very expensive in terms of chip area for a 50 � input matching. The on-chipinductor has a low-quality factor and high losses which lead to poor noise performance.Since the LC transmission line has delay, the distributed amplifier output is delayedfrom each amplifier stage. Also, the total power consumption and the chip area of thecomplete circuit are inevitably large [10,19].

Figure 2e shows the inductive degeneration common-source amplifier structure.The degenerative inductor LS introduces a real part impedance at the transistor gate.The inductive component at the gate is cancelled by the parasitic capacitance Cgs,leaving only the real part of the input impedance, Z in. Z in can be derived from thesmall signal circuit as


Vdd

Antenna

RF out

M5

M6M1

M2M3

Ls

Lg

L1 Rb

C1C2

C3

L2

C4

Ld

Rd

L3

R3

M7

Cgd5

Cgd7

X

Diplexer andimpedance matching

co-designed 2nd ordernetwork

Rx_EN

Tx_EN

Rx_EN

Bondingwire

Transmitter matching

L7C7

L8C8

M8

Fig. 3 Schematic of the proposed UWB receiver front-end with a UWB band diplexer

Z in = 1

sCgs+ sLs + gm

Cgs· sLs

s+ sLg = s(Lg + Ls) + 1

sCgs+ ωT Ls (1)

where the cut-off frequency, ωT , is defined as ωT = gmCgs

. The gate-drain parasiticcapacitance Cgd will introduce the Miller effect which will be discussed in the nextsection. Input impedance matching only occurs at the resonance frequency of

ω0 = 1√

(Ls + Lg) · Cgs(2)

To expand this narrow-band input matching, a wideband matching network is pro-posed at the gate to achieve an input matching from 3 to 10 GHz. Compared to othertopologies, the common source configuration offers the best choice in terms of designperformance and robustness.

3 Design Techniques

The proposed receiver front-end LNA, integrated with the UWB band antenna diplexer,is shown in Fig. 3. The LNA stage (M1 and M2) uses a shunt-peaking cascode commonsource configuration with a degeneration inductance as the amplifier core. The NMOStransistors M5 and M7 are connected as a shunt switch to control the incoming RFsignal path to the LNA input. This section focuses on the design approach for theintegrated receiver front-end.

3.1 Antenna Diplexer Input Matching

When designing for UWB frequency matching, the choices are limited to either But-terworth or Chebyshev network. The Chebyshev network provides a steeper roll-off


Sou

rce Load

L1

L2

C1

C2

Fig. 4 Second-order Chebyshev network

Table 1 Nominal input network component values for Chebyshev and Butterworth structures

Type n L2 (nH) C2 (fF) L1 (nH) C1 (fF)

Chebyshev 2 1.787 335 0.619 869

Butterworth 2 2.2 350 0.65 1320

than the Butterworth counterpart, with lower insertion loss, at a cost of the in-bandripple. For the receiver front-end, the input reflection coefficient � can be expressedin terms of the pass band ripple Ripple as

|�|2 = Ripple − 1

Ripple(3)

Equation (3) shows that for a reflection coefficient of −10 dB or smaller, the rippleof the front-end matching network should be smaller than 1.11 or 0.915 dB on alogarithmic scale.

A second-order Chebyshev input network is shown in Fig. 4. C2 and L2 form a shuntconnected branch. Both the source and the load are 50 �. The matching network isconstructed from a low-pass to band-pass filter transformation with de-normalizationusing the normalized low-pass coefficients with a ripple of 0.1 dB. The bandwidth isset from 3.0 to 10.6 GHz, with a center frequency of 6.8 GHz.

Table 1 shows the nominal structure values for the second-order Chebyshev inputnetwork and the second-order Butterworth input network. The Chebyshev structureforms a good compromise between area and power consumption. For the Butterworthstructure, C1, which will be replaced by the gate-source capacitance, is calculated tobe 1.32 pF. This capacitance value requires a large gm to achieve a moderate gain; thisis not acceptable in a high-frequency design.

In the schematic of the proposed structure in Fig. 3, the parasitic capacitances oftransistors M5 and M7, C3, Cgs1, the gate, and the source inductors form a second-order shunt-series Chebyshev matching network to match the 50 � antenna impedancein the 3.1–10.6 GHz UWB band. The parasitic capacitances Cgd5 + Cgd7 and L1form the shunt branch corresponding to C2 and L2 in Fig. 4, andCgs1,Lg, and LS areembedded in the series branch corresponding to C1 and L1 in Fig. 4. The capacitorC3 is added to increase the design freedom. The passband ripple is designed to be 0.1dB, the center frequency is located at 6.8 GHz, and the frequency span for S11< −10dB is designed to be from 3 to 10.6 GHz.


For the LNA core local matching network, the input impedance seen from thetransistor M1 gate inductor Lg is shown in Eq. (1), where the cut-off frequency ωT

is equivalent to the gain-bandwidth product and is a function of gm1 and the nodaldominant capacitance. The degenerative inductance LS introduces a real part to theinput impedance, whileLg and (Cgs1 + C3) dominate the imaginary part of the inputimpedance. At the resonance frequency, Lg and (Cgs1 +C3) cancel each other and theimpedance appears to be a purely resistance, which is dominated by gm1/(Cgs1 + C3)

and LS. By choosing suitable values of gm1, C3, and LS, the input impedance canbe matched to 50 �. This local matching network is embedded inside the full UWBband-matching network to achieve a full band resonance and 50 � matching.

At GHz frequencies, the non-quasi static gate resistancerg,NQS and the parasiticgate resistance RG begin to play an important role. Therefore, the real part of the inputimpedance becomes

Re(Z in) = rg,NQS + RG + ωT LS (4)

rg,NQS and RG are sensitive to bias voltage. The simulated rg,NQS + RG is around 8 �

under a bias voltage of 0.59 V at 6 GHz. In the design, the gate resistance rg,NQS andRG are compensated for by reducing LS to give Re(Z in) = RS.

A series NMOS switch and a shunt NMOS switch are used on each side of theantenna port. The two switches are turned on and off in a complementary fashion.This series-shunt connection is a compromise between the insertion loss and portisolation. Knowing that the typical on-chip inductor Q factor is approximately 10,the insertion loss of the diplexer with different switch sizes, including the impedancematching network, is plotted in Fig. 5a. The switch size with W = 120 μm has thelowest insertion loss. The switch with W = 40 μm has the highest insertion loss of 1dB but it achieves the maximum flatness inside the UWB band. Figure 5b shows theisolation plot for the various switch sizes. The switch with W = 40 μm apparently hasthe best isolation because of its small parasitic capacitance with a large resistance.

3.2 Gain Stage

In high-frequency CMOS design, the transistor transconductance gm becomes the keyparameter that governs the design tradeoffs. The stacked transistors M1 and M2 inFig. 3 form a cascode topology and provide the small-signal gain for the LNA. Themain role of transistor M2 is to reduce the Miller effect, improve the reverse isolation,and boost the intrinsic output impedance by a factor of gm2ro2. Since the currentsflowing through M1 and M2 are equal, the overall effective transconductance Gmis dominated by the amplifier transistor M1 and the transfer function H(s) of theimpedance matching network.

Gm can be derived as

Gm = iout

vs= gm1 H(s) = gm1

s(Cgs1 + C3)(sLs + sLg + Zs) + 1 + gm1sLs(5)

where Zs stands for ωT LS. The actual value of |H(s)| is less than unity because thegate-to-source voltage is less than the input voltage due to input network insertion


1 2 3 4 5 6 7 8 9 10 11 12-6

-5

-4

-3

-2

-1

0

1(a)Insertion Loss Curves vs. Frequency

Frequency (GHz)

Inse

rtio

n L

oss

(dB

)

W = 40um

W = 120um

W = 160um

W = 200um

W = 240um

2 4 6 8 10 12-70

-60

-50

-40

-30

-20

-10

0

Frequency (GHz)

Isol

atio

n (d

B)

Isolation Curves vs. Frequencies

W = 40umW = 80um W = 160umW = 240um

(b)

Fig. 5 a Insertion loss for switch transistors with W = 40 μm, W = 120 μm, W = 160 μm, W = 200 μm,and W = 240 μm, b Port isolation for switch transistors with W = 40 μm, W = 80 μm, W = 160 μm, andW = 240 μm

losses. Equation (1) has shown that

sLs + sLg + 1

s(Cgs1 + C3)= 0 (6)

Equation (5) is simplified to become

Gm = gm1 · 1

2Rss(Cgs1 + C3)(7)

The LNA voltage gain can be expressed as

AV = Vout′

Vin(s) ≈ −Gm · [(gm2 + gmb2)rO1rO2||(Rd + sLd)]

(1 + sωin

) · (1 + sωout

) · (1 + sωX

)(8)


where the input pole ωin is

ωin ≈ 1

50[Cgs1 + C3 + (1 + gm1

gm2)Cgd1

] (9)

the Vout′ is the voltage at the drain of M2. The output pole ωout is

ωout ≈ 1

Rd(Cgs3 + Cgd2)(10)

and the inter-stage pole ωX is estimated as

ωX ≈ 1

(1/gm2||rO1)(Cgs2 + Cgd1)(11)

To achieve a high bandwidth, transistor M1 is biased by a large VGS1 and its length Lis kept to a minimum. However, the overdrive voltage VGS1 − Vth should not exceed0.45 V to prevent the transistor entering the velocity saturation region. In this region,the transconductance gmsat becomes a function of the transistor width Cox, and themaximum channel electron velocity Vsat, and no longer increases with the drain current.

A cascaded common source amplifier is used as a high-frequency driver to drive a 50� output load. The source follower is a common choice at low frequencies. However,as the frequency increases to the GHz range, the output impedance Zout3 tends to reachthe input impedance Z in3, because the gate-source capacitance of M3, Cgs3, will shortboth the gate and the source. In this case, the output impedance value is in severalorders of magnitude higher than 50 �. This Cgs3 high frequency pass will degradethe gain to far below unity. Thus, at higher frequencies, the common source bufferappears to be a better choice for output impedance matching. The transfer function ofa common source buffer can be approximated as

Vout

Vin′≈ −gm3[(R3 + sL3)||50]

(1 + sωout

)(1 + 25 · CL · s)(12)

where Vin′ is the voltage at the gate ofM3, CL is the load capacitance, and the shuntpeaking inductor L3 contributes a zero to extend the bandwidth. Let 1/gm3 ≈ (R3||50)then the buffer exhibits a unity gain at high frequencies while achieving a 50 � outputmatching. The dominant pole of the overall gain transfer function is located at thedrain of transistor M3. Since this output matching buffer forms a voltage divider, thevoltage gain is 6 dB higher than the power gain.

3.3 Noise Analysis of the Receiver Front-End

The first receiver stage contributes most of the overall system noise. Figure 6a showsa simplified noise model of the proposed receiver front-end after application ofa Thevenin equivalent transformation. The noise of an independent drain load is


ind5

M1

Ls

Rb

C3

ind2ing1

iR

M5

M7 ind7

Lg

L1

M1

C3int

Vnt

(a) (b)

Fig. 6 Noise model of the receiver front-end

assumed. This model includes the LNA and the diplexer matching network for acomplete noise analysis. The main noise sources are the amplifier transistor M1 andthe switching transistors M5 and M7. Other noise sources are the equivalent thermalnoise from the biasing resistor Rb and the thermal noise of the low Q lossy on-chipintegrated inductors. The noise source of M1, which is the thermal noise of the channelresistor, can be represented by

i2nd = 4kT γ gd0� f (13)

i2ng = 4kT δgg� f (14)

where gg is expressed as ω2C2gs/5gd0. This is a frequency-dependent term. In other

words, ing2 is the induced gate noise at the non-quasi-static state. The noise componentsof the switching transistors M5 and M7 are solely represented by the channel noisecurrentind because each transistor’s turned-on state is a steady state.

The thermal noise sources can be replaced by an equivalent input correlated noisesource by bringing ind1 to the input gate of the transistor M1. The noise sources ind5and ind7 of M5 and M7, respectively, and the resistor noise are not correlated withing1, thus they can be superimposed into a single noise source, inT. The simplifiednoise model after superimposition is shown in Fig. 6b in which Rb is the biasingresistor.

i2nT =

[jω(C3 + Cgs1)

]2i2nd1

g2m1

+ i2ng1 + i2

nd5 + i2nd7 + 4kT � f

RTot(15)

v2nT = i2

nd

g2m1

+ [jω(LS + Lg + L1)

]2i2nT (16)

where RTot represents Rb and the loss of the inductors. The input noiseinT is decom-posed into two components: the correlated noise, inc, and the uncorrelated noise,inu,whereinc is composed of the correlated terms ofing1, the input-referred form of the noisecurrentind1, and ind5,7. The correlation admittance YC = GC + jBC can be expressed as


Yc = inc

vnt= jω(Cgs1 + C3) −

⎛

⎜⎜⎜⎝

jω(Cgs1 + C3)gm1c√

δ5γ

− 4kT γ gd05,7� f4kT γ gd01

gm1+ jωLs,g,1int

− 4kT � fRT vnt

⎞

⎟⎟⎟⎠

(17)

where the value of c is approximately 0.3 [11]. The transistors M5 and M7 are biasedin deep linear region, in which the values of γ5,7 are approximated to unity.

The equivalent noise resistance Rn and the noise transconductanceGu are definedand expressed as

Rn = v2nt

4kT � f≈ γ

gm1α+ ( jωLT )2

[( jωCT )2γ

gm1α+ δgg1 + 2gd05,7

](18)

Gu = i2u

4kT � f= δω2C2

gs1(1 − |c|2)5gd01

(19)

where α = gm/gd0, and CT = Cgs1 + C3. The noise factor after expansion and simpli-fication is derived as

F = 1 + Rs

⎧⎨

⎩δω2C2

T (1 − |c|)2

5gd01+ A

⎡

⎣γ (1+ω4C2

T L2T γ )

gm1α+

ω2L2T (δgg1 + 2gd05,7)

⎤

⎦

⎫⎬

⎭(20)

where

A ≈√√√√g2

m1 + ω2C2T

(

1 − gm1|c|√

δ

5γ

)2

(21)

The simulated noise figure plot of the overall LNA front-end is shown in Fig. 11 wherethe simulated minimum noise figure is 3.8 dB.

4 Implementation of the Receiver Front-End

The UWB receiver diplexer and the LNA are implemented in the 130 nm seven-metal-layer CMOS technology process. The on-chip capacitors were built using metal–insulator–metal structure. The spiral inductors were implemented on the top metallayer with a shield ground plane.

The LNA stage and the output buffer stage draw a total current of 11 mA fromthe 1.2 V power supply. The diplexer switch sizes of transistors M5, M6, and M7are chosen to be 40 μm for a reasonable compromise between insertion loss andisolation. The 200 μm width of M1 is chosen for noise optimization and gain. Thewidth ofM2is chosen as 80 μm as a compromise between bandwidth and noise. Thevoltage headroom is set by the loadRd, which has a value of 60 �.

For the buffer amplifier, the output introduces a large parasitic capacitance; withoutthe shunt-peaking inductor, the gain will drop at high frequencies. An on-chip shunt-peaking inductor was considered initially. However, the low-quality factor of the on-


UWB RadarReceiver Front-end

RF Input

Vdd

Gnd

RF Output

Fig. 7 ESD protection diode string at RF I/O

Table 2 Component values ofthe receiver for 130 nm CMOS

Parameter Actual value Nominal value

LS in Fig. 3 1.069 nH 0.619 nH

Lg in Fig. 3 1.6 nH

L1 in Fig. 3 1.313 nH 1.787 nH

C3 in Fig. 3 610.3 fF 869 fF

C2 in Fig. 4 Cgd5 + Cgd7 335 fF

C1/C2 in Fig. 3 Coupling capacitors N/A

chip inductor results in the same issue: the signal gain is reduced because the equivalentRp = ωL Q, and Rp is proportional to the gain. It is desirable to use high Q inductorswherever possible. Since the shunt-peaking inductor in the buffer stage is directlyconnected to an output pad, the output buffer shunt-peaking inductor L3 can be realizedusing the bonding wire inductance. The bonding wire can be regarded as a high Q (20–50) inductor of a few nH (approximately 1 nH per 1 mm of bonding wire). In orderto reduce the gain loss at the inter-stage node of the two transistor M1 and M2 atfrequencies in the upper UWB band, an inter-stage matching scheme using inductorL2 and C4 is added.

The buffer stage uses a separate pad Vdd_buffer for wire bonding from 1.2 V to thebuffer core. The buffer core M3 size is set at 120 μm. All transistors in the designare set to a minimum length of 0.13 μm to produce an optimized cut-off frequency.The similar diplexer input matching network for the transmitter side is not presentedin this paper.

To protect the UWB receiver front-end from potential ESD damage during waferionization, handling and testing, shallow trench isolation diode strings were added atthe RF signal input/output to protect the receiver core. This protection scheme is shownin Fig. 7. The matching network is re-optimized using a Smith chart impedance circleto compensate for the matching frequency shift caused by the diode strings. Table 2shows the finalized component values for the receiver diplexer–LNA matching networkafter re-optimization.

The values in the table are the actual values extracted from the layout. Ls andLghave a total value of 2.669 nH. The switch transistor parasitic capacitance Cgd5 +Cgd7of about 300 fF is to imitate C2 in Fig. 4. The value of C3 is reduced from 869 fF to


Fig. 8 Micrograph of thereceiver front-end die

610 fF because of the gate-source capacitance of transistor M1 in Fig. 3. The variouscorners of SS (slow–slow) and FF (fast–fast) with temperature at −20 ◦C and +80 ◦Cand 20 % component value sweeping combinations have been run. The maximumdiscrepancy of the receiver front-end gain under these corners is within 3 dB. Underthe worst-case scenario, the front-end LNA has a 20 % shrinking in bandwidth.

5 Measurement Results

The receiver front-end was fabricated using the IBM 130 nm CMOS technology andpackaged in a high-frequency cavity and test fixture for measurements. The chipmicrograph of the receiver front-end is shown in Fig. 8. The overall die area, excludingthe analog I/O pads, is 0.5 mm2. The receiver LNAs were measured under a powersupply voltage of 1.2 V. An Agilent network analyzer and spectrum analyzer wereused to perform the measurements.

Figure 9a shows the measured and simulated input matching results of the receiverfront-end. Compared to the simulated S11, the measured S11 is shifted to a lowerfrequency because of the parasitic loss that was introduced. A minimum matching levelof −14 dB is achieved over the entire UWB band. Figure 9b shows the measured andsimulated gains of the receiver front-end under different bias currents. The maximumpower gain achieved in the UWB band is 17 dB, and the bandwidth is 3.3–9.9 GHz.The power gain of 17 dB is measured from the antenna input to the output of theLNA buffer. Figure 10a shows the measured output matching of the receiver front-endand the measured inverse isolation. A good output matching of −10 dB and a reverseisolation of −22 dB are achieved. The simulated and measured forward group delaysare shown in Fig. 10b. The forward group delay measures the signal distortion in theUWB band. This is of particular interest for radar applications across the entire UWBband. The measured average group delay is 400 ps. The sharp variations of the groupdelay outside the 3.1–10 GHz band can be the result of the un-matched impedance ofthe pads outside the UWB frequency band, introducing further signal distortions.

The measured overall noise figure plot of the complete LNA front-end is shown inFig. 11. The minimum noise measured in the UWB band is 4.8 dB. The input-referred


Fig

.9a

Mea

sure

dan

dsi

mul

ated

S11,

bM

easu

red

and

sim

ulat

edS2

1of

the

rece

iver

fron

t-en

d


Fig

.10

aM

easu

red

S22

and

S12,

bM

easu

red

forw

ard

grou

pde

lay

ofth

ere

ceiv

erfr

ont-

end


Fig. 11 Simulated and measured noise figures for the receiver front-end

1 dB compression curve of the receiver front-end is shown in Fig. 12a. The test wasperformed at 6 GHz. The 1 dB compression point (IP1) is −13.1 dBm. Figure 12bshows the plot of the third-order intermodulation (IIP3) curve of the receiver front-endat 6 GHz. The IIP3 intercept point is −1.53 dBm.

The performance of the complete receiver front-end is tabulated and is comparedto the recently published values for UWB LNAs in Table 3. A figure-of-merit (FOM)is used to compare the performance between this work and the other published work.The FOM is defined as:

FOM = GBW

(NFmin − 1) · Pdc · |IIP3| (22)

where GBW is the product of the absolute value of the forward gain S21 and thebandwidth, whilePdc is the power dissipation in mW. NFmin is the minimum noisefigure of the LNA.

The UWB receiver LNA front-end provides comparable performance at low powerconsumption while achieving a good matching and high linearity. The proposed designin this work exhibits higher FOM compared to other LNAs, except the design in [15],which is a reactive-feedback LNA with a complex circuit due to the use of an on-chiptransformer. The design in [10] and [19] are the LNAs with distributed structure, whichconsume large die area and high power dissipation, making them not a good candidatefor low-power UWB system integration.

6 Conclusion

A fully integrated UWB receiver front-end with a diplexer implemented in the main-stream 130 nm CMOS process is presented in this paper. The on-chip diplexer hasa 1 dB insertion loss and a −30 dB isolation. This diplexer isolation is competentfor a UWB transceiver, which normally is a gated system. The diplexer switch was


-13-8-32712

1dB

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Table 3 Summary of UWB overall receiver front-end performance and comparison with previously pub-lished UWB LNAs

Design Technology S11 (dB) Gmax(dB)

BW (GHz) NFmin(dB)

IIP3(dBm)

Power(mW)

FOM

This work(withdiplexer)

130 nm CMOS <−14 17 3.5–10 4.8 −1.53 13 1.462

[3] 130 nm CMOS <−7.3 12.4 3.1–10.6 3.7 −3.8 14.4 0.629

[15] 130 nm CMOS <9.9 16.5 3.1–10.6 2.8 −5.1 9 1.498

[10] 180 nm CMOS <−8 8.1 0.6–22 4.3 N/A 52 N/A

[19] 130 nm CMOS <−12 16 1–10.6 4.5 N/A 26 N/A

[2] 180 nm CMOS <9.9 9.3 2.3–9.2 4.0 −6.7 9 0.355

[9] 130 nm CMOS <−8.3 11 2–9.6 4.8 −7.2 19 0.161

[8] 130 nm CMOS <−10 14.5 3.1–10.6 4.5 −4.8 7 0.925

[16] 180 nm CMOS <−10 14 3.4–11 4.7 −5.3 30 0.181

[12] 180 nm CMOS <−9.5 13.2 3.1–10.6 4.5 −1.4 28 1.010

[14] 90 nm CMOS <−5 24.4 4–8 2 −7.7 9.2 1.378

co-designed with the receiver input matching network to optimize for power matchingwhile achieving good noise performance. The use of the UWB diplexer into a receiverLNA on the same substrate greatly improves transmission loss and reduces chip area.The integration is very challenging because more parasitics are introduced into thecircuit, potentially resulting in degradation of the LNA performance and bandwidth.This design co-matches the diplexer and LNA matching network to overcome the extraparasitics, achieving a wideband input matching gain.

For the receiver, an overall noise figure of 4.8 dB was measured and the front-endachieves a full band matching with a maximum power gain of 17 dB. Good outputmatching and reverse isolation were also demonstrated. The complete receiver front-end consumes an average power of 13 mW. Good noise figure performance; goodwideband matching; gain, high level of integration; and low cost of the proposedUWB receiver front-end make it a highly competitive SoC solution for low-powerUWB transceivers.

Acknowledgments The authors would like to thank CMC Microsystems in Canada for the design toolsand fabrication. This project is supported by the Natural Sciences and Engineering Research Council ofCanada under Strategic Project Grant number STPGP 350545.

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3. P.-Y. Chang, S.S.H. Hsu, A compact 0.1-14-GHz ultra-wideband low-noise amplifier in 0.13-μmCMOS. IEEE Trans. Microw. Theor. Tech. 58(10), 2575–2581 (2010)


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16. S.M. Rezaul Hasan, Analysis and design of a multi-stage CMOS band-pass low noise pre-amplifierfor ultra-wide-band RF receiver. IEEE Trans. VLSI Syst. 18(4), 638–651 (2010)

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A 3–10 GHz Ultra Wideband Receiver LNA in 0.13 $$\mu $$ μ m CMOS

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