A 2.98nW Bandgap Voltage Reference Using a Self-Tuning Low Leakage Sample and Hold Yen-Po Chen, Matt Fojtik, David Blaauw, Dennis Sylvester

University of Michigan, Ann Arbor, MI ypchentw@umich.edu, mfojtik@umich.edu, blaauw@umich.edu, dmcs@umich.edu

Abstract A novel low power bandgap voltage reference using a sample and hold

circuit with self-calibrating duty cycle and leakage compensation is presented. Measurements of 0.18μm CMOS test chips show a temperature coefficient of 24.7ppm/°C and power consumption of 2.98nW, marking a 251× power reduction over the previous lowest power bandgap reference.

Introduction A precision voltage reference that is insensitive to process, voltage, and

temperature fluctuations is a key building block in mixed-signal and analog systems. Given a recent emphasis on low-power battery-operated systems, including wireless sensors, ultra-low power voltage references are needed. A number of low power references use different Vth devices [1][2] while the output voltage of the design in [3] is equal to Vth. However, Vth can vary substantially (particularly across device flavors), and is highly technology dependent. The output voltage of bandgap references are set by fundamental parameters and therefore exhibit lower process spread. However, their power consumption is higher; a low power bandgap reference presented in [4] consumes 1μW, which is large relative to recent ultra-low power microsystems [5] with nW power budgets. New structures for bandgap references have been developed [6], but power remains in the μW range.

Proposed Technique This paper presents a low power reference that consumes 2.98nW at

room temperature in 0.18μm CMOS. The reference uses a sample and hold (S&H) technique where the bandgap is duty-cycled to save power consumption. A low duty cycle (0.003% at 27°C) is achieved through three methods: 1) Sampling, holding and restoring the internal node voltages of the bandgap reduces the awake time by 11.5×; 2) Equalizing the voltage across the S&H switch using a subthreshold opamp, increasing the allowable sleep time by 1000×; 3) Automatic tuning of sleep time and a gate leakage compensation capacitor using a canary circuit maintains optimal power consumption across temperature. Finally, a new low injection error switch structure reduces noise from the S&H circuits. We explain each of these methods in more detail below.

Fig. 1 shows the structure of the proposed sample and hold bandgap. The bandgap itself is a traditional design with single point trimming of the resistor. In active mode, the bandgap is ON (CLK0 is low) and the output and intermediate node voltages are stored on sample and hold capacitors C1–C5. In sleep mode CLK0 goes high to power gate the bandgap, while the S&H circuits continue to output the reference voltage. A delay line generates clocks for the S&H switches and the power gating transistor using an on-chip leakage-based oscillator, periodically waking the bandgap and refreshing the voltage levels.

Power consumption during the active and sleep modes is dramatically different (≥1000×), making average power heavily dependent on achievable bandgap duty cycle. The two critical factors determining duty cycle are bandgap wake-up time and leakage in S&H circuits. To speed bandgap wake-up and stabilization time, three internal nodes are sampled in addition to the reference output voltage using capacitors C1- C4 (Fig. 1). Once the bandgap enters wake-up mode, these stored values drive the nodes inside the bandgap, speeding wake-up by 11.5× (from 55ms to 4.8ms) based on simulation.

To reduce leakage in the S&H circuits, a feedback structure is used as shown in Fig. 2. The main sources of leakage in the S&H circuit are shown in Fig. 4. To eliminate junction and subthreshold leakage in sleep mode, a unity gain buffer drives the PMOS pass transistor source voltage onto its body and drain. This reduces Vbs, Vdb, and Vds to very small values dependent on amplifier gain and offset. From simulation, the subthreshold opamp consume 1.22nW with an offset of approximately 1mV (10K Monte Carlo runs). Measured results show that the subthreshold, junction, and GIDL leakage sources are reduced to the same magnitude as gate leakage at room temperature using this method. To minimize gate leakage,

thick oxide I/O devices (tox >5nm) are used in the subthreshold amplifier and pass transistors.

To further reduce gate leakage, a compensation capacitor with selectable voltage drop is connected to the S&H storage node (Fig. 5), reducing the residual gate leakage to as little as 0.01fA based on measurements. Fig. 6 shows the total leakage across temperature calculated from silicon measurements when no compensation is used, and with a fixed compensation setting that minimizes leakage at 25°C. The graph shows that, while effective, the fixed compensation is capable of improving leakage in only a small temperature range. To increase this range, an on-chip canary circuit is used to dynamically generate the compensation tuning. Fig. 7 shows the canary circuit implementation, which includes an identical copy of the sample and hold circuit, but with a smaller storage capacitor (50fF) to accelerate the voltage drift. Whenever the bandgap enters wake-up mode, the voltage difference between the active bandgap and canary output are compared to a programmable threshold. The output of the comparator feeds simple control logic (implemented off-chip for experimentation purposes) that modifies the leakage compensation setting dynamically. Fig. 6 shows that this method extends the effective compensation range from -20°C to 40°C. Above 40°C subthreshold leakage becomes dominant and the gate leakage compensator would have to be increased in size to remain effective.

The canary circuit is also used to automatically set the length of the refresh period. If the voltage difference between the canary and bandgap exceeds a specified threshold, the refresh period is automatically reduced, and vice versa. Fig. 8 shows the refresh period and compensation tuning code across temperature when a constant 100μV voltage error is maintained across temperature using this approach. Fig. 9 shows the corresponding power breakdown. Total power is 2.98nW at 27°C, which is 2.75× lower than the case without canary-based tuning of compensation code and refresh period.

Finally, to reduce clock noise injected onto the reference by the sample and hold circuits, a low injection error S&H switch is proposed in Fig. 2. M1, M3, M4 and M6 are sized to cancel out injection error from M2 and M5. However, transistor mismatch still introduces random injection charges onto the holding capacitor. To minimize this mismatch-induced injection, two switches (a large switch M2 and a small switch M5) are used in parallel. Initially, both are turned on to provide fast sampling. M2 is then turned off, while M5 remains on to remove injected charge. Since M5 is smaller the final injected charge is reduced by 47% without increasing sampling time (Fig. 3). Finally, an RC filter is added to eliminate remaining high frequency switching noise.

Results The proposed bandgap reference was implemented in standard 0.18μm

CMOS. Fig. 10 shows the measured temperature coefficient (TC) of the proposed sample and hold bandgap (Fig. 1), as well as the distribution of ppm/°C for both the standalone bandgap (using the design at left of Fig. 1) and the proposed bandgap across 10 dies. The sample and hold circuits have a negligible effect (2.76ppm/°C change) on TC. Fig. 11 shows a histogram of bandgap output voltage across 10 dies. The single trimmed mean output value is 1.1918V with σ = 1.713mV, and σ/μ = 0.144%. Measured power supply rejection ratio (PSRR) is given in Fig. 12. Since the only injection path is through the PMOS pass transistor and kickback noise in the amplifier, PSRR is small throughout the entire frequency range. Table 1 summarizes the testing results, including a comparison to the most relevant prior work. The chip micrograph is given in Fig. 13.

References [1] G.D. Vita et al., JSSC, 2007. [5] G. Chen et al., ISSCC 2011. [2] H.W. Huang et al., ISSCC, 2008. [6] P. Kinget et al., CICC, 2008. [3] K. Ueno et al., JSSC, 2009. [7] H. Tanaka et al., JSSC, 1994. [4] A.-J. Annema et al., JSSC, 1999. [8] B.Ahuja et al., ISSCC, 2005.

978-1-4673-0849-6/12/$31.00 ©2012 IEEE 2012 Symposium on VLSI Circuits Digest of Technical Papers 200

Fig. 2. Low injection error switch and the structure of sample and hold block

Bandgap Reference

SH

SH

SH

SH

Sample and Hold

Output Filter

Clocking Unit

C1

C2

C3

C4

C5R1

C1 = C2 = C3 = C4 = 2pFC5 = 30pFR1 = 1MΩ

Non-overlapping Clock Generator

CLK0

CLK2

CLK1

CLK2

CLK0

CLK1

LeakageCompensator

Leakage -Based Oscillator

Canary Circuits

Canary Circuits

VREF

Fig. 1. Structure of the proposed sample and hold bandgapreference

LeakageCompensator

From BaselineBandgap M

UX

50fF

Digital Cirucits

Clock Generator

LeakageCompensator

Sample and Hold

Fig. 7. Structure of canary circuits and the automatically tuning loops

Fig. 8. Measured hold time and corresponding tuning code using canary circuit of Fig. 7.

Table. 1. Performance summary and comparison to other previous works

CLK2

Hold value

CLK1

Error introduced by M2

Residual error of M5 branch

CLK1

CLK2

Error after cancellation of M1 and M3

Residual injection charges removed by M5

Residual error of M5 is smaller than M2's

Fig. 3. Waveform of noise injection

Fig 4. The primary leakage sources of the sample and hold circuits

P-sub

N-Well Isub, IGIDL

IGate

Ijunction

B D S

G

IGate

SampleSample

Sample Value

Hold ValueSample

Leakage PathDriving Path

Fig 5. Gate leakage compensator

Hold Value

16:1MUX

Tuning Bits

4

Sample Node

Hold Node

M1

M2

M3

M4

M5

M6

CLK2CLK2

CLK1CLK1

CLK

CLK

To Holding Capacitor C1-C4From

Bandgap

Connect toNWELL

FeedbackNode

M2=2μmM1=M3=1μmM5=700nm M4=M6=350nm

-20 0 20 40 60 80 100

0.1

1

10

100

Temperature (oC)

Perio

d (S

ec)

0

4

8

12

16

Com

pens

ator

Tun

ing

Cod

e

Fig. 6. Hold time and equivalent leakage in the holding circuits for 100μV error

Type

Area

σ/µ

PSRR

Duty Cycle

LS

TC

Power

Process

Parameters

0.98mm2

0.144% (10 dies)

Bandgap

-67dB@100Hz

Duty Cycle

0.062%/V

24.74ppm/°C

2.98nW

180nm

This work

0.45mm2

0.82% (20 dies)

Δ Vth

-47dB@100Hz

N/A

0.27%/V

10ppm/°C

36nW

350nm

[1]

0.55mm2

7% (17 dies)

Vth Based

-45dB@100Hz

N/A

0.002%/V

7ppm/°C

300nW

350nm

[2]

0.63mm2

2% (60 dies)

Bandgap

N/A

N/A

N/A

57.7ppm/°C

1µW

350nm

[3]

0.45mm2

N/A

Bandgap

N/A

0.01

N/A

370ppm/°C

0.75µW

300nm

[5]

1.2mm2

N/A

Programmable Value

< 5dB@10kHz

∞

N/A

<1ppm/°C

< 2.5µW

1.5µm EEPROM

[6]

Fig. 10. Measured output voltage across temperature and ppm/oC with and without the sample and hold circuits

10 15 20 25 30 350

1

2

3

4

5

C

ount

ppm/°C

Without SHμ=21.98ppm/°CMin=10.85ppm/°C

With SHμ=24.74ppm/°CMin=16.05ppm/°C

Fig. 11. Distribution of the output reference voltage

1.188 1.190 1.192 1.194 1.1960

1

2

3

4

5

6

μ=1.198Vσ=1.713mVσ/μ=0.144%

Cou

nt

Reference Voltage (V)

-20 0 20 40 60 80 10010a

100a

1f

10f

100f

Leak

age

Cur

rent

(A)

Temperature (oC)

Compensation at single temperature No compensation Compensation at every temperature

Fig. 9. Power consumption with canary tuning and comparison with the circuits without canary

Fig. 12. Measured power supply rejection ratio(PSRR)

10 100 1k 10k 100k 1M 10M

-70

-60

-50

-40

PSR

R (d

B)

Frequency (Hz)

Fig. 13. Die photo

350μm

-20 0 20 40 60 80 100100p

1n

10n

100n

Total Power Total Power without Auto Correction Clock Power Refresh Power Hold Power

Pow

er (W

)

Temperature (oC)

-20 0 20 40 60 80 100

1.186

1.188

1.190

1.192

1.194

Ref

ence

Vol

tage

(V)

Temperature (oC)

978-1-4673-0849-6/12/$31.00 ©2012 IEEE 2012 Symposium on VLSI Circuits Digest of Technical Papers 201