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Index

∆I noise, see ground bounceΛ rules, 577Π network, 566δ delay

VHDL, 203�, see response acquisition ��, see stimulus application �di(t)/dt noise, see ground bounce1’s complement (1’C), 198, 300, 732

2’s complement (2’C), 198, 367, 464,477, 732

3D integration, see verticalintegration

7400 family, 5, 677

ground bounce, 423

Abelian [semi]group, 131, 132absolute maximum rating, 456, 572abstract, see cell abstractabstract-level verification, 601acceptor, 672access transistor, 712, 715accumulation, 681acknowledge line, 369active area, 687active edge, 319, 326, 361, 505, 752active-low, 753activity, see node activityactivity reduction, 476actual responses, 141Ada, 177, 186adaptive computing, see

reconfigurable processing unitadd-compare-select, 120adder, 240, 298, 407, 479, 482, 734

ripple carry, 69, 409address bus, 480adiabatic logic, 492adjacent state assignment, 792adjustable delay line, 344after clause

VHDL, 203, 234aggregate computation, 108agility, 10, 44, 657, 727algebraic structure, 130

algebraic transform, 86, 108, 118algorithm, 46algorithm transform, 62allocation, 23Alpha processor, 336, 342Alpha-power law model, 450, 521alphanumerical character, 312aluminum (Al), 677, 697ambient temperature, 488ambipolar device, 713amplification, 404Anceau diagram, 173, 319and-or-invert (AOI) gate, see

composite gateAND-plane, 747antagonistic, 398, 403antenna rule, 527, 725antifuse, 32, 640, 643antistatic material, 566antivalence function, see XOR gateaperture time, see data call windowapplication-specific instruction set

processor (ASIP), 55application-specific integrated

circuits (ASIC), 5architecture, 46

parallel, 648architecture body

VHDL, 183, 189, 214architecture synthesis, 14architecture transform, 64area efficiency, 89area occupation, 743Ariane 5, 148arithmetic package

VHDL, 254arithmetic unit, 409arithmetic/logic unit (ALU), 41arrangement

physical, 19array

VHDL, 219array attribute

VHDL, 219, 244ASIC manufacturer, 617, 623ASIC manufacturing service, 625

ASIC on demand, see architectureagility

aspect ratio, 535, 546assertion statement

VHDL, 209, 234assertion-based verification, 150associativity transform, 86, 96, 107,

123, 479asynchronous clocking, 288, 293asynchronous reset, see resetasynchronous state machine (ASM),

288AT -plane, 80, 224AT -product, 68, 73, 76, 80, 88, 640

attributeVHDL array, 219, 244VHDL signal, 208

autocorrelation function, 62automated test equipment (ATE),

24, 91, 139, 141, 158, 160automatic test pattern generation

(ATPG), 146, 324automaton, see finite state machine

(FSM)automaton without output, 778avalanche breakdown, 455, 676avalanche current, 568avalanche-triggered snapback BJT,

568average magnitude difference

function (AMDF), 62

back bias, 454back gate, 572, 704back gate effect, 401, 454

back-annotation, 255, 462, 606

VITAL, 246backgrinding, 544, 550backward signal propagation, 436balloon, 485bamboo wire structure, 565bandgap, 671, 672, 713, 808, 809bare die, 547behavioral, 737behavioral model, 189, 190, 630behavioral model handoff, 624

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Cambridge University Press978-0-521-88267-5 - Digital Integrated Circuit Design: From VLSI Architectures to CMOS FabricationHubert Kaeslin and ETH ZurichIndexMore information

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INDEX 833

behavioral view, 19best in class tool, 29BiCMOS, 38

bidirectionalgate, see transmission gateline, 430pad, 91, 169, 512

binary, 734binary signal discrimination, 393binding, 23

VHDL, 215, 223binning, 544, 633bipartite graph, 327bistable, 409–418, 750–760bit line, 421

reduced-swing, 492bit-serial architecture, 113bit-true model, 22, 64, 661bivalent, 734BJT, 38, 456, 457, 556, 568, 571,

681, 704black box, 19, 220black box probing, 145, 583blind assembly, 642block diagram, 23, 126, 238block isolation, 24blockage, 601blue film, 544body, 388, 445, 553, 677body effect, 482, 518

coefficient, 452body tie, 572, 600, 688, 704body tie cell, 575, 725bond wire, 502, 546bonding diagram, 545book, 12Boolean algebra, 131, 132Boolean complement, see logic

inverseBoolean optimization, 223boron penetration, 702Boston geometry, 481, 539, 558, 565bottom-up, 184Bough-Wooley multiplier, 750branch-based logic, 403Braun multiplier, 609, 750breakout, 43bubble pushing, 407, 739, 746buffer contention, 501built-in self test (BIST), 24, 631built-in voltage, 675, 676

bulk CMOS, 453, 568, 571, 677bulk process, 682, 703bump, 534, 546bus, 43, 125, 195, 430, 437bus contention, see drive conflictbus control

centralized, 433distributed, 433

bus encoding, 480bus holder, see snapperbus invert coding, 480business model, 631, 650butted contacts, 556, 573

butterfly, 83buyout fee, 631bypass capacitor, 506, 547, 567

on-chip, 428, 509

C language, 177, 185capacitance

coupling, 495, 499capacitive load, 211capacitor

on-chip, 528carbon, 808

carbon nanotube (CNT), 716, 808

carbon-doped oxide (CDO), 699, 810carrier concentration, 674, 702carrier mobility, 387, 449, 450, 557,

590, 673, 701, 702, 712–714, 809carry

end-around, 300cell, 43cell abstract, 29

cell characterization, see librarycharacterization

cell library, 11, 325, 621, 622, 626textit, 28

cell outline, see cell abstractCell processor, 345, 705cell-based design, 11cellular phone, 474, 646center pinning, 506central processing unit (CPU), 618chain/tree conversion, see

associativity transformchannel, 448channel area, 687channel leakage, 678channel length, 387, 446, 449, 482,

557, 708

channel length modulation, 450,452, 589, 681

factor, 391, 450, 453channel width, 387, 446, 449, 557charge decay, 194, 432, 600charge recovery logic, see adiabatic

logiccharge sharing, 386, 423chemical mechanical polishing

(CMP), 527, 595, 637, 687, 712chip, 4chip assembly, 25, 539chip stacking, 549cipher block chaining (CBC), 109,

111circuit size, 4, 44, 67, 533circuit under test (CUT), 139, 141,

398circular path, 65clamping device, 556clear

synchronous, 226, 265, 297, 753

clear box probing, 145clock, 69, 141, 287, 296, 518, 768

distribution network, 233clock boundary, 288, 366, 373clock chopping, 300clock distribution, 294, 339–346

delay, 317, 347–353network, 315, 334reduced-swing, 429, 492

clock domain, 288, 315–317, 346,366, 374, 379

clock driver, 342clock duty cycle, 479clock frequency, 81, 386clock gating, 233, 301, 343, 353–360,

363, 386, 438, 478, 480, 518clock input, 751clock jitter, see jitterclock maximum ramp time, 769

clock minimum pulse width, 768

clock period, 69, 235, 319clock ramp time, 339, 383clock skew, 317, 515, 581

analysis, 345scheduling, 316

clock tree generation, 344, 356, 360,538, 606

clock-to-output delay, 768clocked bistable, 752






834 INDEX

clocked circuit, 374clocked inverter, 406, 410, 412, 417clocked RAM, see synchronous

RAMclocked storage element (CSE), see

clocked bistableclocking, 425, 478, 501

discipline, 287, 296, 317–339clocking discipline, 438clockless logic, see self-timed

clockingCMOS

acronym, 682dynamic, 38, 52, 292, 386, 409fabrication flow, 682–689logic family, 38static, 38, 197, 386, 398, 440, 729,

748voltage levels, 498, 517

coarse-grained FPGA, 34code coverage, 147code encryption, 628code inspection, 139, 599collective clock buffer, 340column address, 420combinational

circuit behavior, 181, 207, 735

VHDL circuit model, 256combinational computation, 70, 123combinational feedback loop, see

zero-latency loopcombinational output, 787combinatorial explosion, 143commercial off-the-shelf (COTS)

component, see standard partcommodity chip, 720commodity RAM, 89, 638common impedance coupling, see

ground bouncecommutativity, 87compact model, 452, 569comparator

arithmetic, 583iterative, 584

complementary, 682complementary pair, 366complete gate set, 76, 742

complex gate, see composite gatecomponent, 43component declaration

VHDL, 184

component failure, 566component instantiation

VHDL, 184composite gate, 399compound semiconductor, 712computation cycle, see computation

periodcomputation period, 69, 460, 583computation rate, 68, 69, 460computer arithmetics, 409concurrency, 181, 185, 200, 205concurrent procedure call

VHDL, 245concurrent signal assignment

VHDL, 187, 206conditional clocking, see clock

gatingconditional instantiatiation, 213conditional output, see Mealy-type

outputconditional process

VHDL, 212conditional signal assignment

VHDL, 188conduction band, 671conductive coupling, 495conductor sizing, 536, 565configurable computing, 58configurable logic cell, 33configuration bit stream, 27configuration specification

VHDL, 215conflict, see drive conflictconflict resolution, 196connected by name, 313connectivity, 19connector, 43constant

VHDL, 218constant-field scaling, 482constraint graph, see timing graphconsumerization, 724contact, 528contact bounce, see mechanical

contactcontact plug, 688contact replication, 538, 557, 562,

607, 634contamination delay, 211, 325, 350,

585, 588, 766

contention, see drive conflict

control flow, 50, 126control overhead, 125control signal, 41, 297controlled inverter, 406–408controller, 13, 41, 46, 778convolutional code, 119coordinate rotation digital computer

(CORDIC), 63, 73copper (Cu), 697, 699coprocessor, 55, 59core, 539corelimited, 533corner pinning, 506cost calculator, 640, 669cost per function, 2, 720costs

non-recurring, 632, 636, 638recurring, 633, 635, 636, 638

counter, 779binary, 462Gray, 462Moebius, 462slice, 415

counter mode cipher (CTR), 109coupled-gate MOSFET (cgNMOS),

see avalanche-triggeredsnapback BJT

coveragefunctional, 142–153

critical path, 238, 321crossbar logic, 562, 717crossover current, 291, 389, 429, 432,

465, 502, 503, 588crossover pattern, 366–369crosstalk, 315, 423, 432, 495, 499,

510, 518, 521, 535, 538, 562,585, 593, 596, 607, 764

cryogenic RAM, 718cubing, see chip stacking, 549current amplification, 573current density, 528, 562, 607current drive, 475, 482, 557, 607,

637, 705current filamentation, 570current return path, 499, 505, 510,

534current-mode logic, 518current-starved inverter, 430customer-owned tooling (COT), 626cutoff region, see subthreshold

region






INDEX 835

cycle-based simulation, 292cycles per data item, 67, 97

damascene metallization, 682data call window, 236, 317, 374, 583,

770

data dependency graph (DDG), 65,777

data flow, 52, 126data loss, 501data retention time, 715data type

VHDL, 218, 224data valid window, 236, 317data-to-output delay, see insertion

delay, 768dataflow model, 190datapath, 13, 41, 46, 56datasheet, 29, 322, 339, 378, 383,

592De Morgan’s theorem, 739

dead state, see lockupdebouncing, 440decoupling capacitor, see bypass

capacitordedicated architecture, 45, 124deep UV lithography, 690defect, 634delay balancing, 463, 479delay buffer, 345delay calculation, 606

central, 587delay line, 346, 381, 515

adjustable, 352, 429

delay locked loop (DLL), 352, 429,467

delay modelling, 203, 246delay tuning, 292, 293, 339Delta delay

VHDL, 203density rule, 526depleted substrate transistor (DST),

see ultra-thin-body SOIdepletion region, 576, 675, 677depletion-type MOSFET, 448derating curve, 590, 612design entity, 238

VHDL, 181design file

VHDL, 221design flaw, 30, 140–142

design flow, 29design for manufacturing (DFM),

see also yield enhancement,544, 561, 590, 605, 626

design for test (DFT), 24, 324, 358design house, 617design kit, 601, 626design library

VHDL, 221design reuse, 294, 726design review, 360, 662, 794–803design rule check (DRC), 25, 524,

559, 602, 725design stability checking, see

unsettled node reportingdesign unit

VHDL, 221design view, 29DesignWare, 233destructive readout, 423, 715detail-level verification, 601deterministic automaton, 776device simulation, 456device under test (DUT), see circuit

under test (CUT)diamond, 808, 809die, 4die bonding/attach, 544die size, 4, 489, 533

estimation, 669dielectric constant, see permittivitydifferential and algebraic equation,

252differential signaling, 519, 729diffusion, 674diffusion area, 577digital signal processing, 47digital signal processor (DSP), see

microprocessordiode, 568, 676direct instantiation

VHDL, 184direct memory access (DMA), 55,

440, 772

direct output, see Medvedev-typeoutput

directed acyclic graph (DAG), 123Discrete Cosine Transform (DCT),

161dishing, 527, 565dissociation of signal classes

textit, 296distributed arithmetic, 116, 117distributed clock buffers, 343distribution delay, 581distributivity, 87division algebra, 131don’t care “-”, 194, 243, 734, 791donor, 672dopant, 553, 672, 683doping, 553, 672, 676, 688, 702

concentration, 449, 672, 674double data rate (DDR), 326double-bond, 513double-gate MOSFET

(DG-MOSFET), 709double-rail, 739, 751down-binning, 766drain, 445, 553, 677, 688DRAM, 5, 89, 292, 423, 468, 760

price, 670drift, 675drive capability, 435drive conflict, 91, 169, 193, 196, 291,

415, 430, 434, 598drive strength, 193, 393, 425drivability, see MOSFET drivabilitydriver sizing, 513drop-in replacement, 657dual networks, 399dual-edge-triggered flip-flop

(DETFF), 326, 417dual-edge-triggered one-phase

clocking, 326, 374, 479dual-threshold logic, see

multi-threshold CMOS(MTCMOS)

duty cycle, 147, 327, 356, 468, 474,771

dynamic back-biasing (DBB), see

variable-threshold CMOS(VTCMOS), 482, 491

dynamic frequency scaling, 475, 482dynamic hazard, 762dynamic logic, see CMOS, dynamicdynamic memory, 410dynamic programming, 120dynamic RAM, see DRAMdynamic voltage scaling, 475, 482

Early effect, see channel lengthmodulation






836 INDEX

ECL, 38, 194, 648edge detector, 300edge effect, 634, 670edge-triggered bistable, 751effective channel length, 450, 680EKV transistor model, 445elaboration

VHDL, 216, 223electric field, 675electrical conductivity, 672, 673electrical overstress, 429, 456electrical rule check (ERC), 24, 598electrically erasable memory, 31electromagnetic coupling, 495electromigration, 527, 535, 562

electron, 449, 671excess, 672vacant, 672

Electron beam direct writelithography (EBDW), 696

electron beam lithography, 643electronic code book (ECB), 73,

108

electronic design automation (EDA),29, 40, 615

electronic manufacturing service(EMS), 619

electronic system level (ESL), 16,179, 726

electrostatic discharge (ESD), 427,456, 556, 565, 572, 764

emitter, 572enable, 226, 354, 754, 755encapsulation, 544endurance, 32, 93, 716energy efficiency, 44, 86, 122–126,

224, 294, 325, 327, 334, 343,356, 361, 475, 492, 705, 718, 727

energy level, 671energy per data item, 68energy per operation, 459energy recycling logic, see adiabatic

logicengineering change order (ECO),

538engineering effort, 44enhancement-type MOSFET, 387,

448, 678entity declaration

VHDL, 182, 184equivalence

functional, see functionalequivalence

equivalence checking, 606equivalence function, see EQV gateequivalence transform, 64, 67equivalent oxide thickness (EOT),

700equivalent series inductance (ESL),

507equivalent series resistance (ESR),

428, 507equivalent states, see redundant

statesEQV gate, 406erratic operation, 286ESD protection, 539Euler line, 143event

key of simulation/test, 157, 172VHDL, 201–203

event queue, 201, 209, 582, 583event-driven simulation, 201, 292execution time, 201exhaustive verification, 142expected responses, 141explicit state model, 226Extendable instruction set

processors, 59extension field, 132external timing, see I/O timingextracell wiring, 557extreme UV lithography, 695

F 2 , see lithographic squarefab, 17fabless vendor, 17fabric, 9, 644fabrication defect, 324, 445fabrication process, 6, 636fabrication yield, 524, see yieldfactoring, 745fail safe, 787fake delay, 245fall time, see ramp timefalse path, 585fanout, 340fanout tree, 290, 301Fast Fourier Transform (FFT), 83fault coverage, 24, 146fault grading, 24fault model, 146

fault tolerance, 786feedback bottleneck, 100feedback loop

architecture-level functional, 99architecture-level nonfunctional,

115circuit-level, see memory loop

FET, 38, 676field

algebraic, 131, 132field oxide, 556field oxide MOSFET, 456, 556field-programmable analog array

(FPAA), 37field-programmable gate array

(FPGA), 138field-programmable logic (FPL), 10,

27, 30–37, 45, 138, 619, 639,642, 724, 727, 748

fileVHDL, 217

fillcap, see filler cellfiller cell, 428, 509fin-FET, 709final testing, 544, 633fine-grained FPGA, 34finite acceptor, 778finite field, see Galois fieldfinite precision arithmetics, 52, 102finite state machine (FSM), 14, 43,

52, 136, 227, 366, 434, 438,776–793

VHDL, 261–270FireWire, 310, 517first-time-right design, 27flash memory, 32, 93, 492, 544, 636

price, 670flat-panel display, 646flattening, 745flexiprint, 548flip chip, 510, 547flip-flop, 4, 376, 413–418, 443, 751

D-type, 414, 752

E-type, 354, 415, 754

JK-type, 754

scan-type, 324, 325, 415, 753

T-type, 415, 754

floating body effect, 704floating gate, 30floating node, 432, 434floating well, 600






INDEX 837

floating-point arithmetics, 52, 64,734

floorplan, 531, 586floorplan handoff, 623floorplanning, 24, 531, 623flow control statement, 216flowchart, 227FO4 inverter delay, 76focussed ion-beam (FIB), 27forbidden interval, 193, 426, 433, 497

forbidden state, 756, 759forced air cooling, 489formal specification, 138forward bias, 676forward-annotation, 255foundry service, 626Fowler-Nordheim tunneling, 31, 527fractional core, 90, 420free-running clock, 304frequency divider, 352front-to-back environment, 29full adder, 407, 442, 743full handshaking, 369, 371full layout handoff, 623full scan, 324full swing, 461, 463full-custom IC, 7, 622function

VHDL, 219function hazard, 302, 763function latch, 335, 412, 481functional equivalence, 779–782

functional gauge, 141–153, 155functionality, 44, 136fuse, 32, 564

gain factorMOSFET, 449, 453, 700process, 449, 556

gain-bandwidth product, 380gallium arsenide (GaAs), 648, 712gallium nitride (GaN), 713Galois field, 119, 132gate

FET terminal, 388, 553logic, 388, 426

gate array, 8gate delay, 254, 697, 765gate dielectric, 428, 448, 527, 676,

687, 701

gate dielectric breakdown, 455, 472

gate electrode, 676gate equivalent (GE), 4, 37, 39, 639,

744gate leakage, 468, 527, 701gate length, 576gate oxide, 553, see gate dielectricgate stack, 676, 708gate-matrix layout, 556gate-to-channel capacitor, see

bypass capacitorgated reset, 288, 301general-purpose architecture, 45, 124general-purpose IC, 5generate statement

VHDL, 212–213generic

VHDL, 211generic clause

VHDL, 211geometric layout, 11Germanium on insulator (GOI), 712glitch, 73, 77, 83, 86, 125, 290, 386,

463, 479, 480, 500, 756, 762–766globally asynchronous locally

synchronous (GALS), 294, 726glue logic, 5, 10, 25golden model, 153, 156, 170, 243graceful degradation, 786graded products, 551graphene, 713, 808

Gray code, see unit-distance codegreatest common divisor (gcd), 132grey box probing, 145ground bounce, 291, 315, 431, 444,

495, 499–521, 535, 539, 572,596, 607, 764

ground plane, 510grounded-gate MOSFET

(ggNMOS), see avalanche-triggered snapback BJT

groupalgebraic, 131

guard bar/ring, 556, 573

half pitch, 577half-frequency clocking, 327Hamming distance, 480hand layout, 11handshake protocol, 164, 310,

368–373hardware acceleration, 221

hardware description language(HDL), 14, 40, 734

hardware procedure, 58hardware redundancy, 635hardwired FPGAs, 644hazard, 238, 290, 762–766, 789heat pipe, 489heat removal, 488, 711heat sink, 471, 489heat spreader, 489, 547heat-conducting compound, 490heritage design, 305hidden refresh, 424hierarchical composition, 181high temperature electronics, 704high-density packaging, 547, 720high-impedance “Z”, 194high-level synthesis, see architecture

synthesishigh-side switch, 388, 442hold margin, 498, 585hold mode, 752hold time, 211, 317, 339, 374, 383,

769

negative, 325hold time fixing, 236, 325, 339, 345holding amplifier, see snapperhole, 449, 672

home time, 770Horner’s scheme, 87host computer, 55, 438hot electron degradation, 455, 590hot electron injection, 31hot plug-in, 572, 785hybrid clock distribution, 344hysteresis, 426, 757

I/O circuitry, 683I/O timing, 346–353, 539IC tester, see automated test

equipment (ATE)Iddq testing, 398, 433IEEE 1076, 176, 180, 193, 252IEEE 1076.1, 252IEEE 1076.2, 253IEEE 1076.3, 254IEEE 1076.4, 245IEEE 1076.6, 254IEEE 1076a, 251IEEE 1164, 193, 208, 393, 588IEEE 1497, 254






838 INDEX

IEEE 1532, 58immersion lithography, 693impact ionization, 676implementation loss, 63, 477implication chart algorithm, 784implicit state model, 227impurity, 672in-circuit programming, see

in-system programmingin-place computation, 83in-system configuration (ISC), 10,

30, 58incremental design, 726indemnification, 630indistiguishable states, see

redundant statesindium phosphide (InP), 712inductance

line, 502loop, 510mutual, 495, 499self, 500, 508

inductive coupling, see inductancemutual

industrial control, 46infinite field, 118information hiding, 220information signal, 296input delay

timing constraint, 236input register, see registered inputinput slope model, 589, 611input-to-output mapping, 142input/output buffer, 429, 501, 514,

520input/output line, 492insertion delay, 770

instance, 43instruction set, 46, 53, 56, 57insulator, 671integrated circuit (IC), 4integrated device manufacturer

(IDM), 17integrated plastic circuits (IPC), 714integrity rule, 598intellectual property (IP) module,

see virtual component (VC)interconnect, 502, 526, 529, 539interconnect delay, 254, 340, 343,

535, 623, 637, 765interconnect material, 697

interconnect modelling, 612interlevel dielectric (ILD), 688, 698,

701interrupt, 440, 772

interspersed supplies, 513intracell wiring, 557intrinsic delay, 588inversion layer, 428, 448, 449inverter, 376, 388–396involutory, 78IP module, see virtual componentisomorphic architecture, 66, 94, 125,

126, 463isomorphic graphs, 66, 779iteration bound, 100iterative decomposition, 72, 98, 123ITRS roadmap, 577, 721

jamb latch, 410, 429jitter, 317, 352, 497Josephson junction, 718junction, see pn-junctionjunction temperature, 452, 469, 488,

590

Karnaugh map, 736

kibit/kiByte, 5

lambda rules, 577laminate substrate, 508, 546, 548land grid array, 509large-scale integration (LSI), 5laser programming, 643latch, 376, 410–413, 751

D-type, 755latch fall-through, 329latch-based circuit, 327, 334, 336latch-up, 429, 456, 539, 556, 571,

704, 729latency, 68, 91, 95, 97, 779, 780lateral diffusion, 576layout density, 424, 524, 556, 559,

577, 704layout design, 24, 28, 551–562layout editor, 11, 552, 602layout extraction, 25, 360, 461, 605layout parasitics, 605, 611layout rule, 11, 524, 552, 561, 576,

577, 601, 602layout rule check, see design rule

check (DRC)

layout versus schematic (LVS), 25,605, 725

leaf cell, 43leakage, 386, 398, 423, 488, 669, 701,

704leakage current, 429, 454, 468, 481,

572, 637leakage suppression, 234, 482–487least common multiple (lcm), 132least significant bit (LSB), 733LECTOR, 487level discrimination, 496level restoration, 393, 404, 426, 435,

496, 729level retention device, see snapperlevel shifter, 429, 440, 517level signaling, 371level-sensitive bistable, 752level-sensitive one-phase clocking,

336level-sensitive scan design (LSSD),

333level-sensitive two-phase clocking,

327, 479library, 43

VHDL, 222library characterization, 28, 134,

339, 383, 591, 592, 611

library design, 482library vendor, 28, 622light emitting diode (LED), 646,

713lightly-doped drain (LDD), see

source/drain extensionline-cell memory, 715linear feedback shift register

(LFSR), 183, 790linear region, 447, 679linear system, 53liner, 697linked state machines, 790liquid crystal display (LCD), 646lithographic mask, see photomasklithographic square, 92, 577, 697,

722lithography, 523, 689–696, 717, 719

post-optical, 694, 721subwavelength, 561, 605, 693

lithography compliance check, 605load

synchronous, see clear






INDEX 839

load factor, 588local interconnect, see silicide straplocal substrate, see bodylockup, 786lockup latch, 325lockup situation, 366logic equation, 737

logic family, 325logic gates as repeaters (LGR), 728logic hazard, 764logic inverse, 133, 734

logic minimization, 743logic one “1”, 194, 734logic reoptimization, 606logic state, 193, 393, 588logic system, 193logic value, 193, 734logic zero “0”, 194, 734longest path, 68, 95, 100, 223, 298,

321, 474, 482, 584, 768

longest path delay, 76, 97, 235, 337,416, 581, 728

look-up table (LUT), 34, 35, 53,108, 117

look-up table (LUTs), 50loop unfolding, 101, 123low voltage differential signaling

(LVDS), 492low-activity circuit, 474low-side switch, 388, 442low-threshold device, 448low-voltage differential signaling

(LVDS), 515

macro, 12, 559macrocell, 12, 534, 562

generator, 13magnetic flux quantum device, 718magnetoresistance, 715mainframe, 648maintenance, 211majority carrier, 573

guard, 575majority function, 402, 741majority gate, 758makelink, 643Manhattan geometry, 539, 558manufacturability analysis, 25,

604marginal triggering, 302, 374–381,

415, 426, 433, 759, 770

marketing, 5, 619, 645–650, 660mask, see photomaskmask usage, 638mask-programmed gate array

(MPGA), see semi-custom ICmaster latch, 380, 413master wafer, 7master-slave flip-flop, 413mathematical package

VHDL, 253Matlab, 14, 162, 725Mealy machine, 300, 776

VHDL, 261Mealy-type output, 142, 787mean time between error (MTBE),

380mechanical contact, 440mechanical stress, 510medium-scale integration (MSI), 5Medvedev machine, 778

VHDL, 265Medvedev-type output, 787megacell, 12, 534memorizing, see sequential circuit

behavior, 735

memory, 52, 89, 231, 639memory bound, 94, 126memory configuration, 89memory interleaving, 92memory loop, 376, 410–412, 753memory model, 231, 247memory refresh, 89, 423, 424memory wait cycle, 424memoryless, see combinational

circuit behavior, 735

metal, 671metal deposition, 688metal gate, 677, 702, 710metallurgical junction, 674metastability, 291, 376, 415, 756, 759

resolution time, 377Mibit/MiByte, 5microprocessor, 37, 74, 88, 618, 648microprocessor interface, 438–440Miller capacitance, 395, 490min/max timing analysis, 597minicomputer, 648minimum bit encoding, 792minimum feature size, 576minority carrier, 573

guard, 575

minority function, 402, 741mirror adder, 407mixed-signal design, 37, 518mixed-signal model, see

VHDL-AMSmobility, see carrier mobilitymobility degradation, see velocity

saturationmobility reduction, see velocity

saturationmodel under test (MUT), 139, 141,

153–168VHDL, 242–245

modularity, 181monoflop, 300monoid, 131monotone, 400, 402, 406, 741

Moore machine, 777

VHDL, 263Moore’s law, 175, 719

Moore-type output, 787MOS, 38, 648, 676MOSCAP, 428, 429, 679, 689MOSFET, 38, 553, 676, 688, 716

driveability, 449, 701equivalent conductance, 449model, 387, 445–457

operation, 676–682

most significant bit (LSB), 733Muller-C, 294, 751, 757

multi domain model, 253multi-chip module (MCM), see

high-density packagingmulti-driver node, 195, 196, 430, 461multi-layer reticles, 643multi-project wafer (MPW), 642,

669multi-stage logic, see multilevel logicmulti-threshold CMOS (MTCMOS),

484multi-value system, see logic systemmulti-valued logic, 93, 492multicore, 81multicycle path, 359, 631multilevel logic, 740

multimedia extension (MMX), 57multipath filter, 98multiple-instruction multiple-data

(MIMD), 56multiplexer (MUX), 187, 354, 430,

437, 742






840 INDEX

multiplexer arm, see controlledinverter

multiplexing, 81multiplier, 463, 479

array, 749multiply-accumulate (MAC), 51mutual exclusion element

(MUTEX), 294, 758

n+ , see dopingn-cube, 736, 764NAND gate, 4, 39, 396Nano imprint lithography, 696nanocircuits, 562nanodevice, 717narrow-channel effects (NCE), 454,

481Nassi-Shneiderman diagram, 227native compiled code, 221near hazard, 764negative back bias, 573negative timing constraint, 210net, 43netlist, 11, 40, 601

extracted, 605netlist handoff, 623netlist screening, see electrical rule

check (ERC)network on chip (NoC), 728network processor, 164next state function, see transition

functionNMOS, 38, 467, 682node, 43node activity, 125, 433, 462–465node capacitance, 432, 490noise coupling, 495noise margin, 319, 393, 426, 497, 519non-disclosure agreement, 628non-monotone, 406non-recurring costs, 9, 633non-recurring engineering (NRE)

costs, 633, 643non-volatile, 31, 716nonlinear loop, 106nonrecursive computation, 93, 123NOR gate, 397not-a-number (NaN), 150number representation scheme, 477,

732numeric overflow, 149

objectVHDL, 217, 252

off state, 387off-axis illumination (OAI), 692off-chip communication, 477offset-binary (O-B), 732ohmic contact, 676on state, 387on-chip memory, 89on-chip variations (OCV), 315, 344,

438, 585, 590, 597, 765one-hot encoding, 366, 429, 792one-mask customization, 650one-shot, 300open collector, see open drainopen drain, 197, 430operating conditions, 382operating temperature, 562operator reordering, see

associativity transformoptical proximity correction (OPC),

636, 693, 725or-and-invert (OAI) gate, see

composite gateOR-plane, 747organic semiconductors, see

integrated plastic circuits (IPC)orientation of binary vectors, 199oscillation, 432output conductance, 391output delay

timing constraint, 236output function, 776

output register, 238, see registeredoutput

over-the cell routing, 592over-the-cell routing, 12, 530, 601overdrive, 466, 472overglass, 689overhead power line, 564overruled memory loop, 410, 415ovonic unified memory (OUM), 715

p+ , see dopingpackage

encapsulation, 43, 489, 540–551,626, 633

VHDL, 43, 220package lead finger, 546package-on-package (PoP), 548pad, 43

pad driver, see input/output buffer,592

pad opening, 689padframe, 533, 539padlimited, 533PAL, 749parallel, see concurrencyparametric failure, 637parametrized circuit model, 211parasitic device, 456, 457, 555, 568parasitic diode, 569parasitic state, 785Pareto-optimal, 224parity gate, 406partial handshaking, 371partial scan, 324partial verification, 143partitioning, 236pass gate, see transmission gatepass mode, 429, 752pass transistor, 30, 403passivation layer, 698passive process

VHDL, 209passive pull-up/-down, 193path algebra, 119, 133pausable clock, 383periodic layout, 561, 717periodic table, 673permittivity, 449, 612, 701, 810perovskite, 700, 715personal digital assistant (PDA),

650Petri net, 138, 179, 757phantom cell, see cell abstractphase locked loop (PLL), 37, 253,

352, 367, 374, 429, 467phase shift masks (PSM), 636, 691,

725photolithography, see lithographyphotomask, 7, 559, 636, 643, 683,

689, 695preparation, 543, 579, 626

photoresist, 683, 690physical design verification, 25, 462physical view, 19pin, 43, 547pin count, 533pin-to-pin delay, 588pinch off, 680ping-pong, 83






INDEX 841

pinout, 506, 534pipeline interleaving, 109, 123pipeline register, 75, 482pipelined interconnect, 728pipelining, 75, 81, 95, 111, 123

coarse grain, 76fine grain, 76, 337

pitch, see half pitchPLA, 747place and route (P&R), 11, 24, 538,

575, 601plane, 747plesiochronous interface, 381PMOS, 38, 467, 682pn-junction, 555, 674, 704polling, 771poly, see polysiliconpoly depletion, 702polycide, 527polymer electronics, see integrated

plastic circuits (IPC)polysilicon, 559, 674, 687polysilicon gate, 677, 687, 702port, 43

VHDL, 182, 211port clause

VHDL, 182port map

VHDL, 184portable design, 305positional number system, 199,

732

positive feedback, 426post-layout, 25, 586, 606power budgeting, 474power dissipation, 459power distribution, 546power estimation, 24, 669power-delay product (PDP), 68

precedence, 130, 740precharge, 421printed circuit board (PCB), 4, 547probe card, 543, 633procedural layout, 552procedural model, 190procedure

VHDL, 219process

VHDL, 187–189, 205process control monitor (PCM), 626,

689

process control monitor (PCMs),543

process monitoring, 689process option, 560, 636process selection, 475process statement

VHDL, 187, 188, 206process variation, 543, 544, 590, 637,

689product

industrial, 632, 649product grading, 650, 652product-of-sums (PoS), 739

productivity, 11, 16programmable array logic, see PALprogrammable logic array, see PLAprop/ramp model, 588propagation delay, 211, 585, 588,

766

protocol adapter, 161prototype fabrication, 642pseudo code, 221pseudo random sequence generator,

462pseudostatic, 389PTV condition, 255, 323, 382PTV variations, 315, 349, 429, 438,

514, 590

pull protocol, 369pull-up/down

network, 397, 398, 403passive, 419, 433, 467

pulse-clocked latch, 361, 479punch-through, see avalanche

breakdownpush protocol, 369

quantityVHDL-AMS, 252

quartz, 708

race path, see shortest pathradiation, 32, 572radiation-hard device, 704raised source and drain, 705RAM, 231, 418–425, 760

asynchronous, 425dual-port, 761embedded, 89, 425ferroelectric (FeRAM), 715magnetic (MRAM), 715

phase-change (PRAM), 715synchronous, 425

ramp time, 340, 393, 433, 465, 481,518, 589, 614, 769

random access memory, see RAMrandom logic, 492, 747

random testing, 150rapid prototyping, 138, 153Rapid Single Flux Quantum

(RSFQ), 718ratioed logic, 398, 410, 417, 425ratioless logic, 398, 729ray tracing, 57reactive system, 46, 138, 179read amplifier, see sense amplifier,

467read-only memory, see ROMreal-world data, 149rebuffering, 606recombination, 675reconfigurable coprocessor, see

reconfigurable computingreconvergent fanout, 290, 300, 764

recordVHDL, 219

recovery time, 770recursive computation, 99, 123reduced instruction set computer

(RISC), 74redundant logic, 744, 765redundant states, 783register, 89, 126, 226register balancing, see retimingregister transfer level (RTL), 23,

175, 238, 241registered input, 350registered output, 350, 789reject clause

VHDL, 203, 234release time, see recovery timeremoval time, see home timerepeated wire, 343, 728repeater, 343replication, 79, 98, 123request line, 369rescaling, 477reset, 296, 302

asynchronous, 226, 263, 296, 301,303, 518, 753

mechanism, 210, 414, 787signal, 244, 304






842 INDEX

reset (cont.)skew, 304VHDL, 210, 225

resistive load, 467resistivity, 809resistor, 679resolution enhancement techniques

(RET), 691, 719resonance frequency, 507resonant clocking, 494resource sharing, 72, 81response acquisition �, 158, 174, 243resynchronization register, 789retain delay, see contamination

delayreticle, 689retiming, 94, 123reuse, see design reusereverse bias, 675reverse body biasing (RBB), see

variable-threshold CMOS(VTCMOS)

ring, 131commutative with unity, 132with unity, 132

ringing, 572ripper, see break outrise time, see ramp timerising edge()

VHDL function, 208ROM, 5, 231, 749routing, 35routing channel, 8, 12, 530row, see cell rowrow address, 420royalty fee, 632RTL model handoff, 624RTL synthesis, 14rule deck, see layout rulerunt pulse, 756, 762, 764, 765

safe circuit, 438Sah model, 389, 390, 446sales volume, 639salicide, 527, 688sampling time, see data call windowsaturation region, 447, 680, 681scalar acquisition, 373scaling, 38, 593

constant-field, 472scaling property, 440, 706

scan flip-flop, see flip-flop scan-typescan insertion, 325, 539scan path, 24, 159, 234, 324, 333,

363, 778scan reordering, 606scan test, 324, 357, 753schedule, 129, 239scheduling, 23schematic diagram, 40, 185schematic entry/editor, 11, 241Schmitt trigger, 426, 440Schottky junction, 572, 676scribe line, 544sea-of-gates, 8, 559seesaw, 299, 303, 385, 412, 751,

756

selected signal assignmentVHDL, 187

self-aligned gate, 677, 687, 702self-checking, 151self-dual, 402self-protection, 569self-referencing function, see

zero-latency loopself-reverse biasing, 487self-timed, 298, 758, 760self-timed clocking, 288, 294semi-custom IC, 7, 34, 620semiconductor, 672semigroup, 131semiring, 119, 131, 133

commutative, 132sense amplifier, 421sensitivity list

VHDL, 205separation gate, 559sequential

circuit behavior, 181, 207, 225,735

code execution, 181, 188, 200VHDL circuit model, 261

Serial ATA (SATA), 517service, 649set

asynchronous, see resetset-up margin, 498, 585set-up time, 211, 317, 339, 374, 383,

769

set-up-and-hold window, see datacall window

sewing kit, 538

shallow trench isolation (STI), 682,687

shared variableVHDL, 251

sheet resistance, 527, 528, 580,595

Shichman-Hodges model, 391, 450shimming register, 78Shockley model, see Sah modelshort-channel effects (SCE), 396,

454, 481, 687short-channel effects (SCEs), 707shortest path, 321, 322, 585, 768

shortest path delay, 235, 581shuttle, see multi project wafer

(MPW)side-wall spacer, 687sign-and-magnitude (S&M), 198,

300, 464, 477, 732

sign-off, 601, 610, 621, 623, 625signal

VHDL, 186, 204, 217signal silencing, 480signal transition graph (STG), 370,

757

signal transition graphs (STG), 138signed

VHDL data type, 198signed number, 733silica, 708silicide, 527, 569, 688silicide strap, 528silicon, 4, 672

silicon carbide (SiC), 713silicon dioxide (SiO2 ), 697, 699, 707,

810silicon foundry, 17silicon-controlled rectifier (SCR), see

thyristorsilicon-germanium (SiGe), 713silicon-on-insulator (SOI), 484, 703,

721silicone, 4SIMOX, 703simulation

logic, 24, 201, 242–248, 436post-layout, 607

simulation model, 339, 383bistable, 378

simulation report, 141simulation time, 201






INDEX 843

simultaneous switching output(SSO) noise, see ground bounce

single-edge-triggered flip-flop(SETFF), 319, 413

single-edge-triggered one-phaseclocking, 69, 319

single-instruction multiple-data(SIMD), 56

single-rail, 739

single-wire level-sensitive two-phaseclocking, 334

singulation, 544size-time product, see AT -productskew margin, 319–339, 597slack, 321, 345, 585slack graph, see timing graphslave latch, 413sleep mode, 477sleep transistor, 484slew rate, 430, 508, 518, 771

clock, 383slew rate control, 514slope sensivity factor, 589slotting, 565small-scale integration (SSI), 5snapback characteristic, 568snapper, 193, 299, 425, 433, 751,

758soft switching, 514soft X-ray lithography, see extreme

UV (EUV) lithographysoftware engineering, 155, 438, 666solid-state device, 671–682source, 445, 553, 677, 688source/drain extension, 569, 687space-charge region, see depletion

regionspecial-purpose architecture, see

dedicated architecturespeculative completion, 298split power lead frame, 513split supplies, 513SR-latch or SR-flip-flop, see seesawSRAM, 5, 89, 418, 484, 487, 712, 760

cell, 376, 559stacked contact, 528staggered contact, 528, 577staggered pad, 533staggered switching, 514stallable, 371, 728stand-by current, 468

standard

VHDL package, 220standard cell, 11, 534, 556, 575standard delay format (SDF), 246,

254, 586, 607standard part, 10, 617start state, 95, 776

state assignment, see state encodingstate chart, 179state encoding, 223, 230, 268, 480,

791state graph, 138, 170, 179, 776

state reduction, 223, 230, 268,783–784, 791

state table, 776

state transition, 297state transition diagram, see state

graphstate-dependent delay, 589statechart, 138, 790static hazard, 762static logic, see CMOS, staticstatic memory, 30, 409, 639static RAM, see SRAMstatic timing analysis (STA), see

timing verificationstatus signal, 41, 297std

VHDL library, 223std logic

VHDL data type, 196, 199std ulogic

VHDL data type, 194, 199steady-state, 431, 496stick diagram, 553stimuli, 141stimulus application �, 158, 174,

243stipple contact, 526, 565stopover register, 346storage capacity, 477storage requirements, 52stored program, 43strained silicon, 701, 712strong inversion, 678structogram, see Nassi-Shneiderman

diagramstructural, 737structural model, 185, 190structural view, 19structured ASIC, 9, 644, 650, 669

structuring, see factoringsub-word parallelism, 57, 125subprogram

VHDL, 219substrate coupling, 518subthreshold current, 452, 468, 472,

678, 681subthreshold logic, 491subthreshold region, 447, 678, 681subthreshold slope, 453, 469, 701,

705subtractive metallization, 688subtractor, 584, 734subtype

VHDL, 218sum-of-products (SoP), 738

super cutoff CMOS (SCCMOS),484, 681

superfast distribution/recollection,81

superposition, 87superscalar, 81supply chain management, 626, 633supply droop, see ground bounce,

596supply voltage, 89, 383, 466, 492,

590surface acoustic wave (SAW) filter,

548surface mount device (SMD), 507switch model, 387, 458switching activity, 361, see node

activityswitching algebra, 133, 734switching noise, 334, 386, 480, 496,

785switching threshold, 339, 432, 517symbol, see iconsymbolic layout, see stick diagramsymmetric level-sensitive two-phase

clocking, 327symmetry

electrical, 423in coefficient set, 87of logic function, 741

synchronization, 363–384, 438failure, 380

synchronization failure, 785synchronizer, 234, 581

shared flip-flop, 385two-stage, 371, 383






844 INDEX

synchronous clear, see clearsynchronous clocking, 287, 291synchronous design

guiding principles, 296–298synchronous island, see clock

domainsynchronous output, 777synthesis

circuit, 14VHDL, 223

synthesis chunk, 236synthesis constraint, 234synthesis model, 14synthesis package

VHDL, 254synthesis subset

VHDL, 254synthesis tool, 292system house, 617system-in-a-cube, see chip stackingsystem-in-package (SiP), see

high-density packagingsystem-on-a-chip (SoC), 6, 548, 650,

726SystemC, 176SystemVerilog, 176systolic conversion, 97

T-diagram, 152T-gate, see transmission gatetape out, 623target process, 528, 533, 555Tcl, 235technology CAD (TCAD), 456, 710technology mapping, 224terminal, 43termination resistor, 467test cases, see functional gaugetest patterns, see functional gaugetest signal, 297test suite, see functional gaugetest vector

set, 24, 141, 146, 625testability, 436testbench, 141, 155, 161

design, 153–168VHDL, 242–245, 270

text editor, 14textio

VHDL package, 221thermal design power (TDP), 488

thermal equilibrium, 674, 677thermal resistance, 488, 704thermal voltage, 452, 808thinoxide, see gate dielectricthree-state node, 425, 430three-state output, 195, 399, 405threshold adjustment, 702threshold function, 741threshold voltage

inverter, 390MOSFET, 30, 424, 448, 453, 454,

468, 482, 491, 518, 527, 590,637, 705, 708

through path, 300, 787throughput, 44, 68

thyristor, 568, 571tie-off cell, 427tiled layout, 52, 424, 562, 747, 750,

760time borrowing, 329, 335time per data item, 68time sharing, 81, 98, 111time to market, 10, 44, 136, 641time-invariant, 53time-sharing, 123timing

memory, 91timing check, 209, 436timing closure, 538, 599timing condition, 208, 254, 374,

768

timing constraint, 223, 234–238,409, 771

timing library format (TLF), 323timing overhead, 321timing problem, 286, 581, 582, 606timing verification, 24, 235, 321,

323, 345, 358, 360, 498,585–586, 591, 606

timing violation, see marginaltriggering, 585

toggle count, 146toggling rate

maximum, 771

of a node, see node activitytop-down, 184topological order, 173transaction

higher-level, 17, 150, 155, 160

VHDL, 201–203, 583transconductance, 391

transfer characteristicinverter, 393MOSFET, 387, 446–452

transformatorial system, 46, 138,179

transientsmodelling of, 588

transistor count, 4transistor model, 253transistor strength, 449transit frequency, 712transition function, 776

transition signaling, 370transition-minimized differential

signaling (TMDS), 517Transmeta, 476transmission gate, 30, 393, 403, 429,

434–437, 445, 455transmission gate adder, 443transmission line, 612tree-height minimization, see

associativity transformtrench capacitor, 712tri-gate device, see fin-FETTriac, 147trickle inverter, 410trip point/voltage, 591triple-S logic, 485truth table, 138, 735

TTL, 38, 194, 676voltage levels, 498, 517

turnaround time, 9, 139, 548, 621,727

two-level logic, 738

two-phase level-sensitive clocking,518

two-stage logic, see two-level logictype, see data typetype attribute

VHDL, 219type conversion

VHDL, 255

ultra thin body (UTB), 704, 710ultra-large-scale integration (ULSI),

5ultra-thin-body (UTB), 713unate, see monotoneunclocked bistable, 298, 426unclocked RAM, see asynchronous

RAM






INDEX 845

unconditional output, see

Moore-type outputuncontrolled oscillation, 500undecoded Moore type output, see

Medvedev-type outputunderdrive, see super cutoffUNIBOND, 703uninitialized “U”, 194unit distance code, 367unit-distance code, 480unity gain point, 497universal transform, 86unknown “X”, 194, 393, 734unsafe circuit, 437unsettled node reporting, 583unsigned

VHDL data type, 198unsigned number, 733unused input, 518use clause

VHDL, 222user interface, 46UTSi, 703UV-erasable memory, 30

vacancy, see holevalence band, 671Van der Pauw structure, 580, 689variable

VHDL, 204, 218variable-threshold CMOS

(VTCMOS), 482varicap, 675vectored acquisition, 365velocity saturation, 396, 450, 472

index, 451, 453

ventilation, see forced air coolingverification

dynamic, 139static, 139

Verilog, 14, 176, 185vertical integration, 711very-large-scale integration (VLSI),

5very-long instruction word (VLIW),

56VHDL, 14, 176–255, 736

code examples, 256–285VHDL-AMS, 252via, 9, 528virtual component (VC), 16, 351,

615, 621, 627–632, 650, 726virtual prototype, 16, 138VITAL, 245, 607, 613Viterbi algorithm, 62, 119volatile, 716, 761voltage amplification, 390, 391, 393,

588voltage drop, 607, 676voltage swing reduction, 492

wafer, 4, 689processing, 7, 552, 577, 624, 633,

636, 682–689

sorting, 543, 634tape, see blue filmtesting, 543, 633

wafer thinning, see backgrindingwait statement

VHDL, 203, 206, 225, 234wake-up signal, 202, 205, 207, 297wave pipelining, 337

waveformclock, 322, 327, 330, 338, 339, 383,

581signal, 291

weak inversion, 491, 678weak transistor, 410, 433, 557weakly programmable satellite, 55well, 685, 704wire bonding, 533, 544, 546, 548,

550wire load model, 586wire planning, 729wired-AND, 197, 430wiring parasitics, 586word line, 420

word width, 52, 125, 126, 211, 477work

VHDL library, 223work function, 677, 702, 708wristwatch, 468write back, 424

XNOR gate, see EQV gateXOR gate, 132, 406, 740

Y-chart, 18yield, 524, 544, 625, 634, 637, 644,

669model, 634

yield enhancement, 538, 561, 625

Zener diode, 569, 676zero-delay clock distribution, 352zero-latency loop, 66, 238, 299,

302, 327, 440, 582, 757, 758,789






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