VHDL

MHXANH MOORE 7-SEG

Moore, Seven Segment board FLEX10K

MOORE w z z 1 w 1. z 0 z=1 2 Clock w '1', z=0. H z 7-seg clock 3 ,,C

AAB0

BAC0

CAC1

vhdl

moore.vhdLIBRARY ieee;USE ieee.std_logic_1164.all;USE ieee.std_logic_unsigned.all ;

ENTITY moore IS PORT(Clock,Resetn,w :IN STD_LOGIC; z :OUT STD_LOGIC_VECTOR(3 DOWNTO 0));END moore;

ARCHITECTURE behavior OF moore IS TYPE State_type IS (A,B,C); SIGNAL y: State_type;BEGIN

PROCESS(Resetn,Clock) BEGIN IF Resetn='0' THEN y-- CountA 01100 -- 1MHz -- . CountA 1.f1Mhz f10Khz f100hz f1hz