A Gated VCO for 10Gb/s PON Systems in 0.18μm CMOS

Gaowei Gu, En Zhu, Ye Lin Institute of RF- & OE-ICs

Southeast University Nanjing, China

gugaowei@seu.edu.cn

Abstract—A 5GHz Gated VCO for burst-mode operation in 10Gbps GPON and EPON systems is presented. The GVCO consists of four stages of XNOR/XOR cell with voltage-controlled delays, and aligns output clock to burst data within 2 bits time. The GVCO has a tuning range from 4.4GHz to 6.2GHz. The phase noise of the GVCO in steady state circuit is -105dBc/Hz at 5MHz offset. The circuit is implemented in SMIC 0.18μm CMOS process, occupies an area of 425*480μm

2. The power consumption is 35mW (with I/O buffers).

Keywords- gated voltage-controlled oscillator (GVCO); burst-mode; variable delay cell; NXOR; passive optical network (PON)

I. INTRODUCTION The passive optical networks (PONs) become a

prospective solution to bring a very high data rate to the end-users. The IEEE 802.3av 10G-EPON task force has just approved IEEE Std 802.3av™-2009 at September 2009, and full service optical access network is engaged in standardizing the physical specifications for 10GPON system [1,2]. The PON systems apply a point-to-multipoint (P2MP) topology. An optical line terminal (OLT) communicates with multiple optical network units (ONUs) located in the subscribers. Each ONU sends burst data packets to the OLT in a time division multiple access method. As the distance between OLT and each ONU differs, the burst data packets have different amplitudes and phases which should be recovered in tens of bits according to some standards. While the traditional clock and data recovery (CDR) technology based on phase-locked loop (PLL) is rather inefficient to reach steady state in such a short time, a GVCO has been widely adopted in burst-mode CDR for its instantaneous phase aligning characteristics.

In this paper, we present a 5GHz GVCO based on voltage-controlled NXOR cells serve for half-rate burst-mode CDR in PON systems. The design is implemented in SMIC 0.18μm CMOS technology. The simulation results have proved that this GVCO can provide data-aligned clock within an acquisition time of at most 2 bits. It has a tuning range from 4.4GHz to 6.2GHz and the phase noise of the GVCO in steady state circuit is -105dBc/Hz at 5MHz (1‰ center frequency) offset. In section II we give out the architecture of the proposed XNOR-based GVCO and explain its working process, as well as its application in a 10Gb/s PON CDR system. The GVCO is implemented in

section III. The layout and post-simulation results are shown in section IV. Section V is the conclusion for this work.

II. ARCHITECTURE A most popular GVCO architecture [3] is illustrated in

Fig. 1(a). It consists two ring VCOs start/stop oscillating alternately at every data-edge. The proposed GVCO consists only one ring, as shown in Fig. 1(b). There are 4 voltage-controlled delays cells, three of which are connected as NXORs and the other is connected in the form of XOR, as well as two buffers. All the voltage-controlled delays cells are implemented in full differential version although they are illustrated in a single-end form. This GVCO works in a rather different way, as it will never stop during operation. The proposed GVCO works at a half-rate. For a 10GB/s application, the needed center frequency of the oscillator is 5GHz. This has greatly reduced the design difficulty for high-speed circuit and improved the noise performance.

To explain how the proposed GVCO works, we mark four reference points (A, B, C, and D) on the diagram. The input data are set to ‘0’s when there is no data transfer. Suppose that the data are consecutive ‘0’s, Cell 1, 3, 4 work as inverters and Cell 2 works as a buffer, thus form a 4-stage oscillator. When the input data are ‘1’s, Cell1 works as an inverter and Cell2, 3, 4 work as buffers, another oscillating loop is formed. The loop delay time of these two paths are the same.

Figure 2. (a). A popular GVCO architecture

Cell 1 Cell 2 Cell 3 Cell 4

Data in

Vctrl

A B C D

Figure 1. (b). Block diagram of the proposed GVCO.

2010 Second International Conference on Future Networks

978-0-7695-3940-9/10 $26.00 © 2010 IEEE

DOI 10.1109/ICFN.2010.94

261

When a data flip occurs, for example, from ‘0’ to ‘1’, the clocks at point A will be directly influenced.

1) The clock clocks with the data are locked: Waves of each point under this situation are given in Fig. 2(a). The clock (A) is at the threshold and a 180° phase drift of clock (A) will occur at the data edge, that is, the phase of clock(A) is firmed to 90° or 270°. The two NXOR operations of Cell 1 and Cell 2 cancel each other, so clock(B), clock(C) and clock(D) are continuous in both phases and magnitudes.

D

times

CB

AD

ata

Figure 2. (a) The clock locks with the data;

D

times

Dat

aB

AC

Figure 3. (b) The clock leads the data;

D

times

Dat

aA

BC

Figure 2. (c) The clock lags the data.

GVCODataVctrl

GVCODataVctrl

PFD

Charge Pump &

Loop Filter

NRef Clk

MS-DFFD

CKQ

DCK

QMSS-DFF Data Buf

Data in

ClkBuf

DataBuf

MUX

Ck

Clock BufThe proposed GVCO

Figure 3. Application of the proposed GVCO in burst-mode CDR

2) The clock initially leads the data: As shown in Fig. 3(b), clock (A) has crossed the threshold when the 180° phase drift occurs as the result of the data flip. It takes more time for clock(A) to discharge form the current voltage to the bottom level (or charge to the top level), thus slows down the oscillation to track the input data.

3) In the case of the clock initially lags the data, the polarity of clock(A) changes before its threshold, thus shorten the charge/discharge process and pulls the clock to speed up the oscillation.

The sampling time for the clock phase of clock V(C) with respect to the data edge 2*τd , that is, UI/2, so the edge of clock V(C) is aligned with the peak of input data for best receiving. An example of the application of this GVCO in CDR is given in Fig. 3. The control voltage may come from a reference PLL contains a replica of the GVCO locked to a local reference clock. The two GVCOs should be match at a high degree to ensure the GVCO for CDR is operating at the proper frequency, but no need exactly, for the phase-aligning mechanism could eliminate accumulative jitter at every data edge within allowed CIDs(consecutive identical digits). The allowed CIDs can be estimated as :

CIDUINf

Δ=Δ

. (1)

III. IMPLEMENTATION The differential XNOR/XOR cell is realized in current-

mode logic (CML) multiplexer, for its high speed and immunity to common-mode noises. Circuit of the cell is shown in Fig. 4. The load at each end of this differential pair is composed of a PMOS in triode region and a poly-silicon resister. The delay of this cell and frequency of oscillation can be estimated as:

ln 2ln 2load peak

eq load

C VR C

Issτ = =

, (1)

0

1 12 8

fMτ τ

= =. (2)

While

262

Vdd

v_ctrl

in+

in-data+data-

M1

M2 M3

M4 M5 M6 M7

R M8 M9 R

vbn

Figure 4. Schematic of the VC-XNOR cell

3,4

1//

1 1 ( | |)

eqm

p ox DD ctrl THP

R Rg

WC V V VR L

μ

=

≈+ − −

, (3) The Cload at each node contains Cg of two NFETs, (M4 and M6, or M5 and M7) and parasitic capacitance. The oscillation frequency is controlled by the v_ctrl linearly.

8,9

8 ln 2 ( )VCO pctrl load

f WK CoxV C L

μ∂= ≈ −∂ .(4)

The differential pair for data input has introduced additional noise compared to common differential oscillator cells. The SSB phase noise due to white noise of this cell can be derived similar to [7] as:

20

4 8 2,3 1

2 3 / 4 1 1 1( ) [ ( ) ]( )ln 2 eff eff eff op

fkTL f

I V V W V fγ

−

= + + +

(5)

IV. LAYOUT AND SIMULATION RESULTS This circuit is implemented in SMIC 0.18μm CMOS

1P6M (one poly-silicon layer, six metal layers) process. Fig. 5 shows the layout of this design with an chip size of 425*480μm 2. Output buffers are inserted to improve the drive ability. Fig. 6 gives out the transient response simulation results and eye-diagram of output clock locked with the data. The input data we introduce has a realistic ramp, and it works well in phase aligning mechanism. Fig.7 shows the tuning curve of this VCO as well as the phase-noise characteristics. A summary of simulation results is given in Table I.

Figure 5. Layout of the proposed GVCO.

Figure 6. (a) Transient response simulation results, over 50Ω. Loads

Figure 6. (b) Simulation results: output eye diagram over 50Ω. Loads

263

Figure 7. (a) Harmonic frequcy curve;

Figure 7. (b) Phase noise.

TABLE I. SUMMARY OF SIMULATION RESULTS

Technology SMIC 0.18μm CMOSTuning Range 4.4GHz-6.2GHzAcquisition Time 2 bits Output Swing (over

50Ω Load) 0.25V

Phase Noise -105.3dBc@5MHzKVCO -1.73GHz/VPower Consumption 35mW

V. CONCLUSION A 5GHz Gated VCO for half-rate burst-mode CDR is

described, which could be adopted in 10Gbps GPON and EPON systems. We has illustrated its operation process. This GVCO has a tuning range from 4.4GHz to 6.2GHz. The phase noise of the GVCO in steady state circuit is -105.1dBc/Hz at 5MHz offset. The output clock can align to the middle of data unit within 2 bits when a burst data packet arrives.

REFERENCES [1] 10G-EPON Task Force, IEEE P802.3av. [2] Ethernet in the First Mile, IEEE 802.3-2005 Starndard. [3] M. Banu and A. E. Dunlop, Clock Recovery circuits with instanteous

locking, Electronics Letters, Nov 1992, pp.2127-2130. [4] M. Banu, and A. E. Dunlop, "A 660 Mb/s CMOS clock recovery

circuit with instantaneous locking for NRZ data and burst-mode transmission," ISSCC, pp. 102-103, Feb,1995.

[5] C. F. Liang, et al., "A 10Gbps Burst-Mode CDR Circuit in 0.18μm CMOS," Proc. IEEE CICC, pp. 599-602, Sept. 2006.

[6] C. Liang, S. Liu, G. Eason, “A 20/10/5/2.5Gb/s Power-scaling Burst-Mode CDR Circuit using GVCO/Div2/DFF Tri-mode cells,” ISSCC 2008, pp. 224-226.

[7] A. Abidi, “Phase Noise and Jitter in CMOS Ring Oscillators,” JSSCC, Aug 2006, pp 1803-1816

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