Abstract− This paper describes the design and experimentalcharacterization of a 130-nm CMOS cascade ΣΔ modulator in-tended for multi-standard wireless telecom systems. Both architec-tural- and circuital-level reconfiguration strategies are incorporat-ed in the chip in order to adapt its performance to different stan-dard specifications with optimized power dissipation.Measurements show a correct operation for GSM/Blue-tooth/WCDMA standards, featuring a dynamic range of86.7/81.0/63.3dB and a peak signal-to-(noise+distortion) ratio of74.0/68.4/52.8dB within 200kHz/1MHz/4MHz, respectively. Thepower consumption is 25.2/25.0/44.5mW, of which 11.0/10.5/24.8are due to the analog part of the circuit†1.

I. INTRODUCTION

The next generation of wireless telecom systems will requirelow-power multi-standard chipsets, capable to operate over anumber of different communication protocols, signal condi-tions, battery status, etc [1][2]. The efficient implementation ofthese chipsets demands for reconfigurable building blocks thatcan adapt to the different specifications with minimum powerconsumption and at the lowest cost. One of the key blocks is theAnalog-to-Digital Converter (ADC), because of the differentsampling rates and resolutions required to handle the widerange of signals coming from each individual operation mode.

Compared to other data conversion techniques, Sigma-DeltaModulators (ΣΔMs) are very suited for the implementation ofmulti-mode ADCs in highly integrated transceivers usinglow-cost “digital-friendly” nanometer CMOS technologies[3]-[8]. Based on the combination of oversampling and quanti-zation noise shaping, ΣΔMs achieve a high degree of robustnesswith respect to circuit errors, thus making easier to include sys-tem- and circuit-level reconfiguration strategies without signifi-cant performance degradation.

In this work, a 130-nm CMOS reconfigurable ΣΔM is pre-sented. The circuit is intended to cope with GSM/Blue-tooth/WCDMA requirements in a direct-conversion receiver.An expandible cascade architecture is used to fulfil the requiredspecifications with optimized power consumption. The designof the building blocks is based upon a top-down CAD method-ology that combines simulation and statistical optimization atdifferent levels of the system hierarchy. Experimental resultsare shown to demonstrate the correct operation of the chip forthe different standards.

II. MODULATOR ARCHITECTURE

Fig.1 shows the modulator architecture. It consists of an ex-pandible cascade topology [9] that comprises a 2nd-order firststage followed by 1st-order stages, and it can be easily extendedto build a ΣΔM of a generic order by simply adjusting thenumber of 1st-order stages. In addition to , the oversamplingratio, , and the number of bits of the last stage, , can be re-configured using two control signals ( and in Fig.1).

The former issues can be handled at circuit level, by recon-figuring the last stage of the expandible cascade to either 1-bitor 2-bit, and by dividing the master clock frequency (80MHz)by a factor 2. In addition, the same sampling capacitor (0.25pF)is used for all cases, thus eliminating the need for switchable ca-pacitor arrays at the modulator front-end. The integration ca-pacitor of the fourth stage can be modified from 0.5pF to

†1. This work has been supported by the Spanish Ministry of Science andEducation (contract TEC2004-01752/MIC) and the Spanish Ministry of In-dustry, Tourism and Commerce (FIT-330100-2006-134 SPIRIT). Figure 1. SC schematic of the reconfigurable cascade ΣΔM.

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An Adaptive ΣΔ Modulator for Multi-Standard Hand-held Wireless Devices

Alonso Morgado, Rocío del Río and José M. de la RosaInstituto de Microelectrónica de Sevilla, IMSE-CNM (CSIC/University of Seville)

Edif. CNM-CICA, Avda. Reina Mercedes s/n, 41012 Seville, SPAINPhone: +34 955056666, FAX: +34 955056686, E-mail: {alonso|rocio|jrosa}@imse.cnm.es

IEEE Asian Solid-State Circuits Conference

1-4244-1360-5/07/$25.00 2007 IEEE

November 12-14, 2007 / Jeju, Korea8-3

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0.25pF in order to have a loop gain equal to one at this stageand make the implementation of the multi-bit quantizer easi-er†2.

The modulator has been designed to fulfil the requirementsof a multi-standard direct-conversion receiver for GSM/Blue-tooth/WCDMA, considering a separate (switchable) RF sec-tion and a programmable baseband section [2]. The requiredmodulator resolution was extracted from an iterative simula-tion-based procedure, realized in MATLAB/SIMULINK®,considering the propagation of the different standard test sig-nals through the receiver front-end. The outcome is shown inTable I, which lists the modulator specifications as well as theselected values of , and for the different standardscovered by this prototype.

The modulator specifications have been mapped ontobuilding-block specifications using statistical optimization fordesign parameter selection, and compiled equations (captur-ing non-ideal building block behaviour) for evaluation. Thisprocess is fine-tuned by behavioural simulation using SIM-SIDES —a SIMULINK-based time-domain behavioural sim-ulator for ΣΔMs [10]. In this process, the worst cases forspeed and for thermal noise are considered. These specifica-tions define the starting point for the electrical sizing of thebuilding blocks, which is described in the next section.

III. CIRCUIT DESIGN

A. AmplifiersAll amplifiers in the ΣΔM use a folded-cascode topology,

since the required DC gains are not high, whereas the speedspecifications are quite demanding for WCDMA. The fouramplifiers (OA1 to OA4 in Fig.1) share the same transistor siz-es, with the only difference being a larger differential input pairin OA2 and OA3 in order to obtain a faster response. This, to-gether with the use of a reconfigurable bias current for each am-plifier and standard —using the scheme shown in Fig.2—, al-lows to fulfill the amplifiers specifications in the different oper-

ation modes.Table II summarizes the electrical parameters for each stan-

dard obtained after full sizing of the amplifiers, together withtheir corresponding bias currents. Results correspond to theworst-case value of each individual parameter obtained froma corner analysis, considering fast and slow device models,

variation in the 3.3-V supply and temperatures in therange .B. Capacitors

All integrators use 0.25-pF sampling capacitors. This valuehas been fixed considering the trade-off between the modula-tor operation for GSM —in which thermal noise and capaci-tors mismatch can seriously limit the required resolution(13bits)— and that for WCDMA —in which the requiredbandwidth (4MHz) in combination with large capacitiveloads at the integrators can seriously impact power consump-tion.

Metal-insulator-Metal (MiM) structures, which allow thininter-metal oxide between the two top metal layers, wereused. They exhibit a good matching (0.1%) and very smallbottom-plate parasitics (4.6%). The implementation of the re-configurable modulator requires only unit capacitors.C. Switches

The design of the CMOS switches has been tackled withtwo main considerations in mind. First, the on-resistanceheavily affects the integrator dynamic, slowing down its tran-sient response [9]. Second, the switch on-resistance can behighly dependent on voltage. The sampling process with such anon-linear resistance causes dynamic distortion at the ΣΔMfront-end, the more evident the larger the signal frequency. Ac-cording to these considerations, resistances in the range of

can be tolerated in combination with the amplifier dy-namics. In our process, such a value can be obtained usingstandard-threshold CMOS transmission gates, with no need

†2. Note that either a comparator or a 2-bit quantizer can be selected inthe last stage in order to give more flexibility to the chip.

TABLE I: MODULATOR SPECIFICATIONS.Standard Dynamic Range Bandwidth L M B

GSM 13bits 200kHz 3 100 1bitBluetooth (BT) 11bits 1MHz 4 20 2bitsWCDMA 9bits 4MHz 4 10 2bits

L M B

Figure 2. Reconfiguration of the bias current of an amplifier.

Iref

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GSM BT WCDMA(A, B) (1,X) (0,1) (0,0)IB IBT + IB,1 IBT IBT + IB,1 + IB,2

TABLE II: WORST-CASE SIMULATION RESULTS FOR THE AMPLIFIERS.GSM Bluetooth WCDMA

OA1 OA2-OA3 OA1 OA4 OA2- OA3 OA1 OA4 OA2 OA3DC gain (dB) 61.6 64.2 62.7 64.6 58.8 57.3 59.9GBW (MHz) 244 143 183 105 130 326 102 251 232PM (º) 72 76 72 79 76 72 84 76Slew rate ( ) 253 102 144 80 85 474 141 352 289Eq. cap. load (pF) 0.64 1.33 0.63 1.14 1.32 0.64 2.15 1.34Output swing (V) 1.8 1.9 2.1 2.0 1.4 1.0 1.2Input cap. (pF) 0.29 0.44 0.29 0.43 0.30 0.45Output cap. (fF) 31 38 29 39 31 39 24

Input eq. noise ( ) 11.8 10.4 13.6 11.0 10.5 7.8 8.2

Bias current ( ) 28 24 16 20 52 80 66Power cons. (mW) 2.32 1.99 1.32 1.65 4.31 6.63 5.47

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for clock boosters. The sizes of the pMOS and nMOS devices— and , respectively— have been se-lected to equalize their transconductances, keeping the resis-tance of the transmission gate as linear as possible. D. Internal A/D/A converters

The first two stages of the modulator use comparators assingle-bit quantizers. The resolution specifications for thesecomparators —30 and 40mV for the hysteresis and offset re-quirements, respectively— are not very demanding. Howev-er, the maximum comparison time must be around a quarterof the clock period —3ns for the 80-MHz clock frequencycorresponding to WCDMA. For this reason, a latched com-parator has been adopted.

The A/D/A converter used in BT/WCDMA modes atthe last stage is implemented with a flash ADC and a resis-tive-ladder DAC, as shown in Fig.3. The thermometer code atthe comparators outputs is translated into a 1-of-4 output code( ) that controls the generation of the analog output of themulti-bit quantizer. The resistive-ladder DAC consists of 6segments of (unsalicided poly) unit resistors con-nected between reference voltages and

, thus providing a differential full scale of 1.2Vwith current consumption.E. Reference voltage generator

An on-chip voltage generator provides the reference volt-ages to the SC integrators and to the DAC. It consists of aband-gap reference and a resistive amplifier in inverting con-figuration. The main requirements for the references are a fastsettling and a low output impedance in order to avoid dynam-ic distortion at the integrators. A maximum output im-pedance (required for GSM) is obtained along the signal band(up to 4MHz for WCDMA).

IV. EXPERIMENTAL RESULTS

The modulator has been designed and fabricated in a130-nm 1-poly 8-metal digital CMOS technology. Fig.4shows the complete layout [Fig.4(a)] highlighting its mainparts and a microphotograph of the chip [Fig.4(b)]. The lay-out has been carefully designed to maximize the modulator

performance in terms of robustness with respect to switchingactivity, including separate analog, mixed and digital sup-plies, guard-rings surrounding each section of the circuit, etc.The complete modulator occupies an area of 2.68 mm2 in-cluding bonding pads. The chip has been tested using a Print-ed Circuit Board (PCB), shown in Fig.4(c), that includes in-tensive filtering and decoupling strategies, as well as properimpedance termination to avoid signal reflections.

The performance of the modulator was evaluated using anAgilent 93000 SOC test unit to generate the input, biasing,control and clock signals, and to acquire the bit streams of thedifferent stages of the modulator. After acquisition, data weretransferred to a workstation to perform the digital post-pro-cessing using MATLAB®.

Fig.5 shows the measured 65536-point Hanning-windowedFFTs of the modulator output, for the different standard con-figurations, considering a input sinewave with anamplitude of below Full-Scale (FS). The signalbandwidth is highlighted for each operation mode, showingthe corresponding reconfiguration of the noise-shaping per-formed by the modulator. The effective resolution of the cir-cuit is clearly illustrated in Fig.6, where the Sig-nal-to-(Noise+Distortion) Ratio (SNDR) is represented versusthe input signal amplitude for the different operation modes.Finally, Table III summarizes the measured modulator perfor-mance by displaying its most significant figures.

Finally, Table IV compares the experimental results of themodulator with the state of the art in multi-standard low-passSC ΣΔMs. Note that, thanks to the combined use of architec-tural-level (L, M and B) and circuital-level (opamp biasing)reconfiguration strategies, the presented chip achieves a com-petitive performance while covering a wide conversion regionof the resolution-bandwidth plane.

23.49 0.34⁄ 7.56 0.34⁄

2-bit

VDD

Figure 3. 2-bit quantizer at the modulator last stage.

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Figure 4. Chip implementation: (a) Layout, (b) Die microphotograph and (c) Test PCB.

INT#3BIAS

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CONCLUSIONS

A reconfigurable 130-nm CMOS ΣΔ modulator has beenpresented. The chip is able to adapt its architecture and cir-cuit-level parameters to the required specifications forGSM/Bluetooth/WCDMA with optimized power consump-tion. These strategies are demonstrated by experimental re-sults, showing a performance within the cutting edge of thestate of the art in multi-standard ΣΔMs.

REFERENCES

[1] V. Gazis et al.: “Toward a Generic Always Best Connected Capability inIntegrated WLAN/UMTS Cellular Mobile Networks (and Beyond)”.IEEE Wireless Communications, pp. 20-29, June 2005.

[2] A. Savla et al.: “A reconfigurable low IF-zero IF receiver architecture formulti-standard wide area wireless networks”. Proc. ICECS, pp. 935-937,2003.

[3] T. Burger et al.: “A 13.5mW 185-Msample/s ΔΣ Modulator forUMTS/GSM Dual-Standard IF Reception”. IEEE J. of Solid-State Cir-cuits, pp. 1868-1878, Dec. 2001.

[4] T.M.R. Miller et al.: “A Multibit Sigma-Delta ADC for MultimodeReceivers”. IEEE J. of Solid-State Circuits, pp. 475-482, March 2003.

[5] G. Gomez et al.: “A 1.5V 2.4/2.9mW 79/50dB DR ΣΔ Modulator forGSM/WCDMA in 0.13μm Digital Process”. Proc. ISSCC, pp. 242-490,Feb. 2002.

[6] A. Dezzani et al.: “A 1.2-V Dual-Mode WCDMA/GPRS ΣΔ Modulator”.Proc. ISSCC, pp. 58-59, Feb. 2003.

[7] J. H. Shim et al.: “A Third-Order ΣΔ Modulator in 0-18-μm CMOS WithCalibrated Mixed-Mode Integrators”. IEEE J. of Solid-State Circuits, pp.918-925, April 2005.

[8] J. Lim et al.: “A Low-Power Sigma-Delta Modulator for Wireless Com-munication Receivers using Adaptive Biasing Circuitry and Cascadedcomparator scheme”. Springer J. of Analog Integrated Circuits SignalProcessing, pp. 359-365, Sept. 2006.

[9] R. del Río et al.: CMOS Cascade Sigma-Delta Modulators for Sensorsand Telecom - Error Analysis and Practical Design. Springer, 2006.

[10]J.Ruiz-Amaya et al.: “High-Level Synthesis of Switched-Capacitor,Switched-Current and Continuous-Time ΣΔ Modulators UsingSIMULINK-Based Time-Domain Behavioral Models”. IEEE Trans. onCircuits and Systems-I, pp. 1795-1810, Sept. 2005.

Figure 5. Measured output spectra for: (a) GSM, (b) BT and (c) WCDMA.

(a)

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Figure 6. Measured SNDR as a function of the input signal amplitude.

TABLE III: SUMMARY OF THE MEASURED PERFORMANCE

GSM BT WCDMASNDR-peak (dB/bits) 74/12 68.4/11.1 52.8/8.5Dynamic Range (DR) (dB/bits) 86.7/14.1 81/13.2 63.3/10.2Modulator architecture 2-1 Single-bit 2-1-1 Multi-bitSignal Bandwidth (BW) (MHz) 0.2 1 4Sampling Freq. (MHz) 40 80Technology 130nm CMOSActive Area 1.37-mm2 (pads excluded)Overall Power Consumptiona (mW)

a. Digital output buffers and reference generators are not included

25.2 25.0 44.5Analog Core @ 3.3V 11.0 10.5 24.8Ref. Gen. @ 3.3V 19.0 18.9 20.0Mixed @ 3.3V 9.6 10.0 13.9Digital @ 3.3V 4.1 4.1 5.5Digital @ 1.2 V 0.6 0.6 1.2

TABLE IV: STATE OF THE ART IN LOW-PASS MULTI-STANDARD SC ΣΔMs

Author Standard BW (MHz) DR (bits) Power Cons. (mW)

Burger [3] GSM 0.2 14.0 11.513.0 7.5

WCDMA 3.84 8.7 13.5

Miller [4]a

AMPS 0.018 15.030.0GSM 0.2 13.2

CDMA 0.625 12.5WCDMA 1.92 11.4 50.0

Gomez [5] GSM 0.2 12.8 2.412.0 1.4

WCDMA 2 8.0 2.9

Dezzani [6] GPRS 0.1 13.3 2.4WCDMA 1.92 11.3 4.3

Shim [7] GSM 0.1 12.3 4.0WCDMA 2.5 8.8

Lim [8] CDMA-2000 0.615 12.3 22.7WCDMA 1.92 11.0

This workGSM 0.2 14.1 25.2

Bluetooth 1 13.2 25.0WCDMA 4 10.2 44.5

a. In this case, DR data is not available and SNR-peak is usedinstead.

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