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UC Berkeley EE241 J. Rabaey. B. Nikolic

EE241 - Spring 2003Advanced Digital Integrated Circuits

Lecture 10Domino Logic

UC Berkeley EE241 J. Rabaey. B. Nikolic

Aside: Noise in ICsl Sources of noise

» Coupling– Device coupling– Capacitive coupling between wires– Inductive coupling

» Supply line bounce» Charge Injection

– From substrate– α-particles

l Robustness of a circuit» Noise margins» Sensitivity to noise

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UC Berkeley EE241 J. Rabaey. B. Nikolic

Clock Feedthrough

Mp

Me

VDD

φOut

φ

A

B

CL

Ca

Cb

Ma

Mb

Xφ

2.5V

overshoot

out

UC Berkeley EE241 J. Rabaey. B. Nikolic

Clock Feedthrough and Charge Redistribution

0 1 2 3t (nsec)

0

2

4

6

V (V

olt) φ

out

internal node in PDN

output without redistribution (Ma off)

feed

thro

ugh

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UC Berkeley EE241 J. Rabaey. B. Nikolic

Miller and Back-gate Coupling

Courtesy of IEEE Press, New York. 2000

UC Berkeley EE241 J. Rabaey. B. Nikolic

Capacitive Coupling

Courtesy of IEEE Press, New York. 2000

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UC Berkeley EE241 J. Rabaey. B. Nikolic

Capacitive CouplingDynamic node: Static node:

Courtesy of IEEE Press, New York. 2000

UC Berkeley EE241 J. Rabaey. B. Nikolic

Capacitive Coupling

Courtesy of IEEE Press, New York. 2000

Lateral coupling: Shielding

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UC Berkeley EE241 J. Rabaey. B. Nikolic

Minority Charge Injection

Courtesy of IEEE Press, New York. 2000

UC Berkeley EE241 J. Rabaey. B. Nikolic

Supply Noise

Courtesy of IEEE Press, New York. 2000

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UC Berkeley EE241 J. Rabaey. B. Nikolic

Cascading Dynamic Gates

Mp

Me

VDD

φ

φ

Mp

Me

VDD

φ

φ

In

Out1 Out2

φ

Out2

Out1

In

V

t

∆V

VTn

(a) (b)

Only 0→1 Transitions allowed at inputs!

UC Berkeley EE241 J. Rabaey. B. Nikolic

Cascading Dynamic Logic

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UC Berkeley EE241 J. Rabaey. B. Nikolic

Domino Logic

Mp

Me

VDD

PDN

φ

In1In2

In3

Out1

φ

Mp

Me

VDD

PDN

φ

In4

φ

Out2

Mr

VDD

Static Inverterwith Level Restorer

Krambeck et al, JSSC 6/82

UC Berkeley EE241 J. Rabaey. B. Nikolic

Logical Effort

LE =

φ

φ

In

Out

Inverter pair:

Skewed inverter pair:

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UC Berkeley EE241 J. Rabaey. B. Nikolic

Logical effort

LE =

φ

φ

Out

UC Berkeley EE241 J. Rabaey. B. Nikolic

Domino Logic - Characteristics

• Only non-inverting logic

• Very fast - Only 1->0 transitions at input of inverter

move VM upwards by increasing PMOS

• Adding level restorer reduces leakage andcharge redistribution problems

• Optimize inverter for fan-out

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UC Berkeley EE241 J. Rabaey. B. Nikolic

Designing with Domino Logic

Mp

Me

VDD

PDN

φ

In1

In2

In3

Out1

φ

Mp

Me

VDD

PDN

φ

In4

φ

Out2

Mr

VDD

Inputs = 0during precharge

Can be eliminated!

UC Berkeley EE241 J. Rabaey. B. Nikolic

Logical Effort

LE =

φ

Out

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UC Berkeley EE241 J. Rabaey. B. Nikolic

Delayed Precharge

UC Berkeley EE241 J. Rabaey. B. Nikolic

IBM’s 1GHz ProcessorSilberman et al, ISSCC’98JSSC 11/98

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UC Berkeley EE241 J. Rabaey. B. Nikolic

Domino Propertiesl Logic evaluation propagates as falling dominoesl Evaluation period determines the logic depthl The nodes must be precharged during the precharge

period (can limit the minimum size of PMOS)l Inputs must be stable (or have only one rising

transition) during the evaluationl Gates are ratiolessl Restorer is ratioedl All the gates are non-invertingl Only one transition to be optimized

UC Berkeley EE241 J. Rabaey. B. Nikolic

Logic Design Probleml How to design an XOR/MUX without a

complementary signal available?l We need it in datapathsl If the logic is followed by a flip-flop, or a latch with a

hard edge, can use complementary or pass-transistor logic

l Domino logic is used with latches, and a new domino stage may follow the XOR

l Solutions:» Use dual-rail domino (dynamic CVSL)» Violate some of domino rules (but still design a reliable

circuit)» Force a hard edge

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UC Berkeley EE241 J. Rabaey. B. Nikolic

Sum Implementation (1)

Clk

Gi:0

VDD

Clkd

VDDKeeper

Clk

Clk

Clk

Gi:0

Clkd

S i1

S i0

Sum

UC Berkeley EE241 J. Rabaey. B. Nikolic

Sum Implementation (2)

[Anders et al, ISSCC’02]

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UC Berkeley EE241 J. Rabaey. B. Nikolic

Sum Implementation (3): Strobing

[Park, VLSI’00]

UC Berkeley EE241 J. Rabaey. B. Nikolic

Mp

Me

VDD

CLK

CLK

A

B

M1

M2

A B

Mp CLK

O = ABO = AB

VDD

Mf1 Mf2

Differential (Dual Rail) Domino

Dynamic CVSL (Clock CVSL) - Heller et al, ISSCC’84

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UC Berkeley EE241 J. Rabaey. B. Nikolic

Domino TechniquesConditional keeper

Standard keeper Conditional keeper

[Alvandpour, VLSI’01]

UC Berkeley EE241 J. Rabaey. B. Nikolic

Stack Node Preconditioning

Dangerous: With stack nodepredischarged, charge sharingis a problem!

[Ye, VLSI’00]

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UC Berkeley EE241 J. Rabaey. B. Nikolic

Clock-Delayed Domino

UC Berkeley EE241 J. Rabaey. B. Nikolic

Clock-Delayed Domino

φ

DDV

Dφ

Possible implementation of delay block

No need for inversion

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UC Berkeley EE241 J. Rabaey. B. Nikolic

NTP DominoNoise-tolerant precharge (NTP)

Yamada, ICCD’95

UC Berkeley EE241 J. Rabaey. B. Nikolic

Pulsed Static CMOSRH – Reset highRL – Reset low

Fast pull-up Fast pull-down

Chen, Ditlow, US Pat. 5,495,188 Feb. 1996.

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UC Berkeley EE241 J. Rabaey. B. Nikolic

Output-Prediction LogicInverting logic:

Output-prediction logic:

McMurchie, et al, ICCD’2000

UC Berkeley EE241 J. Rabaey. B. Nikolic

Output-Prediction LogicNOR3:

Clocking:

McMurchie, et al, ICCD’2000

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UC Berkeley EE241 J. Rabaey. B. Nikolic

Output-Prediction LogicNOR3 chain of 10:

Clock separation:

UC Berkeley EE241 J. Rabaey. B. Nikolic

Multiple-Output Domino (MODL)

Hwang, Fisher, ISSCC’88

F = F1F2

Common subexpressions

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Lookahead Adder

Multiple Output Domino (MODL)

Generate Propagate

UC Berkeley EE241 J. Rabaey. B. Nikolic

Compound Domino

Houston et al,U.S. Pat. 5,015,882May 1991.

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UC Berkeley EE241 J. Rabaey. B. Nikolic

np-CMOS

Mp

Me

VDD

PDN

φ

In1In2In3

φ

Me

Mp

VD D

PUN

φ

In4

φOut1

Out2

Only 1→0 transitions allowed at inputs of PUNGoncavles, De Man JSSC 6/83Friedman, Liu, JSSC 4/84

UC Berkeley EE241 J. Rabaey. B. Nikolic

np-CMOS

One-bit adder

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UC Berkeley EE241 J. Rabaey. B. Nikolic

NORA Logic

Mp

Me

VDD

PDN

In1

In2In3

Me

Mp

VDD

PUNIn4

Out1

Out 2

To otherN-blocks To other

CLK

CLK

P-blocks

CLK

CLK

UC Berkeley EE241 J. Rabaey. B. Nikolic

NORA Logic

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UC Berkeley EE241 J. Rabaey. B. Nikolic

Clock and Data Precharged Logic

DominoCDPD

Yuan, Svensson, Larson, Electronics Letters, 12/93

UC Berkeley EE241 J. Rabaey. B. Nikolic

Clock and Data Precharged Logic

Logicchains

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UC Berkeley EE241 J. Rabaey. B. Nikolic

NORA Logic

UC Berkeley EE241 J. Rabaey. B. Nikolic

Zipper Logic

Type I:

Type II: