ΔΣ Digital-to-Time Converter

and its Application to SSCG*

1Ramin Khatami, 1H. Kobayashi,

1N. Takai, 1Y. Kobori, 2T. Yamaguchi, 2E. Shikata, 2T. Kaneko, 3K. Ueda

1Gunma University 2AKM Technology Corporation

3Asahi Kasei Microdevices Corporation

With Special Thanks to NEC C&C Foundation

*SSCG : Spread Spectrum Clock Generator The 4th IEICE International Conference on Integrated Circuits Design and Verification (ICDV 2013) Hi Chi Minh City-Vietnam

Outline

I. Background

II. Principle i. PCMΔΣDTC Algorithm

ii. PPMΔΣDTC Algorithm

iii. PWMΔΣDTC Algorithm

iv. PRJΔΣDTC Algorithm

v. Other Possible Algorithms

III. Analysis

IV. Result

V. Conclusion 2

Outline

I. Background

II. Principle i. PCMΔΣDTC Algorithm

ii. PPMΔΣDTC Algorithm

iii. PWMΔΣDTC Algorithm

iv. PRJΔΣDTC Algorithm

v. Other Possible Algorithms

III. Analysis

IV. Result

V. Conclusion 3

Common Object in All Electronic Devices

4

Clock Signal Circuit

Clock is everywhere

Spread Spectrum Clock Technique

Time

Volt

s

Frequency

Pow

er

EMI Limit

Frequency

Pow

er

EMI Limit

5

Frequency

Pow

er

Frequency

Pow

er

Time

Volt

s

EMI Regulation (CISPR22 ) in Japan

Class A: Industrial

Class B: Home

EMI Problem

6

Costly Time Consuming

Solving is difficult Ignoring is Dangerous

Lead to Malfunctioning of devices

SSGC Approach

Time

Volt

s

Time

Volt

s

Solving Digital

Problem By

Analog

Approach

7

Conventional SSGC Problems

8

Frequency

Pow

er

2 Interfere with other desired signals

1 Wasting huge bandwidth

Exclusive Noise Spectrum Selection

9 Frequency

Pow

er

EMI Limit

f [Hz] f v

EMI Limit Our Target:

Ex. FM band

Goal

10

Simple

Low cost

Effective

To compete with conventional methods,

Our method should be:

Converters Path

11

Devices miniaturization, speed, high frequency

Spreading ΔΣ oversampling Applications

Time domain signal processing

From ΔΣADC to ΔΣTDC

From ΔΣDAC to ???

Time Domain v.s. Voltage Domain

ΔΣDAC

Time Voltage

Digital

Analog

ΔΣADC

12

ΔΣTDC

Kobayashi Ring

ΔΣDTC

ΔΣDAC & ΔΣ DTC Analogy

13

Digital ΔΣ

Modulator

1bit

DTC

Digital

Input 1 or 0

One bit

Resolution

Timing

Signal

ΔΣDTC

Digital ΔΣ

Modulator

1bit

DAC

Digital

Input 1 or 0

Pulse

Density

Analog

Output

ΔΣDAC

time domain

Outline

I. Background

II. Principle I. PCMΔΣDTC Algorithm

ii. PPMΔΣDTC Algorithm

iii. PWMΔΣDTC Algorithm

iv. PRJΔΣDTC Algorithm

v. Other Possible Algorithms

III. Analysis

IV. Result

V. Conclusion 14

Pulse Cycle Modulation

15

Dout = 1

Output Pulse Cycle Period = f (Dout )

Exa. : (Dout=10110)

Sout

Dout= 1 , 0 , 1 , 1 , 0

0 T 2T 3T 4T 5T 6T 7T 8T

Dout = 0

Sout

0 T 0 T 2T

Sout

16

CLK

＋ PCM DTC

Clock Generator

Digital Input

Generation

circuit

Din Dout

Sout

PCMΔΣDTC – Configuration

＋

Clock

Generator

Buffer

Memory

Din

Dout

PCM DTC

Sout

Outline

I. Background

II. Principle i. PCMΔΣDTC Algorithm

ii. PPMΔΣDTC Algorithm

iii. PWMΔΣDTC Algorithm

iv. PRJΔΣDTC Algorithm

v. Other Possible Algorithms

III. Analyze

IV. Result

V. Conclusion 17

Pulse Position Modulation

18

Dout = 1

0 T

Sout φ = C

Output pulse position (or phase) = g(Dout )

Ex. (D=10110) Dout = 0

φ = 0

0 T

Sout

Dout = 1 , 0 , 1 , 1 , 0

0 T 2T 3T 4T 5T

Sout

PPMΔΣDTC - Configuration

ΔΣ Modulator MUX

τ Clk

clkout

Digital

Input

19

High Frequency Clock

Outline

I. Background

II. Principle i. PCMΔΣDTC Algorithm

ii. PPMΔΣDTC Algorithm

iii.PWMΔΣDTC Algorithm

iv. PRJΔΣDTC Algorithm

v. Other Possible Algorithms

III. Analysis

IV. Result

V. Conclusion 20

Pulse Width Modulation

Dout = 0

0 T

Sout

τL

Dout= 1 , 0 , 1 , 1 , 0

0 T 2T 3T 4T 5T

Sout 21

Output pulse width = h(Dout )

Dout = 1

0 T

Sout

τH

Exa. : (Dout=10110)

PWMΔΣDTC - Configuration

22

ΔΣ Modulator

Clk

clkout Digital

Input

Sawtooth Wave Generator

Outline

I. Background

II. Principle i. PCMΔΣDTC Algorithm

ii. PPMΔΣDTC Algorithm

iii. PWMΔΣDTC Algorithm

iv. PRJΔΣDTC Algorithm

v. Other Possible Algorithms

III. Analysis

IV. Result

V. Conclusion 23

Pseudo Random Jitter

24

Dout(0) = 1, Dout(1) = 0, Dout(2) = 1, Dout(3) = 1, Dout(4) = 0

0 T 2T 3T 4T 5T 6T 7T 8T Sout

0 T

Sout

Dout = 0 Dout = 1

0 T 2T

Sout

0 T 2T

Sout

3T

Exa. : (Dout=10110)

Output pulse cycle = k(Dout ,h)

25

PRJΔΣDTC - Configuration

Clkout

PRPG Pseudo Random

Pulse Generator

Clk

Digital

Input ΔΣ

Modulator MUX nτ

mτ

dτ

Outline

I. Background

II. Principle i. PCMΔΣDTC Algorithm

ii. PPMΔΣDTC Algorithm

iii. PWMΔΣDTC Algorithm

iv. PRJΔΣDTC Algorithm

v. Other Possible Algorithms

III. Analysis

IV. Result

V. Conclusion 26

PCMDTC: based on digital Input Alter T

PPMDTC: Alter φ

PWMDTC: Alter τP

PRJDTC: Alter T randomly

PPCMDTC, PPWMDTC,PPCRJCDTC, …

Compound DTC… τP

Sout

T φ

τP

Sout

T φ

Sout

T

τP

φ

Sout

φ

τP

27

Outline

I. Background

II. Principle i. PCMΔΣDTC Algorithm

ii. PPMΔΣDTC Algorithm

iii. PWMΔΣDTC Algorithm

iv. PRJΔΣDTC Algorithm

v. Other Possible Algorithms

III. Analysis

IV. Result

V. Conclusion 28

SSGC with Exclusive Noise Spectrum using ΔΣDTC τp

Sout

T φ

TC = 1 (base) , T = nTC, τP =mTC, φ

=2πq/n

Digital Pulse

PCMΔΣDTC

, = 1, 2, 3, 4,…,

PPMΔΣDTC

, = 1, 2, 3, 4,…,

29

SSGC using Delta-Sigma DTC τp

Sout

T φ

TC = 1 (base) , T = nTC, τP =mTC, φ

=2πq/n

, = 1, 2, 3, 4,…,

Digital Pulse

PWMΔΣDTC

PRJΔΣDTC

30

Outline

I. Background

II. Principle i. PCMΔΣDTC Algorithm

ii. PPMΔΣDTC Algorithm

iii. PWMΔΣDTC Algorithm

iv. PRJΔΣDTC Algorithm

v. Other Possible Algorithms

III. Analysis

IV. Result

V. Conclusion 31

Result・Clock’s PSD（Without DTC）

in Base & in Each

Clock Harmonics

32

(66)

66 dB

f

PCMΔΣDTC

33 0 1

TH = 7 TL=5

(50)

-35 dB

50 dB

f

-16dB

PPMΔΣDTC

34

(64)

64 dB

-31dB

f

0 1

TH=5

φ=2

TL=5

φ=0

-2dB

PWMΔΣDTC

35

(67)

62 dB

-37 dB

f

0 1

τH=3 τL=1

TH=5 TL=5

-4dB

PRJΔΣDTC

36 0 1

TH=5 or 6 or 7 TL=5

(52)

51 dB

f

-37 dB

-15 dB

Compound DTC: PRJWPΔΣDTC

37

(63)

49 dB

-100 dB f

0 1

TH=5 or 6 or 7 TL=5

-17 dB

φ=2

Outline

I. Background

II. Principle i. PCMΔΣDTC Algorithm

ii. PPMΔΣDTC Algorithm

iii. PWMΔΣDTC Algorithm

iv. PRJΔΣDTC Algorithm

v. Other Possible Algorithms

III. Analysis

IV. Result

V. Conclusion 38

Result

39

Spreading Usage Spectrum of

SSCG With Exclusive Noise Spectrum!

Low Cost Accuracy Simplicity

＋Completely Digital Circuit ＋High Frequency clock

The End

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Cảm ơn bạn rất nhiều

非常感谢

Thank You Very Much

ممنون خیلی

Muchas gracias

Большое спасибо

Vielen Danken

小林先生ありがとう

40

Presentation

41

Presentation Start

Presentation

42

Kobayashi Ring Conclusion

Presentation

43

Question and Answer