1© 2003-2021 Roberto Muscedere, Images and text portions © 2003 Prentice Hall
Microcomputer Structure and Operation Microcomputer Structure and Operation –– Chapter 5Chapter 5• A Microprocessor (μP) contains
the controller, ALU and internal registers
• A Microcomputer (μC) contains a microprocessor, memory (RAM, ROM, etc), input and output units
• A μP and μC can deliver an inexpensive (cost and hours) solution to a design problem
• Custom circuits are generally preferred in areas where very high speed is necessary, but they are very costly
2© 2003-2021 Roberto Muscedere, Images and text portions © 2003 Prentice Hall
Typical ApplicationsTypical Applications• A μC receives input information or data and
executes a sequence of instructions which processes this information and then provides an output
• A μC may control the engine of an automobile and provides feedback via the display panel
• Many parameters such as temperature, oxygen, fuel, etc provide the information to the algorithms which control the performance of the engine
• A μC may also control an electric oven where information is entered via a keyboard to indicate cooking temperature and time
• It responds by controlling the burner through an output
• A temperature sensor provides feedback on the current temperature of the oven so that it can be better controlled
3© 2003-2021 Roberto Muscedere, Images and text portions © 2003 Prentice Hall
68HC11 in Expanded Mode68HC11 in Expanded Mode• The 68HC11 is set in
expanded mode by “pulling”MODA and MODB high
• This mode allows “external”memory and I/O devices to be connected directly to the MPU busses
• Not all the information is shown; still a simple diagram
• Three busses carry all the information necessary
• Address (A15-A0)• Data (D7-D0)• Control (R/W, etc)
• The MPU is constantly transferring information to and from memory
4© 2003-2021 Roberto Muscedere, Images and text portions © 2003 Prentice Hall
PortsPorts• A port is a set of pins on the chip
through which digital information is transmitted to and from the MPU
• 68HC11 has 5 ports: A, B, C, D, and E
• We are only interested in ports B and C for expanded mode
• In expanded mode, port B is an output and port C is bi-directional
• Port B is used to provide the upper order address information for memory access
5© 2003-2021 Roberto Muscedere, Images and text portions © 2003 Prentice Hall
PortsPorts• Port C is a multifunction port depending
on the state of E-clock and address strobe (AS)
1. Provides the lower order address information for memory access
2. Provides the data for writing to memory and reads the data from memory while reading
• Port C is time-multiplexed since it delivers different signals at different times
• A latch is used to capture the low order address to be used at a later time
• Additional decoders can be used to allow for different memory types
6© 2003-2021 Roberto Muscedere, Images and text portions © 2003 Prentice Hall
Control BusControl Bus• The control bus synchronizes the
operation of the MPU with other elements
• R/W is set to indicate the direction of data on the data bus
• AS is high when the information on Port C is the low order address of a memory access
• /RESET is used to reset the MPU; it can also be initiated by the 68HC11
• /XIRQ and /IRQ are “interrupt” signals that tell the MPU that something important has happened and it must be investigated
• E is the 68HC11’s E-clock (more on this later)
7© 2003-2021 Roberto Muscedere, Images and text portions © 2003 Prentice Hall
Clock SignalsClock Signals• 68HC11 exposes a single
clock signal, E-clock, externally
• The frequency is determined by the external clock components connected to EXTAL and XTAL
• E-clock is always ¼ this frequency
• Maximum external clock is 8MHz; maximum internal is 2MHz
Rf
XTAL
XTALEXTAL
(A)
C2C1
68HC11 MPU
Rf
RsXTAL
XTALEXTAL
(B)
C2C1
68HC11 MPU
8© 2003-2021 Roberto Muscedere, Images and text portions © 2003 Prentice Hall
Clock SignalsClock Signals• 68HC11 also uses an internal clock
PH2 - we can’t see it• The PC is incremented on the rising
edge of PH2• Data is latched into the accumulator
on the falling edge of E-clock• When E-clock is low, AS goes high
and address information is placed on ports B and C
• PH2 has the same frequency as E-clock but it leads by 90 degrees; they do not overlap
• Falling edge of E-clock signifies the beginning of a clock cycle
EXTAL
E-clock
AS
1 Clock Cycle
PH2clock
9© 2003-2021 Roberto Muscedere, Images and text portions © 2003 Prentice Hall
I/O Interfacing and PortsI/O Interfacing and Ports• There can be several I/O
devices connected to the bus• Cannot be directly connected
to the bus; must use interfacing circuitry
• Interfacing may be required when voltage levels and timing are different
• Most μCs have many ports, which can be used to interface with other devices
10© 2003-2021 Roberto Muscedere, Images and text portions © 2003 Prentice Hall
Read and Write TimingRead and Write Timing• The MPU is constantly performing READ and WRITE
operations as it executes a program• READ:
• Fetches the op-code from memory• Fetches the operand from memory• Fetches the data from memory (LDAA, ADDA, SUBA)
• WRITE:• Transfers data from internal register to memory (STAA)• Transfers data from internal register to output device
• Read operations are more common since they are necessary to read the program instructions
11© 2003-2021 Roberto Muscedere, Images and text portions © 2003 Prentice Hall
Read OperationsRead Operations• Everything is in reference
to PH2, E-clock and AS1. Rising edge of AS
• R/W = 1• Address is set
2. Rising edge of PH2• PC is incremented
PH2clock
E-clock
AS
R/W
Port B
Valid data(D0–D7)
Port C High-ZHigh-ZHigh-Z
Old address byte(A8–A15)
GenerateR/W and
newaddress
IncrementPC
Enableselecteddevice
Latchdata into
MPU
New low-orderaddress byte is
latched. Fullnew address is
now on address bus.
New address byte(A0–A7)
1 READ Cycle
1
2
3
45
Invaliddata
New address byte(A8–A15)
12© 2003-2021 Roberto Muscedere, Images and text portions © 2003 Prentice Hall
Read OperationsRead Operations3. Falling edge of AS
• Low order address is fully latched
• Remove low order address from port C
4. Rising edge of E-clock• Enable selected devices
(RAM, ROM, I/O)• Port C becomes an input
PH2clock
E-clock
AS
R/W
Port B
Valid data(D0–D7)
Port C High-ZHigh-ZHigh-Z
Old address byte(A8–A15)
GenerateR/W and
newaddress
IncrementPC
Enableselecteddevice
Latchdata into
MPU
New low-orderaddress byte is
latched. Fullnew address is
now on address bus.
New address byte(A0–A7)
1 READ Cycle
1
2
3
45
Invaliddata
New address byte(A8–A15)
13© 2003-2021 Roberto Muscedere, Images and text portions © 2003 Prentice Hall
Read OperationsRead Operations5. Falling edge of E-clock
• Data on port C are latched to an internal register
• Memory must deliver a value within this time
• When E-clock goes low, external memory is disabled and bus goes to high-Z
PH2clock
E-clock
AS
R/W
Port B
Valid data(D0–D7)
Port C High-ZHigh-ZHigh-Z
Old address byte(A8–A15)
GenerateR/W and
newaddress
IncrementPC
Enableselecteddevice
Latchdata into
MPU
New low-orderaddress byte is
latched. Fullnew address is
now on address bus.
New address byte(A0–A7)
1 READ Cycle
1
2
3
45
Invaliddata
New address byte(A8–A15)
14© 2003-2021 Roberto Muscedere, Images and text portions © 2003 Prentice Hall
Write OperationsWrite Operations1. Rising edge of AS
• R/W = 0• Address is set
2. Rising edge of PH2• Nothing happens
Invaliddata
PH2clock
E-clock
AS
R/W
Port B
Valid data(D0–D7)
Port C High-Z
Old address byte(A8–A15)
GenerateR/W and
newaddress
No effecton PC
Enable MPUdata buffers
Latchdata intoselected
memory orI /O device.
New low-orderaddress byte is
latched. Fullnew address is
now on address bus.
New address byte(A0–A7)
New address byte(A8–A15)
1 WRITE Cycle
1
2
3
45
Invaliddata
Nextaddress
15© 2003-2021 Roberto Muscedere, Images and text portions © 2003 Prentice Hall
Write OperationsWrite Operations3. Falling edge of AS
• Low order address is fully latched
• Remove low order address from port C
4. Rising edge of E-clock• Enable selected devices
(RAM, ROM, I/O)• Port C becomes an output• Data is placed on port C
Invaliddata
PH2clock
E-clock
AS
R/W
Port B
Valid data(D0–D7)
Port C High-Z
Old address byte(A8–A15)
GenerateR/W and
newaddress
No effecton PC
Enable MPUdata buffers
Latchdata intoselected
memory orI /O device.
New low-orderaddress byte is
latched. Fullnew address is
now on address bus.
New address byte(A0–A7)
New address byte(A8–A15)
1 WRITE Cycle
1
2
3
45
Invaliddata
Nextaddress
16© 2003-2021 Roberto Muscedere, Images and text portions © 2003 Prentice Hall
Write OperationsWrite Operations5. Falling edge of E-clock
• Data on port C is latched into selected memory device
• Memory must commit this value within this time
Invaliddata
PH2clock
E-clock
AS
R/W
Port B
Valid data(D0–D7)
Port C High-Z
Old address byte(A8–A15)
GenerateR/W and
newaddress
No effecton PC
Enable MPUdata buffers
Latchdata intoselected
memory orI /O device.
New low-orderaddress byte is
latched. Fullnew address is
now on address bus.
New address byte(A0–A7)
New address byte(A8–A15)
1 WRITE Cycle
1
2
3
45
Invaliddata
Nextaddress
17© 2003-2021 Roberto Muscedere, Images and text portions © 2003 Prentice Hall
Sample Program for Bus ActivitySample Program for Bus Activity• Execute 2
instructions• ADDA and STAA• Requires 8 cycles
Memory Address
Contents Mnemonic Description
$C300$C301$C302
$BB$D7$5C
ADDA ADD contents of $D75C to Accumulator A
$C303$C304$C305
$B7$D2$50
STAA STORE contents of Accumulator A to $D250
$C306 ?? ???? Next op-code
18© 2003-2021 Roberto Muscedere, Images and text portions © 2003 Prentice Hall
Bus Activity During Program ExecutionBus Activity During Program Execution
E d e
AS
PH2
R/W
Addressbus
Fetchop code
Fetchoperandaddress
Fetchoperandaddress
Fetchop code
Fetchoperandaddress
Store [A]in memory
Fetchoperandaddress
Fetchdata toADDA
BB D7 5C B7 D2 3C502A
C300 C301 C302 C303 C304 D250C305D75C
1 1 1 1 1 011
1 2 3 5 6 874
Databus
b
a c
19© 2003-2021 Roberto Muscedere, Images and text portions © 2003 Prentice Hall
Bus Activity During Program ExecutionBus Activity During Program Execution• Read operation:
a. Rising edge of AS• MPU places PC/DAR on address bus• R/W=1
b. Rising edge of PH2• Increment PC
c. Falling edge of AS• Low order address is latched
d. Rising edge of E-clock• Memory device is enabled
e. Falling edge of E-clock• Latch data word from memory device
• Write operation:a. Rising edge of AS
• MPU places DAR on address bus• R/W=0
b. Rising edge of PH2• Nothing takes place
c. Falling edge of AS• Low order address is latched
d. Rising edge of E-clock• Memory device is enabled• Output is placed on data bus
e. Falling edge of E-clock• Latch data word to memory device
20© 2003-2021 Roberto Muscedere, Images and text portions © 2003 Prentice Hall
MPU Address Space AllocationMPU Address Space Allocation• When a Read or Write is
performed the MPU places an address on the bus
• The 68HC11 has 65536 (64K) available addresses
• This can be allocated into different types of memory (RAM, I/O, ROM)
• Figure on right is an example of what you might find in one of the 68HC11s
• This could be the memory available in expanded mode
21© 2003-2021 Roberto Muscedere, Images and text portions © 2003 Prentice Hall
OnOn--Chip Memory and I/OChip Memory and I/O• Various 68HC11s• All contain the same number of
internal registers, etc• Different memory configurations
• RAM and ROM locations are generally fixed while I/O can be moved (more on this later)
• Some have a different number of Timers, Serial interfaces, A-to-D converters as well as Pulse Width Modulators
• Some also operate at different voltages and speeds
A/D PWM Voltage Bus Freq.ROM RAM OTP EEP (CH/bit) (CH/bit) (V) (MHz)
HC11D0 0 192 0 0 SCI SPI 3/5 3
HC11D3 4Ki 192 0 0 SCI SPI 8/8 3/5 3
HC11E0 0 512 0 0 SCI SPI 8/8 3/5 3
HC11E1 0 512 0 512 SCI SPI 8/8 3/5 3HC11E2 0 256 0 2048 SCI SPI 8/8 5 2
HC11E9 12Ki 512 0 512 SCI SPI 8/8 3/5 3
HC11E20 20Ki 768 0 512 SCI SPI 8/8 5 3
HC11F1 0 1 0 512 SCI SPI 8/8 3/5 5
HC11K0 0 768 0 0 SCI SPI 8/8 4/8 or 2/16 3/5 4
HC11K1 0 768 0 640 SCI+ SPI 8/8 4/8 or 2/16 3/5 4HC11K4 24Ki 768 0 640 SCI+ SPI 8/8 4/8 or 2/16 3/5 4
HC11KS2 0 1 32Ki 640 SCI+ SPI 8/8 5 4
HC11KW1 0 768 0 640 SCI+ SPI 10/10 4/8 or 2/16 5 4
HC11P1 0 1 0 640 3x SCI SPI 8/8 4/8 or 2/16 5 4
HC11P2 32Ki 1 0 640 3x SCI SPI 8/8 4/8 or 2/16 5 4
HC711D3 0 192 4Ki 0 SCI SPI 5 3HC711E9 0 512 12Ki 512 SCI SPI 8/8 3/5 4
HC711E20 0 768 20Ki 512 SCI SPI 8/8 5 4
HC711KS2 0 1 32Ki 640 SCI+ SPI 8/8 5 4
Memory (Bytes)Product Serial
22© 2003-2021 Roberto Muscedere, Images and text portions © 2003 Prentice Hall
Memory PagesMemory Pages• The 64K of memory can be divided
into 256 blocks of 256 addresses• Each is called a page
• The upper 8-bits of an address can be referred to as the page number
• The lower 8-bits of an address can be referred to as the word number
• Upon startup, we can specify the location of the I/O in the 68HC11 by writing the desired page number to a fixed memory register
23© 2003-2021 Roberto Muscedere, Images and text portions © 2003 Prentice Hall
Memory Modules and Address DecodingMemory Modules and Address Decoding• The amount of memory in a μC depends on the intended application
• Once the memory arrangement is decided, an address decoding system must be put in place to enable the particular memories at the right time
• Generally higher-order memory addresses are used to dictate which memory is in use
24© 2003-2021 Roberto Muscedere, Images and text portions © 2003 Prentice Hall
Microcomputer Decoding ExampleMicrocomputer Decoding Example• Create an external circuit to
connect to a 68HC11 in expanded mode
• RAM is usually placed starting at address 0 to take advantage of “zero page” operations
• ROM is placed at the highest point since the startup information for the 68HC11 is located between $FFFC and $FFFF
• I/O is placed at $8000 to simplify decoding circuitry
25© 2003-2021 Roberto Muscedere, Images and text portions © 2003 Prentice Hall
RAM Decoding LogicRAM Decoding Logic• 4K x 8 RAM memory required• Use 1K x 8 components• Need to use a decoder
(74HC138) to determine which $0400 part of $0000-$0FFF is being addressed
• Use of an inverting input NAND gate for higher order address lines provides FULL address decoding
A6A7
A4A5
A2A3
A0A1
A14A15
A12A13
A10A11
A8A9
A13A12
A15A14
74HC373
Data Bus
Address Bus
Address Bus
Control Bus
To ROMand I/O
MC68HC11A8
OELE
Q6Q7
Q4Q5
Q2Q3
Q0Q1
D6D7
D4D5
D2D3
D0D1
D6D7
D4D5
D2D3
D0D1
AD6AD7
AD4AD5
AD2AD3
AD0AD1
PORTC
PORTB
VSS
EXTAL
XTAL
VDD
VDD
AS
R/W
E
A14A15
MODA4.7K
4.7K
4.7KMODB
A12A13
A10A11
A8A9
Connectjumper forTest Mode
Clock
MC34064
RESET
RESET
A9
A8
A6
A7
A4
A5
A2
A3
A0
A1
D6
D7
D4
D5
D2
D3
D0
D1
1K � 8RAM
Module-3R/W
CS
A9
A8
A6
A7
A4
A5
A2
A3
A0
A1
D6
D7
D4
D5
D2
D3
D0
D1
1K � 8RAM
Module-2R/W
CS
A9
A8
A6
A7
A4
A5
A2
A3
A0
A1
D6
D7
D4
D5
D2
D3
D0
D1
1K � 8RAM
Module-1R/W
CS
A8
A9
A6
A7
A4
A5
A2
A3
A0
A1
D6
D7
D4
D5
D2
D3
D0
D1
1K � 8RAM
Module-0R/W
CS
Y0Y1Y2
A10A11
E
Y3Y4Y5Y6Y7
A0A1A2
74HC138
G
G2G1
26© 2003-2021 Roberto Muscedere, Images and text portions © 2003 Prentice Hall
RAM Decoding LogicRAM Decoding Logic• Can use partial address
decoding• Address lines A14-A12 are
not considered for decoding• $0000-$0FFF is mirrored to
$1000, $2000, $3000, $4000, etc…
• This is acceptable as long as the programmer is aware that these memory addresses are shared
Y0Y1Y2
A10
Address Bus
Control Bus
A11A15
E
Y3Y4Y5Y6Y7
A0A1A2
74HC138
G
G2G1
27© 2003-2021 Roberto Muscedere, Images and text portions © 2003 Prentice Hall
ROM Decoding LogicROM Decoding Logic• 16K x 8 ROM memory required• Use 4K x 8 components• Need to use a decoder
(74HC138) to determine if $C000-$FFFF is addressed
• Use of an inverter on A15 as well as A14-A12 to determine which 4K page is being used
• /8000 is used later for I/O
Y0
R/W R/W
Y1Y2
A12
Address Bus
Data Bus
Control Bus
A13A14
A15
E
FromFig.5.14
Y3Y4Y5Y6Y7
A0A1A2
74HC138
GG2
G1
A11
A10
A8
A9
A6
A7
A4
A5
A2
A3
A0
A1
D6
D7
D4
D5
D2
D3
D0
D1
2732ROM-0
CE
OE
A11
A10
A8
A9
A6
A7
A4
A5
A2
A3
A0
A1
D6
D7
D4
D5
D2
D3
D0
D1
2732ROM-1
CE
OE
A11
A10
A8
A9
A6
A7
A4
A5
A2
A3
A0
A1
D6
D7
D4
D5
D2
D3
D0
D1
2732ROM-2
CE
OE
A11
A10
A8
A9
A6
A7
A4
A5
A2
A3
A0
A1
D6
D7
D4
D5
D2
D3
D0
D1
2732ROM-3
CEFxxx
Exxx
8xxx
Dxxx
Cxxx
R/W
ToFig.5.18
OE
28© 2003-2021 Roberto Muscedere, Images and text portions © 2003 Prentice Hall
I/O Decoding LogicI/O Decoding Logic• A large amount of I/O is usually not
necessary• In this example, we will only have 8 input
and 8 output bits• A2 decides on which to enable• Writing to $8000 puts data on the output I/O• Reading from $8004 reads data from the
input I/O• $8000 is mirrored to $8001, $8002, $8003,
$8008, $8009, etc…• $8004 is mirrored to $8005, $8006, $8007,
$800C, $800D, etc…
Address Bus
Data Bus
FromFig.5.14
A2
Control Bus
D0
D1
D2
D3
D4
D5
D6
D7
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
74HC377
74HC244
CLKE–clock
Output Port
IE
D7 D6 D4 D3 D2 D1 D0D5
I7 I6 I4 I3 I2 I1 I0I5
OE1
OE2
Input Port
FromFig.5.17
R/W
R/W
8xxx
1
2
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